CN203013717U - Three-dimensional integration power hybrid integrated circuit - Google Patents
Three-dimensional integration power hybrid integrated circuit Download PDFInfo
- Publication number
- CN203013717U CN203013717U CN2012206867331U CN201220686733U CN203013717U CN 203013717 U CN203013717 U CN 203013717U CN 2012206867331 U CN2012206867331 U CN 2012206867331U CN 201220686733 U CN201220686733 U CN 201220686733U CN 203013717 U CN203013717 U CN 203013717U
- Authority
- CN
- China
- Prior art keywords
- ceramic substrate
- integrated circuit
- hybrid integrated
- semiconductor chip
- convex
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
The utility model discloses a three-dimensional integration power hybrid integrated circuit. The integrated circuit comprises a tube base, a pedestal, pins, a ceramic substrate, a stop band, a conduction band/bonding region, a semiconductor chip, and a sheet-type component, which are all of an original hybrid integrated circuit. The stop band, the conduction band/bonding region, the semiconductor chip, and the sheet-type component are all integrated on the ceramic substrate. What make differences are that the used ceramic substrate is a convex-type ceramic substrate; the convex-type ceramic substrate is mounted on the pedestal of the tube base; more than one semiconductor chip and sheet-type component are integrated on a horizontal plane and two side surfaces of a protruding portion of the convex-type ceramic substrate; and an inner lead bonding mode is adopted to conduct the connection between the pins and the substrate and the connection between the semiconductor chip and the substrate, and the integration portion between the two side surfaces are connected through a via hole by metalized filling. The three-dimensional integration power hybrid integrated circuit is increased in maximum utilization power thereof, wide in application field, and particularly suitable for being used in fields of equipment system miniaturization and high reliability.
Description
Technical field
The utility model relates to hybrid integrated circuit, furthermore, relates to power hybrid integrated circuit, relates in particular to three-dimensional integrated power hybrid integrated circuit.
Background technology
In the integrated technology of original hybrid circuit, adopt two dimensional surface integrated technology or three-dimensional perpendicular stacked chips technology integrated of the mixing of ceramic substrate, semiconductor chip, other chip components and parts are directly filled be attached on thick film or film substrate, adopt again bonding wire (spun gold or Si-Al wire) to carry out Bonding, complete whole electrical equipment and connect, in specific atmosphere, Guan Ji and pipe cap are sealed to form at last.
original technology Main Problems is: owing to adopting the two dimensional surface integrated technology, semiconductor chip, other chip components and parts mount on ceramic substrate with the largest face direction, the Bonding of chip and substrate needs certain span from a solder joint to another solder joint, add the requirement that also needs on substrate according to physical circuit and make necessary thick film or film resistor, thick film or thin-film capacitor, thick film or thin film inductor etc., therefore, the chip attachment limited amount of substrate surface, integrated chip efficient is subjected to the impact of chip area, chip integration is difficult to improve.If adopt three-dimensional perpendicular stacked chips technology, during chip operation, produce the heat stack, increase the difficulty of heat radiation, the further lifting of restriction hybrid integrated circuit power.
In Chinese patent database, there are 3 to the integrated application part relevant with hybrid integrated circuit of three-dimensional, namely No. 200710176933.6 " preparation method of the hybrid integrated circuit structure of three-dimensional CMOS and molecule switching element ", No. 200710176934.0 " hybrid integrated circuit structure of three-dimensional CMOS and molecule switching element ", No. 200720046276.9 " substrate by dual-beam dual-wavelength laser three-dimensional micro-cladding is made the equipment of hybrid integrated circuit substrate ".But these patents and the utility model are also irrelevant, there is no at present the application part of three-dimensional integrated power hybrid integrated circuit.
Summary of the invention
The purpose of this utility model is to provide three-dimensional integrated power hybrid integrated circuit, the largest face of all chips or other chip components and parts and substrate or base are filled subsides, guarantee that all chips or other chip components and parts carry out contacting of maximum area with substrate or base, increasing heat radiation area, quickening radiating rate, the maximum that reaches the bring to power hybrid integrated circuit is used power.
The three-dimensional integrated power hybrid integrated circuit that the designer provides has Guan Ji, base, pin, ceramic substrate, stopband, conduction band/bonding region, semiconductor chip and the chip components and parts of original power hybrid integrated circuit, stopband, conduction band/bonding region, semiconductor chip and chip components and parts all are integrated on ceramic substrate, different is: ceramic substrate used is the convex ceramic substrate, and the convex ceramic base is on chip to be attached on the pipe base seat; Be integrated with more than one semiconductor chip and chip components and parts at convex ceramic substrate horizontal plane and bossing two sides; Stopband and conduction band are used respectively lead and pin bonding, and semiconductor chip is also filled with the mutual bonding of lead and by through hole, metallization and connected with lead and stopband bonding, vertical each integrated components and parts in two sides.
Above-mentioned convex ceramic substrate has the back face metalization layer.
Above-mentioned through hole is positioned at the bossing of convex ceramic substrate.
Above-mentioned conduction band, stopband are thick film or film conduction band, thick film or film stopband.
Above-mentioned chip components and parts do not comprise semiconductor chip.
The utility model method has following characteristics: 1. carry out simultaneously chip or other chip components and parts at the horizontal plane of convex ceramic substrate and the two sides of bossing, realize that all chips or other chip components and parts carry out contacting of maximum area with substrate or base, increasing heat radiation area, quickening radiating rate reach the maximum purpose of using power of bring to power hybrid integrated circuit; 2. carry out simultaneously chip or other chip components and parts at the horizontal plane of convex ceramic substrate and the two sides of bossing, realize that density three-dimensional is integrated, greatly improve the integrated level of hybrid integrated circuit; 3. can integrated more semiconductor chip, other chip components and parts, thereby can integrated more function; 4. can reduce the complete machine application system and use the quantity of electronic devices and components, thereby reduce the volume of complete machine, improve the reliability of application system; 5. adopt High Density Integration, greatly shorten wire length, can further improve operating frequency and the reliability of hybrid integrated circuit.
Such devices with the utility model production is widely used in the fields such as space flight, aviation, boats and ships, precision instrument, communication, Industry Control, is specially adapted to change system miniaturization, highly reliable field, has wide market prospects and application space.
Description of drawings
Fig. 1 is the basic schematic diagram of pipe, and Fig. 2 is hybrid integrated circuit schematic diagram of the present utility model, and Fig. 3 is ceramic substrate enlarged diagram of the present utility model, and Fig. 4 is ceramic substrate through hole of the present utility model, printing conduction band, stopband and back face metalization enlarged diagram.
In figure, 1 is pin, and 2 is base, and 3 is Guan Ji, and 4 is lead, and 5 is stopband, and 6 is semiconductor chip, and 7 is conduction band/bonding region, and 8 is vertical integration section, and 9 is chip components and parts, and 10 is the convex ceramic substrate, and 11 is the back face metalization layer, and 12 is through hole.
Embodiment
Embodiment:
A three-dimensional integrated power thick film hybrid integrated circuit, as shown in Fig. 1-4, base 2, pipe base 3, pin one, ceramic substrate, stopband 5, conduction band/bonding region 7, chip 6 and chip components and parts 9 with original thick film hybrid integrated circuit, stopband 5, conduction band/bonding region 7, semiconductor chip 6 and chip components and parts 9 all are integrated on ceramic substrate, different is: ceramic substrate used is convex ceramic substrate 10, and convex ceramic substrate 10 dresses are attached on the base 2 of pipe base 3; Be integrated with more than one semiconductor chip 6 and chip components and parts 9 at convex ceramic substrate 10 horizontal planes and bossing two vertical side; Stopband 5 and conduction band are used respectively lead 4 and pin one bonding, and semiconductor chip 6 use leads 4 and stopband 5 bondings, the vertical integration section 8 in the two sides of bossing are also filled with the mutual bonding of lead 4 and by through hole 12, metallization and connected.Convex ceramic substrate 10 has the back face metalization layer.
Claims (3)
1. three-dimensional integrated power hybrid integrated circuit, base (2) with original hybrid integrated circuit, Guan Ji (3), pin (1), ceramic substrate, stopband (5), conduction band/bonding region (7), chip (6) and chip components and parts (9), stopband (5), conduction band/bonding region (7), semiconductor chip (6) and chip components and parts (9) all are integrated on ceramic substrate, it is characterized in that: ceramic substrate used is convex ceramic substrate (10), convex ceramic substrate (10) dress is attached on the base (2) of Guan Ji (3), be integrated with more than one semiconductor chip (6) and chip components and parts (9) at convex ceramic substrate (10) horizontal plane and bossing two vertical side, stopband (5) and conduction band are used respectively lead (4) and pin (1) bonding, semiconductor chip (6) is filled by through hole (12), metallization and is connected with lead (4) and stopband (5) bonding, the vertical integration sections in two sides (8).
2. hybrid integrated circuit as claimed in claim 1, is characterized in that described convex ceramic substrate (10) has the back face metalization layer.
3. hybrid integrated circuit as claimed in claim 1, is characterized in that described through hole (12) is positioned at the bossing of convex ceramic substrate (10).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012206867331U CN203013717U (en) | 2012-12-12 | 2012-12-12 | Three-dimensional integration power hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012206867331U CN203013717U (en) | 2012-12-12 | 2012-12-12 | Three-dimensional integration power hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203013717U true CN203013717U (en) | 2013-06-19 |
Family
ID=48605282
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012206867331U Expired - Fee Related CN203013717U (en) | 2012-12-12 | 2012-12-12 | Three-dimensional integration power hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203013717U (en) |
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2012
- 2012-12-12 CN CN2012206867331U patent/CN203013717U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130619 Termination date: 20181212 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |