CN203012131U - Variable sequence radar pulse generating circuit - Google Patents
Variable sequence radar pulse generating circuit Download PDFInfo
- Publication number
- CN203012131U CN203012131U CN 201220673332 CN201220673332U CN203012131U CN 203012131 U CN203012131 U CN 203012131U CN 201220673332 CN201220673332 CN 201220673332 CN 201220673332 U CN201220673332 U CN 201220673332U CN 203012131 U CN203012131 U CN 203012131U
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- radar pulse
- radar
- pulse generating
- generating circuit
- zero clearing
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- Expired - Lifetime
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Abstract
The utility model relates to a variable sequence radar pulse generating circuit. The variable sequence radar pulse generating circuit comprises an address generation circuit, one or more EPROM memories connected with the address generation circuit and latch registers corresponding to EPROM memory outputs, wherein output ends of the latch registers comprise multiple data bits, each data bit correspondingly outputs a pulse, one of the data bits is connected with a zero clearing input end of a zero clearing device, and an output end of the zero clearing device is connected with a zero clearing end of the address generation circuit. According to the variable sequence radar pulse generating circuit, change of a radar sequence can be realized by modifying content of the EPROMs, and software adjustment for various sequence relations can be carried out according to a practical work state of an integral radar. System performances are convenient to improve by improving timing frequency and employing the EPROM memories with faster speed.
Description
Technical field
The utility model belongs to the airborne control computer circuit design field, is specifically related to the variable radar pulse of a kind of sequential and produces circuit.
Background technology
Early stage radar Sequential Circuit Design adopts logic chip on a small scale, if will change sequential after the hard wire design is completed, not only will change the hardware wiring and also will debug on this basis checking, and the design cycle is long, maintainability is low.
Summary of the invention
Change inconvenient in order to solve present radar sequential circuit sequential, the technical matters that design cycle is long, maintainability is low, the utility model provide a kind of radar pulse that can adjust various sequential relationships according to the state of radar complete machine real work at any time to produce circuit.
Technical solution of the present utility model is as follows:
The variable radar pulse of a kind of sequential produces circuit, its special character is: the one or more eprom memories that comprise address production electric circuit, are connected with address production electric circuit, the latch corresponding with eprom memory output, the output terminal of described latch comprises a plurality of data bit, pulse of the corresponding output of described each data bit, one of them data bit is connected with the zero clearing input end of clear device, and the output terminal of described clear device is connected with the address production electric circuit clear terminal.
The content of above-mentioned eprom memory is write by programmable device.
Address above mentioned produces the counter that circuit comprises a plurality of cascades.
Above-mentioned counter is the tetrad counter.
The quantity of above-mentioned counter is 4, and the quantity of above-mentioned eprom memory is 6, and the quantity of above-mentioned latch is 6.
Above-mentioned clear device is and door.
The beneficial effects of the utility model:
1, the utility model radar pulse produces circuit, and the change of radar sequential realizes by the content of revising EPROM, can be at any time according to the state of radar complete machine real work, various sequential relationships be carried out the software adjustment.By to the raising of toggle rate and the eprom memory of employing faster speed, easily system performance is promoted.
2, the utility model method for designing cycle short, maintainable high, easy control accuracy; Get final product if only need to change the content of EPROM in the time of will changing pulsion phase for the delay of original pulse and the pulsewidth of self simultaneously, need not to change the hardware wiring, upgradability is good.
Description of drawings
Fig. 1 is radar timing pulse circuit design concept figure.
Embodiment
As shown in Figure 1, the variable radar pulse of a kind of sequential produces circuit, comprise by the address production electric circuit of four SNJ54LS161AJ chip cascades, 6 CY7C271A eprom memories, each CY7C271A storer can produce 8 time sequential pulse signals, and six CY7C271A can produce 48 time sequential pulse signals, six SNJ54LS374J latchs and clear device.
principle of work: clock signal is as the input signal of counter, come often that clock number of addresses is corresponding increases progressively one, counter is transferred to eprom memory by address wire with address signal, EPROM is according to writing the corresponding output of content (admittedly depositing) pulse, pulse of the corresponding output of a data bit of EPROM, the latch of rear class latchs corresponding data bit at the rising edge of each pulse, avoid waveform burr to occur, the working pulse that the corresponding needs of the output of a data bit of latch produce, one of them data bit is used for making counter again from 0 counting, circulation produces the EPROM address.
The frequency of supposing counter is 6MHz, that is to say that the precision of admittedly depositing each output is 1/6MHz=0.166666us.Make one when the relative radar pulse of needs and postpone 120.83us, during the pulse of pulsewidth 1us, 120.83/0.166666=725,1/0.166666=6 a data bit of admittedly depositing this moment is exported 725 low levels 0 and then is exported 6 high level 1 and just can produce the positive pulse that postpones 120.83us pulsewidth 1us.The height state of data bit shows as the high-low level of continuous signal pulse.Revise pulse parameter as long as revise corresponding data of admittedly depositing interior curing.
Claims (6)
1. the variable radar pulse of sequential produces circuit, it is characterized in that: the one or more eprom memories that comprise address production electric circuit, are connected with address production electric circuit, the latch corresponding with eprom memory output, the output terminal of described latch comprises a plurality of data bit, pulse of the corresponding output of described each data bit, one of them data bit is connected with the zero clearing input end of clear device, and the output terminal of described clear device is connected with the address production electric circuit clear terminal.
2. the variable radar pulse of sequential according to claim 1 produces circuit, and it is characterized in that: the content of described eprom memory is write by programmable device.
3. the variable radar pulse of sequential according to claim 1 and 2 produces circuit, and it is characterized in that: described address production electric circuit comprises the counter of a plurality of cascades.
4. the variable radar pulse of sequential according to claim 3 produces circuit, and it is characterized in that: described counter is the tetrad counter.
5. the variable radar pulse of sequential according to claim 4 produces circuit, and it is characterized in that: the quantity of described counter is 4, and the quantity of described eprom memory is 6, and the quantity of described latch is 6.
6. the variable radar pulse of sequential according to claim 5 produces circuit, and it is characterized in that: described clear device is and door.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220673332 CN203012131U (en) | 2012-12-07 | 2012-12-07 | Variable sequence radar pulse generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220673332 CN203012131U (en) | 2012-12-07 | 2012-12-07 | Variable sequence radar pulse generating circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203012131U true CN203012131U (en) | 2013-06-19 |
Family
ID=48603713
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220673332 Expired - Lifetime CN203012131U (en) | 2012-12-07 | 2012-12-07 | Variable sequence radar pulse generating circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203012131U (en) |
-
2012
- 2012-12-07 CN CN 201220673332 patent/CN203012131U/en not_active Expired - Lifetime
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130619 |