CN202977388U - Novel silicon wafer bearing device used in growth process of wafer silicon dioxide back-seal membrane - Google Patents
Novel silicon wafer bearing device used in growth process of wafer silicon dioxide back-seal membrane Download PDFInfo
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- CN202977388U CN202977388U CN 201220651780 CN201220651780U CN202977388U CN 202977388 U CN202977388 U CN 202977388U CN 201220651780 CN201220651780 CN 201220651780 CN 201220651780 U CN201220651780 U CN 201220651780U CN 202977388 U CN202977388 U CN 202977388U
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Abstract
The utility model provides a novel silicon wafer bearing device used in the growth process of a wafer silicon dioxide back-seal membrane. The device comprises a rounded upper base, a rounded lower base and three bearing rods installed between the upper base and the lower base, wherein a plurality of bearing grooves are uniformly distributed on each bearing rod. With the silicon wafer bearing device, wafer single-sided contact growth of silica back-seal membrane on a horizontal furnace can be realized, no mark is left on the edge of the grown silica back-seal membrane, the entire surface of the membrane is uniform and consistent; and membrane quality is significantly enhanced.
Description
Technical field
The utility model relates to a kind of novel silicon wafer carrying device that is used for wafer silicon dioxide back seal film growth course.
Background technology
Along with developing rapidly of domestic IC industry, the demand of silicon wafer substrate material is also increasing, quality requirement is more and more stricter, in order to prevent that the heavy doping silicon chip from prolonging outdiffusion and the autodoping that causes impurity in production process outside, introduced back of the body envelope technique, back of the body envelope is normally at the back side of wafer substrate sheet growth one deck inside front cover silicon oxide film, due to the diffusion coefficient of impurity in the inside front cover silica much smaller than the diffusion coefficient in silicon, therefore can carry out effective shutoff to the impurity in the wafer substrate sheet, as the term suggests be referred to as back of the body envelope.
Although silica membrane back of the body envelope effect is better, but when introducing inside front cover silica back of the body envelope technique, the growth of silica membrane also becomes a constantly problem of research, relatively more commonly used is to adopt the mode of low-pressure chemical vapor phase deposition (LPCVD) to grow now, generally adopts the Horizontal type stove.but in growth course, traditional mode is to adopt the horizontal bearing device, silicon chip stands up on bogey, the mean level bogey needs four groove rods to fix silicon chip, the wafer two sides, position that silicon chip contacts with bogey in growth course so all can be variant, although the wafer frontside marking is on our not impact, but wafer rear is namely carried on the back the marking of 3～5cm of front cover and can't be overcome, not only have a strong impact on the uniformity of film, in diaphragm, uniformity is in 5% left and right, between whole stove sheet, uniformity is in 10% left and right, and when outward appearance detects, four markings on surface have a strong impact on outward appearance, yield is in 70% left and right, can the wafer utilization rate of rear road IC technique be reduced simultaneously, can not satisfy technological requirement fully.
The utility model content
The purpose of this utility model is to provide a kind of novel silicon wafer carrying device that is used for wafer silicon dioxide back seal film growth course, to grow the silicon dioxide back seal film of high-quality more.
For achieving the above object, the utility model is by the following technical solutions:
A kind of novel silicon wafer carrying device that is used for wafer silicon dioxide back seal film growth course comprises circular top base and bottom base, and is arranged on three carrying rods between upper and lower pedestal, upper several bearing grooves that evenly distribute of each carrying rod.
Between described carrying rod and described top base, angulation is 10～20 degree.
Each carrying rod is provided with 25 bearing grooves, and between the opening of described bearing groove and carrying rod, angulation is 75～85 degree.
The groove depth of described bearing groove is 4～6mm, and separation is 4.5～5.5mm, and bottom land is wide is 0.6～0.9mm.
The section radius of described carrying rod is 5～6mm.
The radius of described top base and bottom base is respectively 105～155mm.
Be respectively equipped with two locating bars on described upper and lower pedestal, the height of those locating bars is 10～15cm, and the spacing between two locating bars on same pedestal is 8～12cm.
The material of described silicon wafer carrying device is the electron level quartz material.
The utility model has the advantage of:
Silicon wafer carrying device of the present utility model has changed the vertical modes of emplacement of traditional wafer, changing wafer level into places, because so horizontal positioned only has wafer frontside and contacts with bogey groove lower surface, changed original double contact, the silicon dioxide film back of the body front cover that grows does not have the marking, and surface uniform is consistent, and in the thickness sheet, uniformity is in 1%, between whole stove sheet, uniformity is in 3%, and outward appearance yield 100% is qualified; Traditional every stove of growth pattern 100 wafer of can only growing simultaneously, adopt the every stove of silicon wafer carrying device of the present utility model 150 wafer of can growing, production capacity promotes 50%, cost 30%, utilance improves 10% in the IC use procedure of rear road simultaneously, has really reached the purpose of work simplification, quality lifting and cost.
Description of drawings
Fig. 1 is the front view of silicon wafer carrying device of the present utility model.
Fig. 2 is the enlarged drawing at A place in Fig. 1.
Fig. 3 is the end view of silicon wafer carrying device of the present utility model.
Fig. 4 is the enlarged drawing at A1 place in Fig. 3.
Fig. 5 is the vertical view of silicon wafer carrying device of the present utility model.
Fig. 6 is the structural representation of the chemical vapour deposition (CVD) Horizontal type stove of installation silicon wafer carrying device of the present utility model.
Fig. 7 is for adopting the process chart of silicon wafer carrying device growth silicon dioxide back seal film of the present utility model.
Embodiment
As shown in Fig. 1～3, silicon wafer carrying device of the present utility model comprises circular top base 1 and bottom base 2, and is arranged on three carrying rods 3 between upper and lower pedestal, upper several bearing grooves 4 that evenly distribute of each carrying rod.Between described carrying rod 3 and described top base 1, angulation is 10～20 degree.Each carrying rod 3 is provided with 25 bearing grooves 4, and between the opening of described bearing groove 4 and carrying rod 3, angulation is 75～85 degree.The groove depth of described bearing groove 4 is 4～6mm, and separation is 4.5～5.5mm, and bottom land is wide is 0.6～0.9mm.The section radius of described carrying rod 3 is 5～6mm.The radius of described top base 1 and bottom base 2 is respectively 105～155mm.Be respectively equipped with two locating bars 5 on described upper and lower pedestal, the height of those locating bars is 10～15cm, and the spacing between two locating bars on same pedestal is 8～12cm.
As shown in Fig. 4～5, when adopting above-mentioned silicon wafer carrying device growth silicon dioxide back seal film, several silicon wafer carrying devices are arranged in the deposition chamber of chemical vapour deposition (CVD) Horizontal type stove 6, then silicon chip is imported those silicon wafer carrying devices; Set the temperature and pressure in deposition chamber, set the flow of tetraethoxysilane (TEOS) steam, control sedimentation time; After deposition is completed, carry out cavity and purify, take out silicon chip, measure in sheet and uniformity between sheet; Whole stove silicon chip carries out appearance surfaces and detects, and calculates yield.
Embodiment 1
Adopt device for piling sheets that silicon chip is managed, the silicon chip plane of reference is downward; Silicon chip is imported in 6 silicon wafer carrying devices with rewinder, and each silicon wafer carrying device can load 25 4 inches wafers, amounts to 150; 6 bogeys that are mounted with 150 silicon chips are put into horizontal stove, adjusting the TEOS flow is 100SCCM, temperature is 650 ℃, deposition pressure is 550MT, grow, growth time is 90min, take out silicon chip after growth, the test thickness is 5200～5400 dusts, in sheet, uniformity (uniformity test is fully by the SEMI standard) is 0.52% (requirement 10%), between 100 silicon chip sheets, uniformity is 1.52% (requiring 10%), 150 silicon chips outward appearance under major light is detected, whole surface uniform is consistent, without the marking, qualification rate 100%, meet the demands fully.
adopt device for piling sheets that silicon chip is managed, the silicon chip plane of reference is downward, silicon chip is imported in 6 silicon wafer carrying devices with rewinder, and each silicon wafer carrying device can load 25 5 inches wafers, amounts to 150, 6 bogeys that are mounted with 150 silicon chips are put into horizontal stove, adjusting the TEOS flow is 150SCCM, temperature is 668 ℃, deposition pressure is 700MTORR (millitorr), grow, growth time is 90min, take out silicon chip after growth, the test thickness is 5300～5500 dusts, in sheet, uniformity (uniformity test is fully by the SEMI standard) is 0.46% requirement 10%), between 100 silicon chip sheets, uniformity is 1.23% (requiring 10%), 150 silicon chips outward appearance under major light is detected, whole surface uniform is consistent, without the marking, qualification rate 100%, meet the demands fully.
adopt device for piling sheets that silicon chip is managed, the silicon chip plane of reference is downward, silicon chip is imported in 6 silicon wafer carrying devices with rewinder, and each silicon wafer carrying device can load 25 6 inches wafers, amounts to 150, 6 bogeys that are mounted with 150 silicon chips are put into horizontal stove, adjusting the TEOS flow is 150SCCM, temperature is 668 ℃, deposition pressure is 700MTORR (millitorr), grow, growth time is 90min, take out silicon chip after growth, the test thickness is 5300～5500 dusts, in sheet, uniformity (uniformity test is fully by the SEMI standard) is 0.86% (requirement 10%), between 100 silicon chip sheets, uniformity is 2.01% (requiring 10%), 150 silicon chips outward appearance under major light is detected, whole surface uniform is consistent, without the marking, qualification rate 100%, meet the demands fully.
Adopt device for piling sheets that silicon chip is managed, the silicon chip plane of reference is downward; Silicon chip is imported in 6 silicon wafer carrying devices with rewinder, and each silicon wafer carrying device can load 25 4 inches wafers, amounts to 150; 6 bogeys that are mounted with 150 silicon chips are put into horizontal stove, adjusting the TEOS flow is 160SCCM, temperature is 680 ℃, deposition pressure is 750MT, grow, growth time is 90min, take out silicon chip after growth, the test thickness is 5500～5700 dusts, in sheet, uniformity (uniformity test is fully by the SEMI standard) is 0.33% (requirement 10%), between 100 silicon chip sheets, uniformity is 1.41% (requiring 10%), 150 silicon chips outward appearance under major light is detected, whole surface uniform is consistent, without the marking, qualification rate 100%, meet the demands fully.
Claims (8)
1. novel silicon wafer carrying device that is used for wafer silicon dioxide back seal film growth course, it is characterized in that, comprise circular top base and bottom base, and be arranged on three carrying rods between upper and lower pedestal, upper several bearing grooves that evenly distribute of each carrying rod.
2. silicon wafer carrying device according to claim 1, is characterized in that, between described carrying rod and described top base, angulation is 10～20 degree.
3. silicon wafer carrying device according to claim 1, is characterized in that, each carrying rod is provided with 25 bearing grooves, and between the opening of described bearing groove and carrying rod, angulation is 75～85 degree.
4. silicon wafer carrying device according to claim 1, is characterized in that, the groove depth of described bearing groove is 4～6mm, and separation is 4.5～5.5mm, and bottom land is wide is 0.6～0.9mm.
5. silicon wafer carrying device according to claim 1, is characterized in that, the section radius of described carrying rod is 5～6mm.
6. silicon wafer carrying device according to claim 1, is characterized in that, the radius of described top base and bottom base is respectively 105～155mm.
7. silicon wafer carrying device according to claim 1, is characterized in that, is respectively equipped with two locating bars on described upper and lower pedestal, and the height of those locating bars is 10～15cm, and the spacing between two locating bars on same pedestal is 8～12cm.
8. silicon wafer carrying device according to claim 1, is characterized in that, the material of described silicon wafer carrying device is the electron level quartz material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220651780 CN202977388U (en) | 2012-11-30 | 2012-11-30 | Novel silicon wafer bearing device used in growth process of wafer silicon dioxide back-seal membrane |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220651780 CN202977388U (en) | 2012-11-30 | 2012-11-30 | Novel silicon wafer bearing device used in growth process of wafer silicon dioxide back-seal membrane |
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| Publication Number | Publication Date |
|---|---|
| CN202977388U true CN202977388U (en) | 2013-06-05 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220651780 Expired - Lifetime CN202977388U (en) | 2012-11-30 | 2012-11-30 | Novel silicon wafer bearing device used in growth process of wafer silicon dioxide back-seal membrane |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103855062A (en) * | 2012-11-30 | 2014-06-11 | 有研半导体材料股份有限公司 | Novel silicon wafer bearing device applied to wafer silicon dioxide back sealing membrane growth process, and growth method |
-
2012
- 2012-11-30 CN CN 201220651780 patent/CN202977388U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103855062A (en) * | 2012-11-30 | 2014-06-11 | 有研半导体材料股份有限公司 | Novel silicon wafer bearing device applied to wafer silicon dioxide back sealing membrane growth process, and growth method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: GRINM ADVANCED MATERIALS CO., LTD. Free format text: FORMER NAME: GRINM SEMICONDUCTOR MATERIALS CO., LTD. |
|
| CP01 | Change in the name or title of a patent holder |
Address after: 100088 Beijing city Xicheng District Xinjiekou Avenue No. 2 Patentee after: GRINM ADVANCED MATERIALS CO.,LTD. Address before: 100088 Beijing city Xicheng District Xinjiekou Avenue No. 2 Patentee before: GRINM SEMICONDUCTOR MATERIALS Co.,Ltd. |
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| ASS | Succession or assignment of patent right |
Owner name: GRINM SEMICONDUCTOR MATERIALS CO., LTD. Free format text: FORMER OWNER: GRINM ADVANCED MATERIALS CO., LTD. Effective date: 20150611 |
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| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20150611 Address after: 101300 Beijing city Shunyi District Shuanghe Linhe Industrial Development Zone on the south side of the road Patentee after: GRINM SEMICONDUCTOR MATERIALS Co.,Ltd. Address before: 100088 Beijing city Xicheng District Xinjiekou Avenue No. 2 Patentee before: GRINM ADVANCED MATERIALS CO.,LTD. |
|
| CP01 | Change in the name or title of a patent holder |
Address after: 101300 south side of Shuanghe Road, Linhe Industrial Development Zone, Shunyi District, Beijing Patentee after: Youyan semiconductor silicon materials Co.,Ltd. Address before: 101300 south side of Shuanghe Road, Linhe Industrial Development Zone, Shunyi District, Beijing Patentee before: GRINM SEMICONDUCTOR MATERIALS Co.,Ltd. |
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| CP01 | Change in the name or title of a patent holder | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130605 |
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| CX01 | Expiry of patent term |