CN202977378U - Micropore type pressure welding clamp for QFN-DFN integrated circuit package - Google Patents
Micropore type pressure welding clamp for QFN-DFN integrated circuit package Download PDFInfo
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- CN202977378U CN202977378U CN 201220678510 CN201220678510U CN202977378U CN 202977378 U CN202977378 U CN 202977378U CN 201220678510 CN201220678510 CN 201220678510 CN 201220678510 U CN201220678510 U CN 201220678510U CN 202977378 U CN202977378 U CN 202977378U
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- micropores
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- lead frame
- dfn
- pressing plate
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Abstract
The utility model relates to a micropore type pressure welding clamp for quad flat no-lead package (QFN)-DFN integrated circuit package. The provided clamp comprises a heating block (1) and a pressing plate (2); and when the clamp is used, the heating block (1), a lead frame (3) and the pressing plate (2) are successively superposed from bottom to top. And the clamp is characterized in that the heating block (1) has a body (4); a vacuum absorption hole (5) and a plurality of micropores (6) are arranged on the body (4), wherein the aperture of each of the micropores (6) is 0.15 to 0. 17 millimeters; the plurality of micropores (6) are communicated with the vacuum absorption hole (5); and the arrangement positions of the micropores (6) on the body (4) correspond to positions of wafer carriers on the lead frame (3). According to the scheme, the pressure welding clamp is suitable for application to the wiring and bonding process of a QFN-DFN packaging technology-based integrated circuit product with a small wafer carrier interval. And phenomena of floating, bad wiring and pseudo soldering during the wiring and boding process can be avoided; and the production efficiency can be improved and the effect is good.
Description
Technical field
The utility model belongs to the integrated antenna package field, is specially a kind of QFN, and DFN integrated antenna package pore type bonding clamper is applicable to the little QFN in interval of silicon wafer carrier, the routing bonding process in DFN packaging technology integrated circuit (IC) products encapsulation process.
Background technology
Wafer level packaging is a step during integrated circuit (IC) encapsulation is made, being about to crystal grain is placed on the silicon wafer carrier of lead frame, solder joint on crystal grain is seen through superfine gold thread be connected to pin within lead frame, and then the circuit signal of integrated circuit crystal grain is transferred to the external world.Namely carry out the operations such as sealer, cutting, bending, test after wafer level packaging.Will use bonding clamper during wafer level packaging, bonding clamper comprises heat block (be base, also need heating process during because of common encapsulation) and pressing plate, is provided with window frame body on pressing plate, and offers the suction vacuum hole on heat block.during encapsulation, heat block, lead frame and pressing plate are stacked successively from lower to upper, place crystal grain on the silicon wafer carrier on lead frame, following heat block holds lead frame through inhaling vacuum hole, pressing plate is simultaneously pushed down lead frame downwards, the corresponding crystal grain in window frame body position on pressing plate, lead frame under the acting in conjunction of the suction of heat block and platen pressure and on silicon wafer carrier be positioned, crystal grain exposes from the window of window frame body, the frame section of window frame body pushes down the pin of crystal grain week side, adopt the welding procedure such as ultrasonic bonding that the solder joint on crystal grain is connected with pin within lead frame, this process namely claims the routing bonding.In the routing bonding process, must guarantee that pressing plate can not contact silicon wafer carrier, more the crystal grain that carries on silicon wafer carrier can not be contacted, otherwise the welding between crystal grain and pin will be affected, cause product rejection.
QFN(Quad Flat No-lead Package), DFN is all packaging technologies of integrated circuit, refer to bilateral or the quad flat Lead-free in Electronic Packaging, it has gull wing lead-in wire unlike traditional SOIC and TSOP encapsulation, the silicon wafer carrier interval is little, conductive path between its inner pin and pad is short, in coefficient of self-inductance and packaging body, the cloth line resistance is very low, therefore can provide remarkable electrical property, has volume little, thickness is little, lightweight, the characteristics that electrical property and hot property are outstanding, the Electronic Packaging ghost effect promotes, be fit to very much be applied in mobile phone, digital camera, on the high-density printed circuit board of PDA and other portable miniaturized electronicss.DFN, on the lead frame of QFN packaging technology integrated circuit (IC) products, usually several silicon wafer carriers are pressed the vehicle group of the some row of ranks one-tenth several rows arranged sequentially in length and breadth, in vehicle group, the size of space of adjacent wafers carrier is very little, for avoiding pressing plate contact silicon wafer carrier, window frame body on the pressing plate of existing routing bonding bonding clamper is a large window frame, the corresponding whole vehicle group of this large window frame, all silicon wafer carriers on vehicle group and the crystal grain of carrying thereof expose from the window of large window frame, the frame section of large window frame can only push down the pin of each silicon wafer carrier side at position, vehicle group edge, and the suction vacuum hole aperture on heat block is larger, can not be stable hold lead frame and on silicon wafer carrier, obviously, this structure will cause between the adjacent single silicon wafer carrier of the row of vehicle group inside and row (and row be listed as) and lack pressing, the pressing effect is bad, cause the routing bonding process to float, routing is bad, rosin joint etc., finally cause product rejection.
the applicant of this patent scheme has designed a kind of QFN for this kind situation, DFN integrated antenna package line type bonding clamper, referring to Fig. 1, comprise base (heat block 1) and pressing plate 2, establish window frame body on pressing plate 2, this window frame body is a bay window shape structure, have sidepiece and bottom, its bottom is to arrange in length and breadth by some vertical elements the plane grid that connects to form, its sidepiece is spaced by some back-up blocks and forms, during use the vertical element correspondence of plane grid be pressed in lead frame 3 up with the row, between the single silicon wafer carrier 7 of row and row, push down pin 9, carry out the routing bonding, can not touch silicon wafer carrier 7 and the impact welding.But the plane grid of this scheme generally is unfit to do widely, for example when the columns of plane grid is accomplished to surpass three, four row, the intensity of plane grid, evenness etc. will variation, therefore can only pressure weldings three under impulse stroke, four row silicon wafer carriers 7, and efficient is low.In addition, the plane grid integral body effect of a window frame body under an impulse stroke, therefore if on plane grid, certain is damaged, can cause under this window frame body effect lead frame 3 and above silicon wafer carrier 7 and crystal grain all scrap, cause the integral production cost to increase.
The utility model content
The utility model provides a kind of QFN, DFN integrated antenna package pore type bonding clamper, be applicable to the silicon wafer carrier little QFN in interval, the routing bonding process of DFN packaging technology integrated circuit (IC) products, avoid the floating of routing bonding process, routing is bad, rosin joint etc., and can enhance productivity, effective.
For achieving the above object, the technical solution adopted in the utility model is: a kind of QFN, DFN integrated antenna package pore type bonding clamper, comprise heat block and pressing plate, during use, heat block, lead frame and pressing plate are stacked successively from lower to upper, and described heat block has a body, offer to inhale vacuum hole and some micropores on this body, the aperture of micropore is 0.15～0.17 millimeter, and some micropores all are communicated with described suction vacuum hole; The position of some micropores silicon wafer carrier on the installation position on body and lead frame is corresponding.
Related content in technique scheme is explained as follows:
1, in such scheme, described " upper and lower " is that the direction during according to pressure welding is benchmark.
2, in such scheme, the hole depth of described micropore is 5 times of its aperture.
3, in such scheme, offer one on the body of described heat block and inhale vacuum passage, described some micropores are inhaled vacuum passage through this and are communicated with the suction vacuum hole.
The utility model operation principle is: offer on the heat block of bonding clamper and inhale vacuum hole and some micropores, these some micropores all are communicated with the suction vacuum hole, and the aperture of micropore is 0.15～0.17 millimeter.During wafer level packaging, heat block, lead frame and pressing plate are stacked successively from lower to upper, inhale vacuum hole on heat block and are communicated with vacuum pump, inhale vacuum and hold lead frame through micropore.The position of some micropores silicon wafer carrier on the installation position on body and lead frame is corresponding.Because micropore size is very little, be far smaller than the size of the silicon wafer carrier on lead frame, therefore corresponding each silicon wafer carrier can be laid a plurality of micropores uniformly, and a plurality of micropores can be even, stable holds this silicon wafer carrier.For QFN, the DFN integrated circuit, its lead frame has the multiple lines and multiple rows silicon wafer carrier, just can offer the micropore of One's name is legion on heat block, corresponding to holding all silicon wafer carriers.Pressing plate above lead frame presses down that (manufacturing to the window frame body on pressing plate is less demanding, for example can make a large window frame body, on lead frame, the edge away from silicon wafer carrier gets final product in order to push down), the location live lead frame and on silicon wafer carrier after, can carry out the routing bonding, can not float, routing is bad, rosin joint etc.In addition, due to the micropore that can offer One's name is legion, therefore, can hold the multiple row silicon wafer carrier in an impulse stroke and carry out the routing bonding, greatly enhance productivity.
Because technique scheme is used, the utility model compared with prior art has following advantages:
1, the utility model due to the micropore that can offer One's name is legion, therefore, can hold the multiple row silicon wafer carrier and carry out the routing bonding in an impulse stroke, greatly enhances productivity.
2, the utility model is because micropore size is very little, be far smaller than the size of the silicon wafer carrier on lead frame, therefore corresponding each silicon wafer carrier can be laid a plurality of micropores uniformly, a plurality of micropores can be even, stable hold this silicon wafer carrier, make that the routing bonding process is avoided occurring floating, the problems such as routing is bad, rosin joint.
3, the hole depth of the utility model micropore is 5 times of its aperture, the convenient manufacturing.
Description of drawings
Fig. 1 is the use view of the line type bonding clamper in background technology;
Fig. 2 is that the master of the heat block of the utility model embodiment looks schematic diagram;
Fig. 3 is the A-A cutaway view of Fig. 2;
Fig. 4 is the use view of the bonding clamper of the utility model embodiment.
In above accompanying drawing: 1, heat block; 2, pressing plate; 3, lead frame; 4, body; 5, inhale vacuum hole; 6, micropore; 7, silicon wafer carrier; 8, inhale vacuum passage; 9, pin.
Embodiment
Below in conjunction with drawings and Examples, the utility model is further described:
Embodiment: shown in accompanying drawing 2-4, a kind of QFN, DFN integrated antenna package pore type bonding clamper, comprise heat block 1 and pressing plate 2, during use, heat block 1, lead frame 3 and pressing plate 2 are stacked successively from lower to upper, and described heat block 1 has a body 4, offer to inhale vacuum hole 5 and some micropores 6 on this body 4, the aperture of micropore 6 is 0.15～0.17 millimeter, and described some micropores 6 all are communicated with suction vacuum hole 5; The position of described some micropores 6 silicon wafer carrier 7 on the installation position on body 4 and lead frame 3 is corresponding.
For ease of processing, the hole depth of micropore 6 is 5 times of its aperture.
Offer one on the body 4 of heat block 1 and inhale vacuum passage 8, described some micropores 6 are inhaled vacuum passage 8 through this and are communicated with suction vacuum hole 5.
Above-described embodiment only is explanation technical conceive of the present utility model and characteristics, and its purpose is to allow person skilled in the art scholar can understand content of the present utility model and implement according to this, can not limit protection range of the present utility model with this.All equivalences of doing according to the utility model Spirit Essence change or modify, within all should being encompassed in protection range of the present utility model.
Claims (3)
1. QFN, DFN integrated antenna package pore type bonding clamper, comprise heat block (1) and pressing plate (2), heat block during use (1), lead frame (3) and pressing plate (2) are stacked successively from lower to upper, it is characterized in that: described heat block (1) has a body (4), offer on this body (4) and inhale vacuum hole (5) and some micropores (6), the aperture of micropore (6) is 0.15～0.17 millimeter, and described some micropores (6) all are communicated with suction vacuum hole (5); The installation position of described some micropores (6) on body (4) is corresponding with the position of the upper silicon wafer carrier (7) of lead frame (3).
2. bonding clamper according to claim 1 is characterized in that: the hole depth of described micropore (6) is 5 times of its aperture.
3. bonding clamper according to claim 1 is characterized in that: offer one on the body (4) of described heat block (1) and inhale vacuum passage (8), described some micropores (6) are inhaled vacuum passage (8) through this and are communicated with suction vacuum hole (5).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220678510 CN202977378U (en) | 2012-12-11 | 2012-12-11 | Micropore type pressure welding clamp for QFN-DFN integrated circuit package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220678510 CN202977378U (en) | 2012-12-11 | 2012-12-11 | Micropore type pressure welding clamp for QFN-DFN integrated circuit package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202977378U true CN202977378U (en) | 2013-06-05 |
Family
ID=48518421
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220678510 Expired - Fee Related CN202977378U (en) | 2012-12-11 | 2012-12-11 | Micropore type pressure welding clamp for QFN-DFN integrated circuit package |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202977378U (en) |
-
2012
- 2012-12-11 CN CN 201220678510 patent/CN202977378U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130605 Termination date: 20141211 |
|
| EXPY | Termination of patent right or utility model |