CN202796964U

CN202796964U - Depletion type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor)

Info

Publication number: CN202796964U
Application number: CN 201220379154
Authority: CN
Inventors: 赵金波; 王维建; 曹俊
Original assignee: Hangzhou Silan Integrated Circuit Co Ltd
Current assignee: Hangzhou Silan Integrated Circuit Co Ltd
Priority date: 2012-07-31
Filing date: 2012-07-31
Publication date: 2013-03-13
Anticipated expiration: 2022-07-31

Abstract

The utility model provides an MOSFET, which comprises a first doping type doping liner, a first doping type epitaxial layer formed on one surface of the liner, second doping type deep traps formed inside the epitaxial layer, and first doping type ion filling channels formed at the middle part of each deep trap. The channels of the depletion type MOSFET provided by the utility model are formed by adopting iron injection of mask layers, and higher performance can be ensured due to precise structure, position and depth of the channels.

Description

Depletion type MOS FET

Technical field

The utility model belongs to technical field of manufacturing semiconductors, particularly a kind of depletion type MOS FET.

Background technology

MOSFET is divided into enhancement mode MOSFET and depletion type MOS FET.For depletion type MOS FET, because in the oxide layer of source-drain electrode, mixed a large amount of ions, even when grid voltage VGS=0, under the effect of the doping ion of oxide layer, can induce opposite majority carrier with the substrate doping type in the underlayer surface and form inversion layer, be to have raceway groove between source-leakage, as long as between source-leakage, add forward voltage, just can produce drain current; When adding grid voltage VGS, can make majority carrier flow out raceway groove, inversion layer narrows down the channel resistance change greatly, and when grid voltage VGS increased to certain value, inversion layer disappeared, and raceway groove is by pinch off (exhausting), and depletion type MOS FET can turn-off.

Take N ditch depletion type MOS FET as example, when grid voltage VGS=0, the raceway groove between the drain-source exists, so as long as add voltage VDS, source-drain electrode between source-drain electrode electric current I D circulation is just arranged.If increase grid voltage VGS, the electric field between grid and the substrate will make the more electronics of induction in the raceway groove, the raceway groove thickening, and the electricity of raceway groove is led increase.If add negative voltage at grid, namely grid voltage VGS＜0 will induce positive charge at the device surface of correspondence, and these positive charges are offset the electronics in the N raceway groove, thereby produces a depletion layer at substrate surface, and raceway groove is narrowed down, and channel conduction reduces.When minus gate voltage increased to a certain voltage Vp, depletion region expanded to whole raceway groove, and raceway groove even at this moment VDS still exists, can not produce drain current, i.e. ID=0 fully by pinch off (exhausting) yet.VP is called pinch-off voltage or threshold voltage.Conventional art mixes a large amount of cations in advance in grid oxic horizon when making depletion type MOS FET, when VGS=0, the electric field energy " induction " in P type substrate that these cations produce goes out enough electronics, forms the N-type raceway groove.

Namely in conventional art, the raceway groove of depletion type MOS FET is to form by the induction of the doping ion in the grid oxic horizon, so the structure of raceway groove, position and the degree of depth all be the ion doping situation that depends in the grid oxic horizon, and is not easy to determine.As everyone knows, the breadth length ratio of depletion type MOS FET raceway groove can affect the mutual conductance of raceway groove, thereby can affect many important parameters such as saturation current, leakage current and pinch-off voltage of depletion type MOS FET.And the manufacture method of traditional depletion type MOS FET is because its severity control to the position of raceway groove and raceway groove is not accurate enough, also can cause adverse effect to other zones (for example source region and drain region) to the Implantation of oxide layer simultaneously, thereby can't produce high-quality depletion type MOS FET.

Therefore structure, position and the degree of depth how accurately to control raceway groove have become a urgent problem in the manufacture process of depletion type MOS FET.

The utility model content

The utility model provides a kind of depletion type MOS FET, with the purpose of the structure, position and the channel depth that are able to accurately control raceway groove.

For solving the problems of the technologies described above, the utility model provides a kind of depletion type MOS FET, comprising:

The doped substrate of one first doping type;

Be formed at the epitaxial loayer of the first doping type on the described substrate one side;

Be formed at the deep trap of the second doping type in the described epitaxial loayer; And

Be formed at the implanted channel of first doping type at described deep trap middle part.

Optionally, described depletion type MOS FET also comprises:

Be formed at the grid structure of described raceway groove top;

Be formed at source region and drain region in the deep trap of described grid structure both sides.

Optionally, comprise grid oxic horizon and grid at described grid structure.

Optionally, described grid oxic horizon is silica.

Optionally, described grid is a kind of in polysilicon, doped polycrystalline silicon or the aluminium.

In the depletion type MOS FET structure in the utility model, its raceway groove forms by using mask layer to carry out Implantation, and the grid oxic horizon induction that passing through in the nontraditional technology mixed generates raceway groove.By using mask layer to carry out the raceway groove that Implantation generates, can accurately control by mask layer position and the structure of raceway groove, the condition by adjusting Implantation is with parameters such as accurate control channel depth and doping contents.Structure, position and the degree of depth of accurate raceway groove can guarantee high performance depletion type MOS FET.

Description of drawings

Fig. 1-Fig. 7 is section of structure in each step of depletion type MOS FET manufacture method of the utility model embodiment one.

Embodiment

Core concept of the present utility model is to utilize mask layer to carry out the raceway groove that Implantation is realized depletion type MOS FET, by using mask layer can realize accurately controlling position and the structure of raceway groove, the condition by adjusting Implantation is with parameters such as accurate control channel depth and doping contents.Structure, position and the degree of depth of accurate raceway groove can guarantee high performance depletion type MOS FET.

In order to make the purpose of this utility model, technical scheme and advantage are clearer, further elaborate below in conjunction with accompanying drawing.

As shown in Figure 7, the depletion type MOS FET of the utility model one embodiment comprises: N-type substrate 101; Be formed at the N-type epitaxial loayer 102 on described substrate 101 one sides; Be formed at the P type doping deep trap 105 in the described N-type epitaxial loayer 102; Be formed in the N-type implanted channel 108 at deep trap 105 middle parts; Be formed at the grid oxic horizon 109 that also covers described raceway groove 108 on the raceway groove 108 fully; Be formed at the grid 110 on the described grid oxic horizon 109; And, be formed in the grid 110 both sides epitaxial loayers 102 and source region 112 and drain region 113 in the deep trap 108.Described grid oxic horizon 109 and the grid 110 common grid structures that form.

Below in conjunction with Fig. 1 to Fig. 7 each step of the manufacture method of the depletion type MOS FET of the utility model one embodiment is elaborated.

As shown in Figure 1, provide a N-type substrate 101, at described substrate 101 growth N-type epitaxial loayers 102.The thickness of described epitaxial loayer 102 can affect the voltage endurance capability of device, and the thickness of epitaxial loayer 102 is thicker, and the voltage endurance capability of device is higher.For example, when device withstand voltage required as 600V, the thickness range of described epitaxial loayer 102 was 40 μ m ~ 60 μ m.

Then, as shown in Figures 2 and 3, form patterned the first mask layer 103 at described epitaxial loayer 102, form the first Implantation window 104; Carry out the Implantation first time take described the first mask layer 103 as mask, at described epitaxial loayer 102 interior formation P moldeed depth traps 105.In the present embodiment, the ion of Implantation is the boron ion for the first time, and the scope of Implantation Energy is 40Kev ~ 200Kev, and implantation dosage is 1.0E13/cm ²~ 1.0E14/cm ²Then, remove the first mask layer 103.

Finish after the Implantation first time, carry out the annealing first time, the temperature range of the described annealing first time is 1100 ℃ ~ 1200 ℃, and the time range of the described annealing first time is 60min ~ 180min.

Then, as shown in Figure 4 and Figure 5, form patterned the second mask layer 106 at described epitaxial loayer 102 and deep trap 105, the central region that exposes deep trap 105 forms the second Implantation window 107, carry out the Implantation second time take described the second mask layer 106 as mask, forming the implanted channel 108 that N-type is mixed corresponding to the second Implantation window 107 described deep trap 105 two side areas.The length range of described raceway groove 108 is 1 μ m ~ 3 μ m.In the present embodiment, the ion of Implantation is arsenic ion for the second time, and the energy range of Implantation is 80Kev～200Kev for the second time, and implantation dosage is 1.0E12/cm ²~ 1.0E13/cm ²Then, remove the second mask layer 106.

Then, as shown in Figure 6, form oxide layer and polysilicon layer in described deep trap 105, raceway groove 108 and extension 102 depositions.Then, etching is removed partial oxidation layer and polysilicon layer, forms the grid oxic horizon 109 and the grid 110 that cover raceway groove 108 fully.Described grid oxic horizon 109 and the grid 110 common grid structures that form.

In the present embodiment, oxide layer is silica, and the thickness range of described oxide layer is The thickness range of described polysilicon layer is

Further, in order to improve the conductivity of polysilicon, can carry out ion doping to polysilicon, doping process can adopt the POCL3(phosphorus oxychloride) diffusion technology or ion implantation technology.When adopting the POCL3 diffusion technology, it draws together the square resistance scope in advance is 15 Ω/ ~ 30 Ω/.When adopting ion implantation technology, can inject phosphonium ion and inject, the Implantation Energy scope is 40Kev ~ 150Kev, and implantation dosage is 1.0E15/cm ²~ 1.0E16/cm ²Certainly, the material as grid also can use preferably metal material of conductivity, for example aluminium.

Then, as shown in Figure 7, take described grid structure as mask, carry out for the third time Implantation in the deep trap 105 to described grid structure both sides, deep trap 105 interior formation source region 112 and the drain regions 113 of grid structure both sides.In the present embodiment, the ion of Implantation is arsenic ion for the third time, and the energy range of Implantation is 100Kev～200Kev for the third time, and implantation dosage is 1.0E15/cm ²~ 1.0E16/cm ²After finishing the 3rd Implantation, carry out the annealing second time, the temperature range of the described annealing second time is 800 ℃ ~ 1000 ℃, and the time range of the described annealing second time is 30min ~ 80min.

So far, finished the manufacturing of depletion type MOS FET as shown in Figure 7.Should be understood that, all the doping ions in above-described embodiment or doping type are got on the contrary that can obtain another embodiment, this belongs to ordinary skill in the art means, is not giving unnecessary details at this.

In sum, in the depletion type MOS FET structure in the utility model, its raceway groove carries out Implantation by the second mask layer and forms, and the grid oxic horizon induction that passing through in the nontraditional technology mixed generates raceway groove.By using mask layer to carry out the raceway groove that Implantation generates, can accurately control by mask layer position and the structure of raceway groove, the condition by adjusting Implantation is with parameters such as accurate control channel depth and doping contents.Structure, position and the degree of depth of accurate raceway groove can guarantee high performance depletion type MOS FET.

Obviously, those skilled in the art can carry out various changes and modification to utility model and not break away from spirit and scope of the present utility model.Like this, if of the present utility model these revise and modification belongs within the scope of the utility model claim and equivalent technologies thereof, then the utility model also is intended to comprise these change and modification.

Claims

1. a depletion type MOS FET is characterized in that, comprising:

The doped substrate of one first doping type;

2. depletion type MOS FET as claimed in claim 1 is characterized in that, described depletion type MOS FET also comprises:

Be formed at the grid structure of described raceway groove top;

3. depletion type MOS FET as claimed in claim 2 is characterized in that, described grid structure comprises grid oxic horizon and grid.

4. depletion type MOS FET as claimed in claim 3 is characterized in that, described grid oxic horizon is silica.

5. depletion type MOS FET as claimed in claim 4 is characterized in that, described grid is a kind of in polysilicon, doped polycrystalline silicon or the aluminium.