CN202796919U - 无引脚mosfet封装结构 - Google Patents

无引脚mosfet封装结构 Download PDF

Info

Publication number
CN202796919U
CN202796919U CN2012204211991U CN201220421199U CN202796919U CN 202796919 U CN202796919 U CN 202796919U CN 2012204211991 U CN2012204211991 U CN 2012204211991U CN 201220421199 U CN201220421199 U CN 201220421199U CN 202796919 U CN202796919 U CN 202796919U
Authority
CN
China
Prior art keywords
pin
mosfet
area
mosfet chip
welding disk
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CN2012204211991U
Other languages
English (en)
Inventor
胡乃仁
杨小平
李国发
钟利强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suzhou Good Ark Electronics Co Ltd
Original Assignee
Suzhou Good Ark Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suzhou Good Ark Electronics Co Ltd filed Critical Suzhou Good Ark Electronics Co Ltd
Priority to CN2012204211991U priority Critical patent/CN202796919U/zh
Application granted granted Critical
Publication of CN202796919U publication Critical patent/CN202796919U/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3201—Structure
    • H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
    • H01L2224/32013—Structure relative to the bonding area, e.g. bond pad the layer connector being larger than the bonding area, e.g. bond pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/37124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848—Bonding techniques
    • H01L2224/84801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本实用新型公开一种无引脚MOSFET封装结构，其导电基盘由散热区和基盘引脚区组成，此漏极引脚一端与散热区端面电连接，所述散热区位于MOSFET芯片正下方且与MOSFET芯片下表面之间通过软焊料导电层电连接；所述第一导电焊盘和第二导电焊盘位于MOSFET芯片另一侧，第一导电焊盘和第二导电焊盘均包括焊接区和引脚区，焊接区与引脚区的连接处具有一折弯部，从而使得焊接区高于引脚区；一铝导体带跨接于所述MOSFET芯片的源极与第一导电焊盘的焊接区之间；一金属线跨接于所述MOSFET芯片的栅极与第二导电焊盘的焊接区之间。本实用新型有利于进一步缩小器件的体积，同时减少封装体中部件的数目；且有效避免了由于连接栅极的金属线较细在使用中容易断的技术缺陷。

Description

无引脚MOSFET封装结构
技术领域
本发明涉及MOSFET芯片技术领域，具体涉及一种无引脚MOSFET封装结构。
背景技术
随着电子制造技术的快速发展，消费电子产品越来越向小型、便携的趋势发展，这也导致了这些电子产品的内部能够用于布置电学元件的空间变得越来越有限。在此情况下，采用的电学元件势必越薄越好，这也成为了目前电子元件制造也的发展趋势。四方扁平无引脚封装(QFN)工艺恰好可以满足这一需求。
附图1所示是现有技术中一种典型的QFN封装结构的剖面示意图，包括芯片900,散热片920、引线框架930、多个导线940，以及包裹上述结构的绝缘胶950。芯片900粘附在散热片920上，引线框架930具有多个相互绝缘的管脚，芯片900表面的焊盘通过导线940连接在引线框架93。相应的管脚上。绝缘胶950将上述结构全部包裹起来，以将其同外界隔离，仅将引线框架930的各个管脚和散热片920与芯片900相对的表面暴露在空气中。引线框架930暴露出来的管脚用于实现被封装的芯片900同外界的电学连接，而散热片920暴露出来的作用在于将芯片900工作时产生的热量通过暴露的表面散发到环境中去。
发明内容
本发明目的是提供一种无引脚MOSFET封装结构，此无引脚MOSFET封装结构有利于进一步缩小器件的体积，同时减少封装体中部件的数目；且有效避免了由于连接栅极的金属线较细在使用中容易断的技术缺陷，从而延长了产品的使用寿命并提高了可靠性。
为达到上述目的，本发明采用的技术方案是：一种无引脚MOSFET封装结构，包括MOSFET芯片、环氧树脂层，所述MOSFET芯片上表面设有源极和栅极，下表面设有漏极，还包括导电基盘、第一导电焊盘和第二导电焊盘，所述导电基盘由散热区和基盘引脚区组成，此基盘引脚区由若干个相间排列的漏极引脚组成，此漏极引脚一端与散热区端面电连接，所述散热区位于MOSFET芯片正下方且与MOSFET芯片下表面之间通过软焊料导电层电连接；所述第一导电焊盘和第二导电焊盘位于MOSFET芯片另一侧，第一导电焊盘和第二导电焊盘均包括焊接区和引脚区，焊接区与引脚区的连接处具有一折弯部，从而使得焊接区高于引脚区；一铝导体带跨接于所述MOSFET芯片的源极与第一导电焊盘的焊接区之间；一金属线跨接于所述MOSFET芯片的栅极与第二导电焊盘的焊接区之间。
上述技术方案中进一步改进的方案如下：
1、上述方案中，所述铝导体带宽厚比为1：10〜15。
2、上述方案中，所述漏极引脚的数目为四根。
由于上述技术方案运用，本发明与现有技术相比具有下列优点和效果：
1、本发明封装体中导电基盘，其同时兼备了现有技术中导电焊盘、散热片和基岛三个部件功能，既有利于进一步缩小器件的体积，也减少器件中部件的数目，同时由于散热区和基盘引脚区为一个整体，提高了电性能的稳定性。
2、本发明封装体中焊接区与引脚区的连接处具有一折弯部，从而使得焊接区高于引脚区，并保证了第一、第二导电焊盘的焊接区与MOSFET芯片的栅极在同一水平面，从而有效避免了由于连接栅极的第二金属线较细在使用中容易断的技术缺陷，从而延长了产品的使用寿命并提高了可靠性。
3、本发明所述MOSFET芯片的源极与第一导电焊盘的焊接区之间跨接有铝导体带，从而有利于减少欧姆接触电阻，提高了电性能指标，同时也减少热量的产生。
附图说明
图1为现有技术结构示意图；
图2为本发明功率MOSFET芯片的封装体结构示意图；
图3为附图2中沿A-A线的剖视图。
以上附图中： 1、MOSFET芯片；2、环氧树脂层；3、导电基盘；31、散热区；32、基盘引脚区；321、漏极引脚；4、第一导电焊盘；5、第二导电焊盘；6、软焊料导电层；7、焊接区；8、引脚区；9、金属线；10、铝导体带；11、金属线。
具体实施方式
下面结合实施例对本发明作进一步描述：
实施例：一种无引脚MOSFET封装结构，包括MOSFET芯片1、环氧树脂层2，所述MOSFET芯片上表面1设有源极和栅极，下表面设有漏极，还包括导电基盘3、第一导电焊盘4和第二导电焊盘5，所述导电基盘3由散热区31和基盘引脚区32组成，此基盘引脚区32由若干个相间排列的漏极引脚321组成，此漏极引脚321一端与散热区31端面电连接，所述散热区31位于MOSFET芯片1正下方且与MOSFET芯片1下表面之间通过软焊料导电层6电连接；所述第一导电焊盘4和第二导电焊盘5位于MOSFET芯片1另一侧，第一导电焊盘4和第二导电焊盘5均包括焊接区7和引脚区8，焊接区7与引脚区8的连接处具有一折弯部9，从而使得焊接区7高于引脚区8；一铝导体带10跨接于所述MOSFET芯片1的源极与第一导电焊盘4的焊接区7之间；一金属线11跨接于所述MOSFET芯片1的栅极与第二导电焊盘5的焊接区7之间。
上述铝导体带10宽厚比为1：10〜15。
上述漏极引脚321的数目为四根。
上述实施例只为说明本发明的技术构思及特点，其目的在于让熟悉此项技术的人士能够了解本发明的内容并据以实施，并不能以此限制本发明的保护范围。凡根据本发明精神实质所作的等效变化或修饰，都应涵盖在本发明的保护范围之内。

Claims (3)

1. 一种无引脚MOSFET封装结构，包括MOSFET芯片（1）、环氧树脂层（2），所述MOSFET芯片上表面（1）设有源极和栅极，下表面设有漏极，其特征在于：还包括导电基盘（3）、第一导电焊盘（4）和第二导电焊盘（5），所述导电基盘（3）由散热区（31）和基盘引脚区（32）组成，此基盘引脚区（32）由若干个相间排列的漏极引脚（321）组成，此漏极引脚（321）一端与散热区（31）端面电连接，所述散热区（31）位于MOSFET芯片（1）正下方且与MOSFET芯片（1）下表面之间通过软焊料导电层（6）电连接；所述第一导电焊盘（4）和第二导电焊盘（5）位于MOSFET芯片（1）另一侧，第一导电焊盘（4）和第二导电焊盘（5）均包括焊接区（7）和引脚区（8），焊接区（7）与引脚区（8）的连接处具有一折弯部（9），从而使得焊接区（7）高于引脚区（8）；一铝导体带（10）跨接于所述MOSFET芯片（1）的源极与第一导电焊盘（4）的焊接区（7）之间；一金属线（11）跨接于所述MOSFET芯片（1）的栅极与第二导电焊盘（5）的焊接区（7）之间。
2. 根据权利要求1所述的无引脚MOSFET封装结构，其特征在于：所述铝导体带（10）宽厚比为1：10〜15。
3. 根据权利要求1所述的无引脚MOSFET封装结构，其特征在于：所述漏极引脚（321）的数目为四根。
CN2012204211991U 2012-08-23 2012-08-23 无引脚mosfet封装结构 Expired - Lifetime CN202796919U (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2012204211991U CN202796919U (zh) 2012-08-23 2012-08-23 无引脚mosfet封装结构

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2012204211991U CN202796919U (zh) 2012-08-23 2012-08-23 无引脚mosfet封装结构

Publications (1)

Publication Number Publication Date
CN202796919U true CN202796919U (zh) 2013-03-13

Family

ID=47824122

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2012204211991U Expired - Lifetime CN202796919U (zh) 2012-08-23 2012-08-23 无引脚mosfet封装结构

Country Status (1)

Country Link
CN (1) CN202796919U (zh)

Similar Documents

Publication Publication Date Title
CN102983114B (zh) 具有超薄封装的高性能功率晶体管
CN102842549B (zh) 四方扁平无引脚的功率mosfet封装体
CN112701094A (zh) 一种功率器件封装结构及电力电子设备
CN102842548A (zh) 四方扁平型功率mos芯片封装结构
CN102842550B (zh) 功率mosfet芯片的dfn封装结构
CN209104141U (zh) 一种芯片外露型封装结构
TW201822322A (zh) 具有多晶粒層疊的覆晶封裝整流／保護型二極體元件
CN202796919U (zh) 无引脚mosfet封装结构
CN202796930U (zh) 用于mosfet芯片的封装体
CN214203676U (zh) 贴片式光伏旁路模块的封装框架
WO2020118818A1 (zh) 一种功率半导体贴片封装结构
CN203118939U (zh) 四方扁平型功率器件封装体
CN202796931U (zh) 功率mosfet的器件结构
CN202796918U (zh) 四方扁平无引脚的mos封装结构
CN203118935U (zh) 整流芯片的dfn封装结构
CN202796917U (zh) 无引脚的功率mosfet器件
CN203118936U (zh) 整流半导体芯片封装结构
CN103208474A (zh) 四方扁平型高功率芯片封装结构
CN212182316U (zh) 一种无载体的半导体叠层封装结构
CN218039187U (zh) 一种应用于平面型功率器件的封装结构
CN211238226U (zh) 功率半导体封装器件
CN203277352U (zh) 高导热型功率整流半导体器件
CN216435895U (zh) 一种bms使用的集成化mos模块
CN102723420B (zh) 一种支架与led灯
CN216054694U (zh) 一种采用陶瓷基板封装的芯片

Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
CX01 Expiry of patent term
CX01 Expiry of patent term

Granted publication date: 20130313