CN202720870U - Gate on array circuit, display panel, and display device - Google Patents
Gate on array circuit, display panel, and display device Download PDFInfo
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- CN202720870U CN202720870U CN2012204302295U CN201220430229U CN202720870U CN 202720870 U CN202720870 U CN 202720870U CN 2012204302295 U CN2012204302295 U CN 2012204302295U CN 201220430229 U CN201220430229 U CN 201220430229U CN 202720870 U CN202720870 U CN 202720870U
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Abstract
The utility model relates to the technical field of display, and discloses a gate on array (GOA) circuit, a display panel, and a display device. The GOA circuit can generate control signals used to accurately control OLED drive current, and realize respectively controlling working condition and a pixel circuit of an OLED device, thereby preventing OLED flicker probably occurs in a process of writing data into the pixel circuit caused by unstable pixel current. The GOA circuit comprises a gate drive module and a luminescence control module. The gate drive module is used to generate gate drive signals. The luminescence control module is connected with a gate drive signal output end of the gate drive module, and is used to generate luminescence control signals controlling on and off of the OLED under control of the gate drive signals. The gate drive signals and the luminescence control signals are inversed.
Description
Technical field
The utility model relates to the display technique field, particularly relates to a kind of array base palte horizontal drive circuit, display panel and display device.
Background technology
Traditional passive matrix Organic Light Emitting Diode (Passive Matrix OLED, be called for short PMOLED) when being applied in the display, along with the increase of the display size of display, need the driving time of shorter single pixel, thereby need to increase transient current, can increase power consumption like this.Simultaneously, the application of large electric current can cause on the ITO line pressure drop excessive, and makes the OLED operating voltage too high, and then reduces its efficient.And active matrix organic light-emitting diode (Active Matrix OLED, be called for short AMOLED) can address these problems well by the switching tube input OLED electric current of lining by line scan.Therefore, AMOLED is applied in the Performance Monitor more and more owing to having high brightness, wide visual angle and the advantage such as response speed faster.
Array base palte horizontal drive circuit (Gate on Array is called for short GOA) is that the gate switch circuit is integrated on the array base palte, thereby the height of realizing driving circuit is integrated, from saving material and reducing processing step two aspects and reduce cost.
AMOLED technology based on the low temperature polycrystalline silicon technology, its thin film transistor (TFT) that drives panel has higher mobility, so be more conducive to the integrated of GOA circuit, yet as a kind of technology that also is in the To be improved stage, the driving circuit that is applied to AMOLED on the market is also fewer.
The utility model content
The technical matters that (one) will solve
The technical problems to be solved in the utility model is: how to design a kind of array base palte horizontal drive circuit that can stably produce accurate control OLED drive current.
(2) technical scheme
In order to solve the problems of the technologies described above, the utility model provides a kind of array base palte horizontal drive circuit, the multi-level pmultistage circuit unit that comprises series connection, every stage circuit units comprises grid electrode drive module and light emitting control module, described grid electrode drive module is for generation of gate drive signal, described light emitting control module is connected with the gate drive signal output terminal of described grid electrode drive module, be used for producing the open/close led control signal of control Organic Light Emitting Diode under the control of described gate drive signal, described gate drive signal and described led control signal are anti-phase.
Preferably, described grid electrode drive module comprises the first film transistor ~ the 5th thin film transistor (TFT) and the first bootstrap capacitor, wherein,
The transistorized first end of the first film is connected with the 3rd end of the 5th thin film transistor (TFT) and the second end of the 4th thin film transistor (TFT) respectively, the second end connects outside level signal, the 3rd end respectively with the first bootstrap capacitor be connected the second end of thin film transistor (TFT) and be connected, and as the output terminal of described gate drive signal;
The first end of the 3rd thin film transistor (TFT) connects clock signal, and the second end connects respectively the first end of the 5th thin film transistor (TFT), the first bootstrap capacitor and the second thin film transistor (TFT), and the 3rd end connects the gate drive signal output terminal of upper level circuit unit;
The second end of the first end of the 4th thin film transistor (TFT), the 5th thin film transistor (TFT) connects clock signal, and the 3rd end of the second thin film transistor (TFT) connects the reverse signal of clock signal, and the 3rd end of the 4th thin film transistor (TFT) connects outside level signal;
The first end of the first film transistor ~ the 5th thin film transistor (TFT) is grid.
Preferably, described grid electrode drive module also comprises the 6th thin film transistor (TFT) and the 7th thin film transistor (TFT), wherein, the first end of the 7th thin film transistor (TFT) connects the inversion signal of clock signal, the second end is connected with the 3rd end of the 5th thin film transistor (TFT), and the 3rd end is connected with the second end and the transistorized first end of the first film of the 6th thin film transistor (TFT) respectively; The first end of the 6th thin film transistor (TFT) connects clock signal, and the 3rd end of the 6th thin film transistor (TFT) is connected with the second end of the 4th thin film transistor (TFT).
Preferably, described grid electrode drive module also comprises the second bootstrap capacitor, and the first end of described the second bootstrap capacitor is connected with the transistorized first end of the first film.
Preferably, described light emitting control module comprises the 8th thin film transistor (TFT) ~ the 11 thin film transistor (TFT) and the 3rd bootstrap capacitor, wherein,
The first end of the 9th thin film transistor (TFT), the 11 thin film transistor (TFT) is connected with transistorized the 3rd end of described the first film, and the second end of the 8th thin film transistor (TFT) is connected with the first end of the 3rd end of the 9th thin film transistor (TFT) and the tenth thin film transistor (TFT), the 3rd bootstrap capacitor respectively; The second end of the tenth thin film transistor (TFT) is connected with the 3rd end of the second end of the 3rd bootstrap capacitor and the 11 thin film transistor (TFT) respectively and as the output terminal of described led control signal, the 3rd end of the tenth thin film transistor (TFT) connects clock signal; The outside level signal of the second termination of the 3rd end of the 8th thin film transistor (TFT), the 9th thin film transistor (TFT) and the 11 thin film transistor (TFT); The first end of described the 8th thin film transistor (TFT) ~ the 11 thin film transistor (TFT) is grid.
Preferably, for the described circuit unit of the first order, the 3rd end of the 3rd thin film transistor (TFT) connects external input signal; For the n stage circuit units, the input signal of the 3rd end of the 3rd thin film transistor (TFT) is provided by the described gate drive signal of the first film transistor the 3rd end output in the upper level circuit unit, and the input signal that the 8th thin film transistor (TFT) first end connects in this stage circuit units is the described gate drive signal of the first film transistor the 3rd end output in the next stage circuit unit; For the afterbody circuit unit, the 8th thin film transistor (TFT) first end connects another external input signal; Wherein, n is the integer more than or equal to 2.
Preferably, the first film transistor ~ the 11 thin film transistor (TFT) is P type thin film transistor (TFT), and the 3rd end of the 4th thin film transistor (TFT), the 8th thin film transistor (TFT) connects low level, and the second end of the second bootstrap capacitor, the first film transistor, the 11 thin film transistor (TFT) and the 9th thin film transistor (TFT) connects high level.
Preferably, the first film transistor ~ the 11 thin film transistor (TFT) is the N-type thin film transistor (TFT), and the 3rd end of the 4th thin film transistor (TFT), the 8th thin film transistor (TFT) connects high level, and the second end of the second bootstrap capacitor, the first film transistor, the 11 thin film transistor (TFT) and the 9th thin film transistor (TFT) connects low level.
Preferably, the first end of the 4th thin film transistor (TFT) is connected the 3rd end that first end that clock signal replaces with the 4th thin film transistor (TFT) connects the 4th thin film transistor (TFT).
Preferably, the second end of the first film transistor ~ the 11 thin film transistor (TFT) is source electrode, and the 3rd end is drain electrode.
Preferably, the second end of the first film transistor ~ the 11 thin film transistor (TFT) is drain electrode, and the 3rd end is source electrode.
The utility model also provides a kind of display panel, described display panel with described circuit as the array base palte horizontal drive circuit.
The utility model also provides a kind of display device, and described display device comprises described display panel.
(3) beneficial effect
Technique scheme has following advantage: the designed array base palte horizontal drive circuit of the utility model can stably produce the control signal Emission that can accurately control the OLED drive current, thereby can avoid the luminous flicker of the unstable OLED that causes of the pixel current that in data writing pixel circuitry processes, may cause, in this circuit, by adopting the CLK signal transistor T 4 is controlled, guaranteed at t1, t2, this gate line of t3 outside the period non-selects the stage, output G[n] Level hold relatively steady, fluctuate less.Capacitor C 2 level that kept N2 to order has simultaneously guaranteed to select the stage non-, and transistor T 1 is closed, and guarantees G[n] low level stability.Introduce transistor T 6 and T7, the annexation of further clear and definite N2 point and high-low level.
Description of drawings
Fig. 1 is the P type AMOLED pixel unit circuit of accurately controlling function with the OLED drive current;
Fig. 2 is the structural drawing of the utility model embodiment;
Fig. 3 is the structured flowchart of the GOA circuit unit of the utility model embodiment;
Fig. 4 is the circuit diagram of the GOA circuit unit of the utility model embodiment two;
Fig. 5 is each signal timing diagram of the GOA circuit unit of the utility model embodiment two;
Fig. 6 ~ Fig. 8 is that the GOA circuit unit of the utility model embodiment two is at the schematic diagram of each working stage;
Fig. 9 is the circuit diagram of GOA circuit unit among the utility model embodiment three;
Figure 10 is the circuit diagram of GOA circuit unit among the utility model embodiment four;
Figure 11 is each signal timing diagram of GOA circuit unit among the utility model embodiment four.
Embodiment
For active matrix liquid crystal display (AMLCD), the GOA circuit is for generation of the capable gating control signal of image element circuit array.For the AMOLED display, OLED is current driving apparatus, and whether the current path of control inflow OLED device just can be controlled the OLED device luminous.Control accurately for the drive current to OLED, when carrying out pixel circuit design, can add the circuit unit that drive current is accurately controlled, as shown in Figure 1.If therefore adopt the image element circuit structure of the type, provide the grid control signal for image element circuit except adopting traditional GOA unit, also need to design the Emission_GOA unit, for generation of the Emission signal of accurately controlling the OLED drive current.This Emission_GOA unit and traditional GOA unit (below be called Gate_GOA) cooperating, be used for finishing the respectively control of OLED device duty and image element circuit, can avoid the unstable OLED flicker that causes of pixel current that in data writing pixel circuitry processes, may cause.
Schematically, Fig. 1 is with the P type AMOLED pixel unit circuit of accurately controlling OLED drive current function.Referring to Fig. 1, wherein the Gate signal is grid control signal, be used for the control data-signal and (for example write existing image element circuit commonly used, and Emission signal, the i.e. led control signal of OLED on off state the 2T1C circuit),, in order to control the opening and closing of T0, thereby play the on/off of control drive current, and then control the open/close effect of the OLED device that is attached thereto, wherein Emission signal and Gate signal are a pair of anti-phase control signals.In circuit shown in Figure 1, describe as P type thin film transistor (TFT) as example take T0, because driving writing of signal data, grid need the regular hour, be low level at the Gate signal, open in the process of image element circuit, the Emission signal is high level, T0 closes, and namely cuts off being connected of OLED device and image element circuit, thereby so that the ablation process of data the state of OLED is not exerted an influence.Only have when data write finish after, the Gate signal is reset to height, image element circuit is in a stable duty, this moment, the Emission signal dragged down, and opened T0, drive current flows into the OLED device, lights the OLED device.
Below in conjunction with drawings and Examples, embodiment of the present utility model is described in further detail.Following examples are used for explanation the utility model, but are not used for limiting scope of the present utility model.
Embodiment one
The utility model embodiment one provides a kind of array base palte horizontal drive circuit, its structural drawing as shown in Figure 2, the multi-level pmultistage circuit cell S TAGE_1 ~ STAGE_N+1 that comprises series connection, the structure of every stage circuit units as shown in Figure 3, comprise grid electrode drive module 21 and light emitting control module 22, described grid electrode drive module 21 is for generation of gate drive signal, described light emitting control module 22 is connected with the gate drive signal output terminal of described grid electrode drive module 21, be used for producing under the control of described gate drive signal the led control signal of control Organic Light Emitting Diode switch, described gate drive signal and described led control signal are anti-phase.
Embodiment two
The utility model embodiment two provides a kind of array base palte horizontal drive circuit, its structural drawing as shown in Figure 2, on the basis of embodiment one, grid electrode drive module 21 wherein comprises the first film transistor T 1 ~ the 7th thin film transistor (TFT) T5 and the first bootstrap capacitor C1, wherein
The first end of T1 is connected the second end with the 3rd end of T5 respectively and is connected with T4, the second end connects outside level signal, and the 3rd end is connected the second end with C1 respectively and is connected with T2, and as the output terminal of described gate drive signal;
The first end of T3 connects clock signal clk, and the second end connects respectively the first end of T5, C1 and T2, and the 3rd end connects the gate drive signal output terminal of upper level circuit unit;
The second end of the first end of T4, T5 connects clock signal clk, and the 3rd end of T2 connects the reverse signal CLKB of clock signal, and the 3rd end of T4 connects outside level signal;
The first end of described T1 ~ T5 is grid.
In the present embodiment, the circuit structure of light emitting control module can be for realizing producing the arbitrary structures of the open/close led control signal of control Organic Light Emitting Diode under the control of described gate drive signal.Grid electrode drive module provides grid control signal for image element circuit, wherein, the on off state of transistor T 4 impact output G[n] speed that resets, adopt the CLK signal that transistor T 4 is controlled, guaranteed to select the stage gate line non-, the Level hold of output is relatively steady, fluctuates less, realizes the stable control that the image element circuit grid drive.
Embodiment three
The utility model embodiment three provides a kind of array base palte horizontal drive circuit, its structural drawing as shown in Figure 2, on the basis of embodiment two, grid electrode drive module wherein also comprises thin film transistor (TFT) T6 and T7, wherein, the first end of T7 connects the reverse signal CLKB of clock signal, and the second end is connected with the 3rd end of T5, and the 3rd end is connected with the second end of T6 and the first end of T1 respectively; The first end of T6 connects clock signal clk, and the 3rd end of T6 is connected with the second end of T4.
Add transistor T 6 and T7 in this circuit, connect with T4, T5 respectively, so that duty is more stable, and the further clear and definite N2 level of ordering and the annexation of high-low level, for example at the period t3 that resets, transistor T 7 is closed under the control of clock signal clk B, has guaranteed that the level that N2 orders is identical with VGL by the loop that is comprised of T4 and T6, is low level.
Embodiment four
The present embodiment provides a kind of array base palte horizontal drive circuit, its structural drawing as shown in Figure 2, on the basis of embodiment three, described grid electrode drive module wherein also comprises the second bootstrap capacitor C2, the first end of C2 is connected with the first end of T1, and the second end connects outside level signal.
Add C2 in this circuit, the level that has kept N2 to order has guaranteed to select the stage non-, and transistor T 1 is closed, and guarantees G[n] low level stability.
Embodiment five
The utility model embodiment five provides a kind of array base palte horizontal drive circuit, its structural drawing as shown in Figure 2, the multi-level pmultistage circuit cell S TAGE_1 ~ STAGE_N+1 that comprises series connection, every stage circuit units is the GOA circuit unit that is comprised of P type TFT, the structure of every stage circuit units such as Fig. 3, shown in Figure 4, comprise grid electrode drive module 21 and light emitting control module 22, described grid electrode drive module is for generation of gate drive signal, described light emitting control module is connected with the gate drive signal output terminal of described grid electrode drive module, be used for producing the open/close led control signal of control Organic Light Emitting Diode under the control of described gate drive signal, described gate drive signal and described led control signal are anti-phase.Described grid electrode drive module comprises the first film transistor T 1 ~ the 7th thin film transistor (TFT) T7 and the first bootstrap capacitor C1 ~ second bootstrap capacitor C2, and described light emitting control module comprises the 8th thin film transistor (TFT) T8 ~ the 11 thin film transistor (TFT) T11 and the 3rd bootstrap capacitor C3.Wherein, the first end of T3 connects clock signal clk, and the second end connects respectively the first end of T5, C1 and T2; The second end of T5 connects CLK, the first end of T7 connects the inversion signal CLKB of CLK, and the first end of T4, T6 connects CLK, and the 3rd end of T5 is connected with the second end of T7, the 3rd end of T7 is connected with the second end of T6 and the first end of C2, T1 respectively, and the 3rd end of T6 is connected with the second end of T4; The 3rd end of T1 is connected with the second end of C1, the second end of T2 respectively, as the output terminal of described gate drive signal, and is connected with the first end of T9, T11, and the 3rd end of T2 connects CLKB; The second end of T8 is connected with the 3rd end of T9 and the first end of T10, C3 respectively; The second end of T10 is connected with the 3rd end of the second end of C3 and T11 respectively and as the described led control signal of output, the 3rd end of T10 connects CLK;
For the described circuit unit of the first order, the 3rd end of T3 connects external input signal; For the n stage circuit units, the input signal of the 3rd end of T3 is provided by the described gate drive signal of T1 the 3rd end output in the upper level circuit unit, and the input signal that the T8 first end connects is the described gate drive signal of T1 the 3rd end output in the next stage circuit unit; For the afterbody circuit unit, the T8 first end connects another external input signal, and wherein, n is the integer more than or equal to 2.In the present embodiment, thin film transistor (TFT) T1 ~ T11 is P type thin film transistor (TFT), and the 3rd end of T4, T8 connects low level VGL, the second end of C2, T1, T11 and the second end of T9 connection high level VGH.
The port of thin film transistor (TFT) T1 ~ T11 or the upper label of bootstrap capacitor C1 ~ C3 " 1 " in above-mentioned " first end " corresponding diagram 4, the port of " the second end " corresponding label " 2 " wherein, the port of the 3rd end correspondence label " 3 " wherein; And the first end of thin film transistor (TFT) T1 ~ T11 is grid, and the second end is source electrode, and the 3rd end is drain electrode; Perhaps the first end of thin film transistor (TFT) T1 ~ T11 is grid, and the second end is drain electrode, and the 3rd end is source electrode.
Fig. 5 is the signal timing diagram of the P type GOA circuit unit of Fig. 4.Fig. 6 to Fig. 8 be this GOA circuit unit at the schematic diagram of each working stage, wherein, the thin film transistor (TFT) that represents with solid line is the thin film transistor (TFT) of each stage conducting, the thin film transistor (TFT) that the thin film transistor (TFT) that dots cut out for each stage.The principle of work of describing the GOA circuit unit below with reference to Fig. 6 ~ Fig. 8 and Fig. 3, Fig. 4 is as follows:
This GOA circuit unit is by clock signal clk and the CLKB control of two anti-phase (or being called complementation), the output G[n-1 of upper level GOA element circuit] as input signal at the corresponding levels.The course of work of this GOA element circuit is divided into input sample, output signal, three phases resets.
As shown in Figure 6, in the t1 stage, be input sample stage, G[n-1] be low imput, CLK is low level, the T3 conducting, so the level that this moment, N1 was ordered correspondingly is pulled down to VGL+ ∣ Vthp ∣, is low level, Qi Zhong ∣ Vthp ∣ is the threshold voltage of T3.At this moment, T4 and T6 conducting, the N2 point is low level, thus the T1 conducting, output G[n] be high level.Because the low level of N1, T2 also opens, and this moment, the CLKB signal was high level, thereby has guaranteed output G[n] be high level, at this moment, T9 and T11 close, and C1 is recharged simultaneously, and the voltage difference at C1 two ends is VGH – VGL – ∣ Vthp ∣.Since the existence of C3, the low level when the N3 point can keep the previous operating cycle, so this moment, T10 kept conducting, the CLK signal is low level, the led control signal Emission[n of output] be low level.And in this process because G[n+1] be high level, T8 remains and closes.
As shown in Figure 7, in the t2 stage, be output stage, G[n] be low level, input signal G[n-1] be high level, transistor T 3 is closed, the level that N1 is ordered is kept by C1, is VGL+|Vthp ∣, is low level, therefore T2, T5 conducting, CLKB is low level simultaneously, therefore the T7 conducting, and CLK is high level, and T6 closes, and has guaranteed that the N2 point is high level, but T1 closes, can be to G[n] low level exert an influence.G[n] low level, make T11 and T9 conducting.Output Emission[n is drawn high in the T11 conducting] be high level.The level that N3 is ordered is drawn high in the T9 conducting, and transistor T 10 is closed, and can not affect the led control signal Emission[n of output].And in this process because G[n+1] be high level, T8 remains and closes.
As shown in Figure 8, in the t3 stage, be reseting stage, input G[n-1] be high level, CLK is low level, the T3 conducting, the level that corresponding N1 is ordered will be drawn high and be high level, then T2, T5 close, and CLK is low level simultaneously, T4 and T6 conducting, and CLKB is high level, T7 closes, and has guaranteed the low level that N2 is ordered, and T1 opens, G[n] again drawn high and be high level, thereby T11 and T9 close, reset terminal G[n+1] be low level at this moment, the T8 conducting, drag down the level that N3 is ordered, the T10 conducting, the low level output of CLK is to output terminal Emission[n], thereby the reset operation of realization circuit.
In the present embodiment, the on off state of the transistor T 4 in grid electrode drive module impact output G[n] speed that resets, adopt the CLK signal that transistor T 4 is controlled, guaranteed at t1, t2, this gate line of t3 outside the period non-selects the stage, output G[n] Level hold relatively steady, fluctuate less, realize the stable control that the image element circuit grid drive.Capacitor C 2 level that kept N2 to order has simultaneously guaranteed to select the stage non-, and transistor T 1 is closed, and guarantees G[n] low level stability.Add transistor T 6 and T7 in this circuit, the level that further clear and definite N2 is ordered and the annexation of high-low level, for example at the period t3 that resets, transistor T 7 is closed under the control of clock signal clk B, guaranteed that the level that N2 orders is identical with VGL by the loop that is comprised of T4 and T6, be low level.Light emitting control module and grid electrode drive module are used in conjunction with the control signal that the OLED drive current can be accurately controlled in generation.
Embodiment six
The utility model embodiment six provides a kind of array base palte horizontal drive circuit, its structural drawing as shown in Figure 2, the multi-level pmultistage circuit cell S TAGE_1 ~ STAGE_N+1 that comprises series connection, every stage circuit units is the GOA circuit unit that is comprised of P type TFT, every stage circuit units as shown in Figure 9, compare with the GOA circuit unit of Fig. 4, its improvements are transistor T 4 to be diode-connection connect, and an end that namely grid of T4 is connected VGL with it links together.This scheme can guarantee that grid drive under the prerequisite of accurate control function, dwindle the layout area of transistor T 4, and then reduce the area of whole GOA circuit.The principle of work of the present embodiment and embodiment five are similar.
Embodiment seven
The utility model embodiment seven provides a kind of array base palte horizontal drive circuit, its structural drawing as shown in Figure 2, the multi-level pmultistage circuit cell S TAGE_1 ~ STAGE_N+1 that comprises series connection, its every stage circuit units as shown in figure 10, be with GOA circuit unit difference shown in Figure 4, thin film transistor (TFT) T1 ~ T11 wherein is the N-type thin film transistor (TFT), and T4, the 3rd end of T8 connects high level VGH, C2, T1, the second end of T11 and the second end of T9 connect low level VGL, this is that negative voltage is opened because T1 ~ T11 is P type thin film transistor (TFT) among Fig. 4, and T1 ~ T11 is the N-type thin film transistor (TFT) among Figure 10, positive voltage is opened, so the both positive and negative polarity of power supply will exchange.Figure 11 is its control sequential, and the control sequential of Figure 11 is opposite with the control sequential of Fig. 5.This N-type GOA circuit unit can use in the backboard of N-type AMOLED pixel unit circuit.The principle of work of the present embodiment and embodiment five are similar.
Embodiment eight
The utility model embodiment eight provides a kind of array base palte horizontal drive circuit, its structural drawing as shown in Figure 2, the multi-level pmultistage circuit cell S TAGE_1 ~ STAGE_N+1 that comprises series connection, the GOA circuit unit of its circuit unit and Figure 10 is similar, GOA circuit unit with respect to Figure 10, its improvements are transistor T 4 to be diode-connection connect, and an end that namely grid of T4 is connected VGH with it links together.This scheme can guarantee that grid drive under the prerequisite of accurate control function, dwindle the layout area of transistor T 4, and then reduce the area of whole GOA circuit.The principle of work of the present embodiment and embodiment five are similar.
Embodiment nine
The utility model embodiment nine provides a kind of display panel, for example the OLED display panel.Described display panel with described embodiment one to embodiment eight arbitrary described circuit as the array base palte horizontal drive circuit.Because the circuit unit in the employed array base palte horizontal drive circuit of this display panel can stably produce the control signal that can accurately control the OLED drive current, realize the respectively control of OLED device duty and image element circuit, thereby can avoid the luminous flicker of the unstable OLED that causes of the pixel current that in data writing pixel circuitry processes, may cause, so the quality of the shown image of display panel is improved.
Embodiment ten
The utility model embodiment ten provides a kind of display device, for example the OLED display.Described display device comprises embodiment nine described display panels.Because the circuit unit in the employed array base palte horizontal drive circuit of this display device can stably produce the control signal that can accurately control the OLED drive current, realize the respectively control of OLED device duty and image element circuit, thereby can avoid the luminous flicker of the unstable OLED that causes of the pixel current that in data writing pixel circuitry processes, may cause, so the quality of the shown image of display device is improved.
The above only is preferred implementation of the present utility model; should be understood that; for those skilled in the art; under the prerequisite that does not break away from the utility model know-why; can also make some improvement and replacement, these improvement and replacement also should be considered as protection domain of the present utility model.
Claims (13)
1. array base palte horizontal drive circuit, it is characterized in that, the multi-level pmultistage circuit unit that comprises series connection, every stage circuit units comprises grid electrode drive module and light emitting control module, described grid electrode drive module is for generation of gate drive signal, described light emitting control module is connected with the gate drive signal output terminal of described grid electrode drive module, be used for producing the open/close led control signal of control Organic Light Emitting Diode under the control of described gate drive signal, described gate drive signal and described led control signal are anti-phase.
2. circuit as claimed in claim 1 is characterized in that, described grid electrode drive module comprises the first film transistor ~ the 5th thin film transistor (TFT) and the first bootstrap capacitor, wherein,
The transistorized first end of described the first film is connected with the 3rd end of the 5th thin film transistor (TFT) and the second end of the 4th thin film transistor (TFT) respectively, the second end connects outside level signal, the 3rd end respectively with the first bootstrap capacitor be connected the second end of thin film transistor (TFT) and be connected, and as the output terminal of described gate drive signal;
The first end of described the 3rd thin film transistor (TFT) connects clock signal, and the second end connects respectively the first end of the 5th thin film transistor (TFT), the first bootstrap capacitor and the second thin film transistor (TFT), and the 3rd end connects the gate drive signal output terminal of upper level circuit unit;
The second end of the first end of described the 4th thin film transistor (TFT), the 5th thin film transistor (TFT) connects clock signal, and the 3rd end of described the second thin film transistor (TFT) connects the reverse signal of clock signal, and the 3rd end of described the 4th thin film transistor (TFT) connects outside level signal;
The first end of described the first film transistor ~ the 5th thin film transistor (TFT) is grid.
3. circuit as claimed in claim 2, it is characterized in that, described grid electrode drive module also comprises the 6th thin film transistor (TFT) and the 7th thin film transistor (TFT), wherein, the first end of the 7th thin film transistor (TFT) connects the inversion signal of clock signal, the second end is connected with the 3rd end of the 5th thin film transistor (TFT), and the 3rd end is connected with the second end and the transistorized first end of the first film of the 6th thin film transistor (TFT) respectively; The first end of the 6th thin film transistor (TFT) connects clock signal, and the 3rd end of the 6th thin film transistor (TFT) is connected with the second end of the 4th thin film transistor (TFT).
4. circuit as claimed in claim 3 is characterized in that, described grid electrode drive module also comprises the second bootstrap capacitor, and the first end of described the second bootstrap capacitor is connected with the transistorized first end of the first film, and the second end connects outside level signal.
5. circuit as claimed in claim 4 is characterized in that, described light emitting control module comprises the 8th thin film transistor (TFT) ~ the 11 thin film transistor (TFT) and the 3rd bootstrap capacitor, wherein,
The first end of the 9th thin film transistor (TFT), the 11 thin film transistor (TFT) is connected with transistorized the 3rd end of described the first film, and the second end of the 8th thin film transistor (TFT) is connected with the first end of the 3rd end of the 9th thin film transistor (TFT) and the tenth thin film transistor (TFT), the 3rd bootstrap capacitor respectively; The second end of the tenth thin film transistor (TFT) is connected with the 3rd end of the second end of the 3rd bootstrap capacitor and the 11 thin film transistor (TFT) respectively and as the output terminal of described led control signal, the 3rd end of the tenth thin film transistor (TFT) connects clock signal; The outside level signal of the second termination of the 3rd end of the 8th thin film transistor (TFT), the 9th thin film transistor (TFT) and the 11 thin film transistor (TFT); The first end of described the 8th thin film transistor (TFT) ~ the 11 thin film transistor (TFT) is grid.
6. circuit as claimed in claim 5 is characterized in that, for the described circuit unit of the first order, the 3rd end of the 3rd thin film transistor (TFT) connects external input signal; For the n stage circuit units, the input signal of the 3rd end of the 3rd thin film transistor (TFT) is provided by the described gate drive signal of the first film transistor the 3rd end output in the upper level circuit unit, and the input signal that the 8th thin film transistor (TFT) first end connects in this stage circuit units is the described gate drive signal of the first film transistor the 3rd end output in the next stage circuit unit; For the afterbody circuit unit, the 8th thin film transistor (TFT) first end connects another external input signal; Wherein, n is the integer more than or equal to 2.
7. circuit as claimed in claim 6, it is characterized in that, the first film transistor ~ the 11 thin film transistor (TFT) is P type thin film transistor (TFT), and the 3rd end of the 4th thin film transistor (TFT), the 8th thin film transistor (TFT) connects low level, and the second end of the second bootstrap capacitor, the first film transistor, the 11 thin film transistor (TFT) and the 9th thin film transistor (TFT) connects high level.
8. circuit as claimed in claim 6, it is characterized in that, the first film transistor ~ the 11 thin film transistor (TFT) is the N-type thin film transistor (TFT), and the 3rd end of the 4th thin film transistor (TFT), the 8th thin film transistor (TFT) connects high level, and the second end of the second bootstrap capacitor, the first film transistor, the 11 thin film transistor (TFT) and the 9th thin film transistor (TFT) connects low level.
9. such as claim 7 or 8 described circuit, it is characterized in that, the first end of the 4th thin film transistor (TFT) is connected the 3rd end that first end that clock signal replaces with the 4th thin film transistor (TFT) connects the 4th thin film transistor (TFT).
10. circuit as claimed in claim 5 is characterized in that, the second end of the first film transistor ~ the 11 thin film transistor (TFT) is source electrode, and the 3rd end is drain electrode.
11. circuit as claimed in claim 5 is characterized in that, the second end of the first film transistor ~ the 11 thin film transistor (TFT) is drain electrode, and the 3rd end is source electrode.
12. a display panel is characterized in that, described display panel with each described circuit in the claim 1 ~ 11 as the array base palte horizontal drive circuit.
13. a display device is characterized in that, described display device comprises the described display panel of claim 12.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012204302295U CN202720870U (en) | 2012-08-27 | 2012-08-27 | Gate on array circuit, display panel, and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012204302295U CN202720870U (en) | 2012-08-27 | 2012-08-27 | Gate on array circuit, display panel, and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202720870U true CN202720870U (en) | 2013-02-06 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012204302295U Withdrawn - After Issue CN202720870U (en) | 2012-08-27 | 2012-08-27 | Gate on array circuit, display panel, and display device |
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| Country | Link |
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| CN (1) | CN202720870U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102820007A (en) * | 2012-08-27 | 2012-12-12 | 京东方科技集团股份有限公司 | Array substrate row driving circuit, display panel and display device |
| CN107093393A (en) * | 2017-07-03 | 2017-08-25 | 成都晶砂科技有限公司 | The drive circuit that gate driving circuit and light emitting control drive circuit are blended |
| WO2019127873A1 (en) * | 2017-12-29 | 2019-07-04 | 武汉华星光电半导体显示技术有限公司 | Goa circuit unit, goa circuit, and display panel |
| US10803779B2 (en) | 2017-12-29 | 2020-10-13 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Gate driver on array (GOA) circuit unit, GOA circuit, and display panel |
-
2012
- 2012-08-27 CN CN2012204302295U patent/CN202720870U/en not_active Withdrawn - After Issue
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102820007A (en) * | 2012-08-27 | 2012-12-12 | 京东方科技集团股份有限公司 | Array substrate row driving circuit, display panel and display device |
| CN102820007B (en) * | 2012-08-27 | 2014-10-15 | 京东方科技集团股份有限公司 | Array substrate row driving circuit, display panel and display device |
| CN107093393A (en) * | 2017-07-03 | 2017-08-25 | 成都晶砂科技有限公司 | The drive circuit that gate driving circuit and light emitting control drive circuit are blended |
| WO2019127873A1 (en) * | 2017-12-29 | 2019-07-04 | 武汉华星光电半导体显示技术有限公司 | Goa circuit unit, goa circuit, and display panel |
| US10803779B2 (en) | 2017-12-29 | 2020-10-13 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Gate driver on array (GOA) circuit unit, GOA circuit, and display panel |
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