CN202771772U - Shift register, grid driver and display device - Google Patents
Shift register, grid driver and display device Download PDFInfo
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- CN202771772U CN202771772U CN2012204510705U CN201220451070U CN202771772U CN 202771772 U CN202771772 U CN 202771772U CN 2012204510705 U CN2012204510705 U CN 2012204510705U CN 201220451070 U CN201220451070 U CN 201220451070U CN 202771772 U CN202771772 U CN 202771772U
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Abstract
The utility model relates to the display technology field and provides a shift register, a grid driver and a display device. The shift register comprises an input circuit, a reset control circuit, a reset circuit and an output circuit, wherein the input circuit transmits an input signal to a pull-up circuit according to a signal inputted by a signal input end and a signal inputted by a first clock signal end, the reset control circuit transmits a control signal to the reset circuit according to a first level signal, a second level signal, a signal inputted by the first clock signal end, a signal inputted by a second clock signal end and the input signal, the reset circuit carries out reset of an output end according to the control signal transmitted by the reset control circuit and the first level signal, and the output circuit transmits an output signal according to the signal transmitted by the input circuit and the second level signal. The shift register has properties of compact and simple structure and stable performance and realizes row driving in a quite small area.
Description
Technical field
The utility model relates to the display device technical field, and a kind of shift register, gate drivers and display device are provided.
Background technology
Organic Light Emitting Diode (Organic Light-Emitting Diode, OLED) is applied in the high-performance demonstration more and more as a kind of light source with advantages such as high brightness, wide visual angle, fast response times.Traditional passive matrix organic light emitting display (Passive Matrix OLED, PMOLED) needs the driving time of shorter single pixel along with the increase of display size, thereby needs to increase transient current, causes power consumption to increase.The simultaneously application of large electric current can cause on the ITO line pressure drop excessive, and makes the OLED operating voltage too high, reduces its work efficiency.And active matrix organic light-emitting shows that (Active Matrix OLED, AMOLED) by the switching tube input OLED electric current of lining by line scan, can address these problems well.
Compare with AMLCD, the gray scale that AMOLED shows is directly proportional with the drive current of driving OLED device, and in order to realize the demonstration of higher gray scale, AMOLED needs larger drive current, so AMOLED adopts the more much higher crystal silicon technology of mobility to realize more.In order to compensate the problem of the threshold voltage shift that multi-crystal TFT exists, the image element circuit of AMOLED often needs corresponding collocation structure, so the image element circuit structure of AMOLED is more complicated, also need to take accordingly larger layout (layout) area, be unfavorable for miniaturization and the ultrathin of display device.
The utility model content
The technical matters that (one) will solve
For above-mentioned shortcoming, the utility model takies the problem of larger layout area in order to solve AMOLED circuit in the prior art, a kind of shift register, gate drivers and display device are provided.
(2) technical scheme
For addressing the above problem, at first, the utility model provides a kind of shift register, and described shift register comprises: input circuit sends input signal according to the signal of signal input part input and the signal of the first clock signal terminal input to pull-up circuit; Reset control circuit, link to each other with described input circuit and reset circuit, transmit control signal to reset circuit according to the signal of the first level signal, second electrical level signal, the input of the first clock signal terminal, signal and the described input signal of second clock signal end input; Reset circuit links to each other with described reset control circuit and output terminal, according to described control signal and the first level signal described output terminal is resetted; Output circuit links to each other with described input circuit and output terminal, and the signal and the described second electrical level signal that send according to described input circuit send output signal to described output terminal.
Preferably, described output circuit comprises transistor seconds and the first electric capacity, and the source electrode of transistor seconds connects the second clock signal end, and drain electrode connects output terminal at the corresponding levels, and grid connects the first level node; A pole plate of the first electric capacity connects the first level node, and another pole plate connects the drain electrode of transistor seconds.
Preferably, described reset circuit comprises the first transistor and the second electric capacity, and a pole plate of the second electric capacity connects the second electrical level node, and another pole plate connects the first level signal.
Preferably, described input circuit comprises the 3rd transistor, and the 3rd transistorized source electrode connects input end, and drain electrode connects the first level node, and grid connects the first clock signal terminal.
Preferably, described reset control circuit comprises the 4th, the 5th, the 6th and the 7th transistor, and the 4th transistorized drain electrode connects the second electrical level signal, and grid connects the first clock signal terminal, and source electrode connects the 6th transistorized drain electrode; Perhaps, the 4th transistorized drain and gate connects the second electrical level signal simultaneously, and source electrode connects the 6th transistorized drain electrode; The 5th transistorized source electrode connects the first level signal, and grid connects the first level node, and drain electrode connects the 7th transistorized source electrode; The 6th transistorized source electrode connects the second electrical level node, and drain electrode connects the 4th transistorized source electrode, and grid connects the first clock signal terminal; The 7th transistorized source electrode connects the 5th transistorized drain electrode, and drain electrode connects the second electrical level node, and grid connects the second clock signal end.
Preferably, described the first to the 7th transistor all is the P transistor npn npn or all is the N-type transistor.
Preferably, when all being the P transistor npn npn, the first level signal is high level signal, and the second electrical level signal is low level signal; When all being the N-type transistor, the first level signal is low level signal, and the second electrical level signal is high level signal.
Preferably, described the first to the 7th transistor is TFT.
Preferably, the TFT that each pixel cell is corresponding on described the first to the 7th transistorized TFT and the array base palte adopts identical technique to form simultaneously.
On the other hand, the utility model also provides a kind of gate drivers simultaneously, described gate drivers comprises the aforesaid shift register of a plurality of cascades, the first clock signal terminal of every one-level shift register and second clock signal end connect respectively two anti-phase clock signals, and the connection of two clock signal terminals of adjacent level is opposite simultaneously; The input end of every one-level connects the output terminal of upper level, with the output of the upper level input as the corresponding levels; The input termination initial input signal of the first order, the output of every one-level is as the control signal of corresponding row grid.
At last, the utility model also provides a kind of display device, and described display device comprises: aforesaid gate drivers.
(3) beneficial effect
Adopt 7 transistors and 2 electric capacity namely to form shift register in the utility model, simply compact for the shift register structure that each row is driven, stable performance, realized the row of AMOLED is driven with minimum area, thereby integrated gate drive circuitry on array base palte effectively, and need to not connect extra drive IC at substrate edges, reduced the layout area of circuit as far as possible, the height of having realized driving circuit is integrated, simplified the complexity of peripheral drive circuit in the utility model, material and preparation technology have been saved simultaneously, obviously having reduced process time and production cost, is the optimal selection that realizes that high resolution A MOLED shows.
Description of drawings
Fig. 1 is the structured flowchart according to the shift register of a kind of embodiment of the utility model;
Fig. 2 is the circuit structure diagram of shift register among the utility model embodiment 1;
Fig. 3 is the level signal logic timing figure of the shift register of the utility model embodiment 1;
Fig. 4 is the circuit structure diagram of shift register among the utility model embodiment 2;
Fig. 5 is the level signal logic timing figure of the shift register of the utility model embodiment 2;
Fig. 6 is the circuit structure diagram of shift register among the utility model embodiment 3;
Fig. 7 is the gate driver circuit structural drawing of a plurality of shift register cascades in the utility model.
Embodiment
Below in conjunction with the accompanying drawing among the utility model embodiment, the technical scheme among the utility model embodiment is clearly and completely described, obviously, described embodiment is a part of embodiment of the present utility model, rather than whole embodiment.Based on the embodiment in the utility model, the every other embodiment that those of ordinary skills obtain under the prerequisite of not making creative work belongs to the scope that the utility model is protected.
As shown in Figure 1, the shift register according to a kind of embodiment of the utility model comprises: input circuit, reset control circuit, reset circuit and output circuit.Wherein, input circuit sends input signal according to the signal of signal input part input and the signal of the first clock signal terminal input to pull-up circuit; Reset control circuit links to each other with described input circuit and reset circuit, transmits control signal to reset circuit according to the signal of the first level signal, second electrical level signal, the input of the first clock signal terminal, signal and the described input signal of second clock signal end input; Reset circuit links to each other with described reset control circuit and output terminal, according to described control signal and the first level signal described output terminal is resetted; Output circuit links to each other with described input circuit and output terminal, and the signal and the described second electrical level signal that send according to described input circuit send output signal to described output terminal.
The driving method of above-mentioned shift register comprises step:
Signal in the input end input is in the low level cycle, the signal of the first clock signal terminal input is low level, the signal of second clock signal end input is high level, reset control circuit sends to reset circuit and drives signal, reset circuit resets to output terminal, output terminal output high level signal;
Within the next clock period, the signal of the signal of input end input and the input of the first clock signal terminal is high level, the signal of second clock signal end input is low level, output circuit sends output signal to output terminal, reset control circuit sends cut-off signals to reset circuit, output terminal output low level signal;
Within next clock period again, the signal of input end input is high level, the signal of the first clock signal terminal input is low level, the signal of second clock signal end input is high level, reset control circuit sends to reset circuit and drives signal, reset circuit resets to output terminal, output terminal output high level signal.
Further specify the technical solution of the utility model below by specific embodiment.
In order to reduce the layout area of circuit as far as possible, adopt GOA(Gate on Array in the utility model, capable drivings of array base palte claims again integrated grid driving) mode realizes that the height of driving circuit is integrated.Particularly,, stable performance simply compact for the shift register structure that each row is driven in the utility model, realized the row of AMOLED is driven with minimum area, thereby integrated gate drive circuitry on array base palte effectively, and need to not connect extra drive IC at substrate edges, having simplified the complexity of peripheral drive circuit, reduced the layout area of GOA circuit, is the optimal selection that realizes that high resolution A MOLED shows.
Further, as shown in Figure 2, among the embodiment 1 of the present utility model, shift register is subjected to the control of the clock signal (the signal CLKB of the signal CLK of the first clock signal terminal input and the input of second clock signal input part) of two complementations (namely each other inversion signal), receives the output G[n-1 of upper level circuit] as input signal (INPUT) at the corresponding levels.
At first describe as an example of P transistor npn npn (PMOS) example among Fig. 2, in this shift register: output circuit comprises transistor seconds and the first electric capacity, reset circuit comprises the first transistor and the second electric capacity, input circuit comprises the 3rd transistor, reset control circuit comprises the 4th, the 5th, the 6th and the 7th transistor, and wherein, the source electrode of the first transistor T1 connects the first level signal, drain electrode connects output terminal G[n at the corresponding levels], grid connects second electrical level node N2; The source electrode of transistor seconds T2 connects second clock signal end CLKB, and drain electrode connects output terminal G[n at the corresponding levels], grid connects the first level node N1; The source electrode of the 3rd transistor T 3 connects input end INPUT(by the output G[n-1 of upper level] input signal is provided), drain electrode connects the first level node N1, and grid connects the first clock signal terminal CLK; The drain electrode of the 4th transistor T 4 connects the second electrical level signal, and grid connects the first clock signal terminal CLK, and source electrode connects the drain electrode of the 6th transistor T 6; The 5th transistor T 5 source electrodes connect the first level signal, and grid connects the first level node N1, and drain electrode connects the source electrode of the 7th transistor T 7; The source electrode of the 6th transistor T 6 connects second electrical level node N2, and drain electrode connects the source electrode of the 4th transistor T 4, and grid connects the first clock signal terminal CLK; The source electrode of the 7th transistor T 7 connects the drain electrode of the 5th transistor T 5, and drain electrode connects second electrical level node N2, and grid connects second clock signal end CLKB; A pole plate of the first capacitor C 1 connects the first level node N1, and another pole plate connects the drain electrode of transistor seconds T2; A pole plate of the second capacitor C 2 connects second electrical level node N2, and another pole plate connects the first level signal.Among Fig. 1, when adopting the P transistor npn npn, the first level signal is high level signal VGH, and the second electrical level signal is low level signal VGL.
The below is further with reference to the level signal synoptic diagram of figure 3, and the course of work of the shift register that P transistor npn npn among the embodiment 1 of the present utility model is consisted of is described below:
This shift register is by clock signal clk and the CLKB control of two complementations, the output G[n-1 of upper level shift-register circuit] as input signal at the corresponding levels.The course of work of this shift-register circuit is divided into input sample, output signal, three phases resets.
The t1 stage, G[n-1] be low imput, control signal CLK is low level, transistor T 3 conductings are so the level that this moment, N1 was ordered is pulled down to VGL+|Vthp| accordingly.At this moment, transistor T 4 and T6 conducting, the N2 point is low level, thus transistor T 1 conducting, output G[n] be high level VGH.And this moment, the CLKB signal also was high level, thereby had guaranteed output G[n] be high level.This moment, C1 was recharged, to input signal G[n-1]=VGL samples, and the voltage difference at C1 two ends is VGH-VGL-∣ Vthp ∣.
T2 stage, input signal G[n-1] and the CLK signal be high, transistor T 3 is closed, the level that N1 order is kept by C1, for VGL+ ∣ Vthp ∣, is low level, so transistor T 2 conductings, CLKB is low level simultaneously, inputs G[n this moment] be low level.Simultaneously CLKB is low level, and N1 point also is low level, thus transistor T 5 and T7 conducting, and CLK to be high level guaranteed that transistor T 6 is closed has guaranteed that the N2 point is high level, transistor T 1 is closed, can be to not exporting G[n] exert an influence.
In the t3 stage, CLK is low level, transistor T 3 conductings, G[n-1] be high level, the level that corresponding N1 is ordered will be drawn high and be high level, and then transistor T 2 is closed, CLK is low simultaneously, transistor T 4 and T6 conducting, and CLKB is high, transistor T 7 is closed, guaranteed the low level that N2 is ordered, transistor T 1 is opened, input G[n] again drawn high and be high level VGH, realize resetting of output.
The on off state of transistor T 4 impact output G[n] speed that resets, adopt the CLK signal that transistor T 4 is controlled.Guaranteed that at t1 t2, this gate line of t3 outside the period non-selects the stage, input G[n] Level hold relatively steady, it is less to fluctuate.Capacitor C 2 has been guaranteed and should have been closed by period transistor T 1 at the level that the t2 period has kept N2 to order simultaneously, guarantees to input G[n] low level stability.
Shift register among the embodiment 2 comprises equally: the first to the 7th transistor and first, second electric capacity, and wherein, the source electrode of the first transistor T1 connects the first level signal, drain electrode connects output terminal G[n at the corresponding levels], grid connects second electrical level node N2; The source electrode of transistor seconds T2 connects second clock signal end CLKB, and drain electrode connects output terminal G[n at the corresponding levels], grid connects the first level node N1; The source electrode of the 3rd transistor T 3 connects input end INPUT(by the output G[n-1 of upper level] input signal is provided), drain electrode connects the first level node N1, and grid connects the first clock signal terminal CLK; The drain electrode of the 4th transistor T 4 connects the second electrical level signal, and grid connects the first clock signal terminal CLK, and source electrode connects the drain electrode of the 6th transistor T 6; The 5th transistor T 5 source electrodes connect the first level signal, and grid connects the first level node N1, and drain electrode connects the source electrode of the 7th transistor T 7; The source electrode of the 6th transistor T 6 connects second electrical level node N2, and drain electrode connects the source electrode of the 4th transistor T 4, and grid connects the first clock signal terminal CLK; The source electrode of the 7th transistor T 7 connects the drain electrode of the 5th transistor T 5, and drain electrode connects second electrical level node N2, and grid connects second clock signal end CLKB; A pole plate of the first capacitor C 1 connects the first level node N1, and another pole plate connects the drain electrode of transistor seconds T2; A pole plate of the second capacitor C 2 connects second electrical level node N2, and another pole plate connects the first level signal.Can find out from the contrast of Fig. 3 and Fig. 1, the connected mode of each transistor AND gate electric capacity is substantially the same manner as Example 1 among the embodiment 2, be with the difference of embodiment 1 among Fig. 1, among the embodiment 2, when adopting the N-type transistor, the first level signal is low level signal VGL, and the second electrical level signal is high level signal VGH.
The below is again with reference to the level signal synoptic diagram of figure 5, and the course of work of the shift register that N-type transistor among the embodiment 2 of the present utility model is consisted of is described below:
This shift register is controlled the output G[n-1 of upper level shift-register circuit by clock signal clk and the CLKB of two complementations equally among the embodiment 2] as input signal at the corresponding levels.The course of work of this shift-register circuit also is divided into input sample, output signal, three phases resets.
The t1 stage, G[n-1] be the high level input signal, control signal CLK is high level, transistor T 3 conductings are so the level that this moment, N1 was ordered is dragged down accordingly.At this moment, transistor T 4 and T6 conducting, the N2 point is high level, thus transistor T 1 conducting, output G[n] be low level VGL.And this moment, the CLKB signal also was low level, thereby had guaranteed output G[n] be low level.This moment, C1 was recharged, to input signal G[n-1] sample.
T2 stage, input signal G[n-1] and the CLK signal be low, transistor T 3 is closed, the level that N1 is ordered remains high level by C1, so transistor T 2 conductings, CLKB is high level simultaneously, inputs G[n this moment] be high level.Simultaneously CLKB is high level, and N1 point also be high level, thus transistor T 5 and T7 conducting, and CLK to be low level guaranteed that transistor T 6 is closed has guaranteed that the N2 point is low level, transistor T 1 is closed, can be to not exporting G[n] exert an influence.
In the t3 stage, CLK is high level, transistor T 3 conductings, G[n-1] be low level, the level that corresponding N1 is ordered will drag down and be low level, and then transistor T 2 is closed, CLK is high simultaneously, transistor T 4 and T6 conducting, and CLKB is low, transistor T 7 is closed, guaranteed the high level that N2 is ordered, transistor T 1 is opened, input G[n] again dragged down and be low level VGL, realize resetting of output.
The on off state of transistor T 4 impact output G[n] speed that resets, adopt the CLK signal that transistor T 4 is controlled.Guaranteed that at t1 t2, this gate line of t3 outside the period non-selects the stage, input G[n] Level hold relatively steady, it is less to fluctuate.Simultaneously capacitor C 2 has been guaranteed and should have been closed by period transistor T 1 at the level that the t2 period has kept N2 to order, and guarantees to input G[n] stability of high level.
Embodiment 3
Embodiment 3 of the present utility model as shown in Figure 6, by finding out that with the contrast of the embodiment 1 of Fig. 2 in this embodiment 3, the basic circuit structure of shift register is similar, just the connected mode of the drain and gate of the 4th transistor T 4 is slightly had any different.In embodiment 3, the drain and gate of the 4th crystal transistor T4 connects second electrical level signal (PMOS is low level signal VGL during pipe) simultaneously.In this way, the 4th transistor T 4 is operated in state of saturation, and it is in conducting state all the time, thereby can utilize less device size to realize the corresponding stronger ability that drags down when realizing.
In the course of work of embodiment 3, except transistor T 4 is in the conducting state all the time, all the other processes are substantially the same manner as Example 1, do not repeat them here.In addition, this embodiment is equally applicable in the circuit of embodiment 2, and just the second electrical level signal is high level signal VGH under the NMOS pattern.
More preferably, each transistor in the shift register among each embodiment of the utility model and each cell can adopt TFT(Thin Film Transistor, thin film transistor (TFT)) consists of, in the time of on being integrated in array base palte, can adopt identical technique to form simultaneously with the TFT that each pixel cell is corresponding on the array base palte.That is, the corresponding array base palte that adopts P type TFT of the shift register that P type TFT consists of, the shift register correspondence that N-type TFT consists of adopts the array base palte of N-type TFT, can further reduce like this preparation technology of whole devices.
Referring to Fig. 7, in the utility model, a plurality of above-mentioned shift register cascades consist of the gate drivers of liquid crystal panel again.Particularly, the cascade structure that is cascaded into gate drivers by N shift register is: every one-level shift register (STAGE_1, STAGE_2, ..., STAGE_N-1, STAGE_N) the first clock signal terminal CLKIN and second clock signal end CLKBIN connect respectively two anti-phase clock signals (the first clock signal clk and second clock signal CLKB), the simultaneously connection of two clock signal terminals of adjacent level opposite (if namely the CLKIN of odd level connects the first clock signal clk, then the CLKIN of even level meets second clock signal CLKB); The input end IN of every one-level connects the output terminal G[n of upper level], with the output of the upper level input as the corresponding levels; The input termination initial input signal INPUT of the first order, the output of every one-level is as the control signal G_1 of corresponding row grid, G_2 ..., G_N-1, G_N.By the gate drivers of this cascade, liquid crystal panel is opened successively the controlling grid scan line (abbreviation grid line) of every delegation and is closed the controlling grid scan line of other row under the driving of each signal, realizes lining by line scan thereby only drive TFT corresponding to this row pixel cell.
Preferably, above-mentioned gate drivers is integrated in and forms the GOA unit on the array base palte.The utility model also provides a kind of display device, and this display device comprises as above said gate drivers.Described display device can be any product or parts with Presentation Function such as liquid crystal panel, Electronic Paper, oled panel, LCD TV, liquid crystal display, digital album (digital photo frame), mobile phone, panel computer.
In the utility model, simply compact for the shift register structure that each row is driven, stable performance, realized the row of AMOLED is driven with minimum area, thereby integrated gate drive circuitry on array base palte effectively, and need to not connect extra drive IC at substrate edges, reduced the layout area of circuit as far as possible, the height of having realized driving circuit is integrated, simplified the complexity of peripheral drive circuit in the utility model, material and preparation technology have been saved simultaneously, obviously having reduced process time and production cost, is the optimal selection that realizes that high resolution A MOLED shows.
Above embodiment only is used for explanation the utility model; and be not limitation of the utility model; the those of ordinary skill in relevant technologies field; in the situation that does not break away from spirit and scope of the present utility model; can also make a variety of changes and modification; therefore all technical schemes that are equal to also belong to category of the present utility model, and scope of patent protection of the present utility model should be defined by the claims.
Claims (11)
1. a shift register is characterized in that, described shift register comprises:
Input circuit sends input signal according to the signal of signal input part input and the signal of the first clock signal terminal input to pull-up circuit;
Reset control circuit, link to each other with described input circuit and reset circuit, transmit control signal to reset circuit according to the signal of the first level signal, second electrical level signal, the input of the first clock signal terminal, signal and the described input signal of second clock signal end input;
Reset circuit links to each other with described reset control circuit and output terminal, according to described control signal and the first level signal described output terminal is resetted;
Output circuit links to each other with described input circuit and output terminal, and the signal and the described second electrical level signal that send according to described input circuit send output signal to described output terminal.
2. shift register as claimed in claim 1 is characterized in that, described output circuit comprises transistor seconds and the first electric capacity, and the source electrode of transistor seconds connects the second clock signal end, and drain electrode connects output terminal at the corresponding levels, and grid connects the first level node; A pole plate of the first electric capacity connects the first level node, and another pole plate connects the drain electrode of transistor seconds.
3. shift register as claimed in claim 2 is characterized in that, described reset circuit comprises the first transistor and the second electric capacity, and a pole plate of the second electric capacity connects the second electrical level node, and another pole plate connects the first level signal.
4. shift register as claimed in claim 3 is characterized in that, described input circuit comprises the 3rd transistor, and the 3rd transistorized source electrode connects input end, and drain electrode connects the first level node, and grid connects the first clock signal terminal.
5. shift register as claimed in claim 4, it is characterized in that described reset control circuit comprises the 4th, the 5th, the 6th and the 7th transistor, the 4th transistorized drain electrode connects the second electrical level signal, grid connects the first clock signal terminal, and source electrode connects the 6th transistorized drain electrode; Perhaps, the 4th transistorized drain and gate connects the second electrical level signal simultaneously, and source electrode connects the 6th transistorized drain electrode; The 5th transistorized source electrode connects the first level signal, and grid connects the first level node, and drain electrode connects the 7th transistorized source electrode; The 6th transistorized source electrode connects the second electrical level node, and drain electrode connects the 4th transistorized source electrode, and grid connects the first clock signal terminal; The 7th transistorized source electrode connects the 5th transistorized drain electrode, and drain electrode connects the second electrical level node, and grid connects the second clock signal end.
6. shift register according to claim 5 is characterized in that, described the first to the 7th transistor all is the P transistor npn npn or all is the N-type transistor.
7. shift register according to claim 6 is characterized in that, when all being the P transistor npn npn, the first level signal is high level signal, and the second electrical level signal is low level signal; When all being the N-type transistor, the first level signal is low level signal, and the second electrical level signal is high level signal.
8. shift register according to claim 5 is characterized in that, described the first to the 7th transistor is TFT.
9. shift register according to claim 8 is characterized in that, the TFT that each pixel cell is corresponding on described the first to the 7th transistorized TFT and the array base palte adopts identical technique to form simultaneously.
10. gate drivers, it is characterized in that, described gate drivers comprise a plurality of cascades such as each described shift register among the claim 1-9, the first clock signal terminal of every one-level shift register and second clock signal end connect respectively two anti-phase clock signals, and the connection of two clock signal terminals of adjacent level is opposite simultaneously; The input end of every one-level connects the output terminal of upper level, with the output of the upper level input as the corresponding levels; The input termination initial input signal of the first order, the output of every one-level is as the control signal of corresponding row grid.
11. a display device is characterized in that, described display device comprises: gate drivers as claimed in claim 10.
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| CN2012204510705U CN202771772U (en) | 2012-09-05 | 2012-09-05 | Shift register, grid driver and display device |
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| CN2012204510705U CN202771772U (en) | 2012-09-05 | 2012-09-05 | Shift register, grid driver and display device |
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Cited By (7)
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| CN102831861A (en) * | 2012-09-05 | 2012-12-19 | 京东方科技集团股份有限公司 | Shifting register, drive method thereof, gate driver and display device |
| WO2014173011A1 (en) * | 2013-04-27 | 2014-10-30 | 京东方科技集团股份有限公司 | Shift register unit, shift register, and display apparatus |
| CN104751769A (en) * | 2013-12-25 | 2015-07-01 | 昆山工研院新型平板显示技术中心有限公司 | Scanning driver and organic light emitting display employing same |
| CN105206235A (en) * | 2015-09-28 | 2015-12-30 | 京东方科技集团股份有限公司 | Reset device |
| CN108428425A (en) * | 2017-02-15 | 2018-08-21 | 上海和辉光电有限公司 | A kind of scan drive circuit, shift register and its driving method |
| CN110164347A (en) * | 2018-05-08 | 2019-08-23 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, scan drive circuit, display device |
| CN113168814A (en) * | 2018-11-23 | 2021-07-23 | 三星显示有限公司 | Scanning drive unit |
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- 2012-09-05 CN CN2012204510705U patent/CN202771772U/en not_active Expired - Lifetime
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|---|---|---|---|---|
| CN102831861A (en) * | 2012-09-05 | 2012-12-19 | 京东方科技集团股份有限公司 | Shifting register, drive method thereof, gate driver and display device |
| CN102831861B (en) * | 2012-09-05 | 2015-01-21 | 京东方科技集团股份有限公司 | Shifting register, drive method thereof, gate driver and display device |
| WO2014173011A1 (en) * | 2013-04-27 | 2014-10-30 | 京东方科技集团股份有限公司 | Shift register unit, shift register, and display apparatus |
| CN104751769A (en) * | 2013-12-25 | 2015-07-01 | 昆山工研院新型平板显示技术中心有限公司 | Scanning driver and organic light emitting display employing same |
| USRE48737E1 (en) | 2013-12-25 | 2021-09-14 | Kunshan New Flat Panel Display Technology Center Co., Ltd. | Scan driver and organic light-emitting display using same |
| CN105206235A (en) * | 2015-09-28 | 2015-12-30 | 京东方科技集团股份有限公司 | Reset device |
| CN108428425A (en) * | 2017-02-15 | 2018-08-21 | 上海和辉光电有限公司 | A kind of scan drive circuit, shift register and its driving method |
| CN110164347A (en) * | 2018-05-08 | 2019-08-23 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, scan drive circuit, display device |
| CN110164347B (en) * | 2018-05-08 | 2020-11-13 | 京东方科技集团股份有限公司 | Shift register unit and driving method thereof, scanning driving circuit and display device |
| CN113168814A (en) * | 2018-11-23 | 2021-07-23 | 三星显示有限公司 | Scanning drive unit |
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