CN202712193U - Thin-film transistor, array substrate and display apparatus - Google Patents
Thin-film transistor, array substrate and display apparatus Download PDFInfo
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- CN202712193U CN202712193U CN 201220364647 CN201220364647U CN202712193U CN 202712193 U CN202712193 U CN 202712193U CN 201220364647 CN201220364647 CN 201220364647 CN 201220364647 U CN201220364647 U CN 201220364647U CN 202712193 U CN202712193 U CN 202712193U
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Abstract
The utility model belongs to the technical field of display, and particularly relates to a thin-film transistor, an array substrate and a display apparatus. The thin-film transistor comprises a substrate, and a gate layer, a gate insulation layer, an active layer, an electrode metal layer and a passivation layer which are formed sequentially on the substrate. The electrode metal layer includes a source electrode and a drain electrode, wherein the source electrode and the drain electrode are insolated from each other with an in-between channel region. A first transparent conductive layer is disposed between the gate layer and the substrate, and a second transparent conductive layer is disposed between the active layer and the electrode metal layer. According to the thin-film transistor, since transparent conductive layers are added between the substrate and the gate metal layer, and between the active layer and the electrode metal layer, adhesion force between the gate metal layer and the substrate is enhanced, the electrode metal is prevented from diffusing to the active layer, and the product performance is improved.
Description
Technical field
The utility model belongs to the Display Technique field, particularly a kind of thin-film transistor, array base palte and display unit.
Background technology
Thin Film Transistor-LCD (Thin Film Transistor Liquid Crystal Display is called for short TFT-LCD) has the characteristics such as volume is little, low in energy consumption, radiationless, has occupied leading position in current flat panel display market.For TFT-LCD, thin-film transistor array base-plate and manufacturing process have determined its properties of product, rate of finished products and price.Common TN(Twisted Nematic, twisted-nematic) demand that the display effect of type liquid crystal display can not satisfying the market.At present, all big enterprises just gradually various wide viewing angle technology that display effect is better are applied in the mobility product, such as IPS(In-Plane Switching, coplanar conversion), VA(Vertical Alignment, vertical orientation), AD-SDS(Advanced-Super Dimensional Switching, senior super dimension field switch is referred to as ADS) etc. the wide viewing angle technology.Under the ADS pattern, the electric field that the electric field that produces by gap electrode edge in the same plane and gap electrode layer and plate electrode interlayer produce forms multi-dimensional electric field, make in the liquid crystal cell between gap electrode, all aligned liquid-crystal molecules can both produce rotation directly over the electrode, thereby improved the liquid crystal operating efficiency and increased light transmission efficiency.
Because reducing of electrode material resistance reduced resistance/capacitance time delay (RC delay), improved aperture opening ratio, and type of drive can become one-sided driving by two side drives, so the quantity of drive IC can reduce by half.Therefore, in the liquid crystal panel high speed development, industry need to be developed low-resistance electrode material.When using low electrical resistant material as electrode material, there is following problem: low electrical resistant material (copper for example, the resistance of copper only is 2 μ Ω cm, has demonstrated huge superiority as electrode material) little with substrate and semiconductor adhesive force, easily cause the loose contact of electrode material; Can react with Si at a lower temperature, diffuse to active layer, thereby affect device performance.
The utility model content
The technical problem that (one) will solve
The technical problems to be solved in the utility model is: provide a kind of solve low electrical resistant material to active layer by layer diffusion and with thin-film transistor, array base palte, the display unit of the technical problems such as substrate and semi-conducting material poor adhesive force.
(2) technical scheme
In order to solve the problems of the technologies described above, the utility model provides a kind of thin-film transistor, comprises the grid, gate insulation layer, active layer, electrode metal layer and the passivation layer that are formed on the substrate; Electrode metal layer comprises source electrode and drain electrode, and source electrode and drain electrode are isolated mutually, between be channel region; Be formed with the second transparency conducting layer between described active layer and the electrode metal layer.
Wherein, be formed with the first transparency conducting layer between described grid and the substrate.
Wherein, the material of described grid and electrode metal layer is copper; Be formed with respectively the layer of metal layer between described the first transparency conducting layer and the grid and/or between the second transparency conducting layer and the electrode metal layer, the material of described metal level is a kind of in molybdenum, aluminium, neodymium, titanium or its alloy.
Wherein, described active layer is amorphous silicon or oxide semiconductor material.
Wherein, described the first transparency conducting layer and/or the second transparency conducting layer are zinc oxide, indium tin oxide, indium-zinc oxide, poly-ethylenedioxy thiophene or grapheme material.
The utility model provides again a kind of array base palte, and it comprises above-mentioned each described thin-film transistor.
Wherein, be provided with pixel electrode and public electrode on the described array base palte, described pixel electrode and described public electrode are arranged on the different layers of described array base palte, are provided with insulating barrier between described pixel electrode and the described public electrode, described pixel electrode be shaped as slit-shaped.
Wherein, described public electrode adopts identical material with the first transparency conducting layer, and both are forming with in a photoetching process; Described pixel electrode adopts identical material with the second transparency conducting layer, and both are forming with in a photoetching process.
The utility model further provides a kind of display unit, and it comprises above-mentioned each described array base palte.
(3) beneficial effect
Technique scheme has following advantage: the thin-film transistor in the utility model is between substrate and the gate metal layer, increased transparency conducting layer between active layer and the electrode metal layer, strengthened the adhesive force between gate metal layer and the substrate, stop the diffusion of electrode metal layer to active layer, improved properties of product; The making of array base palte is simple in the utility model, so that array base palte and low based on the display unit cost of this array base palte, cost performance is high.
Description of drawings
Fig. 1 a to Fig. 1 f is respectively the process schematic diagram that forms transparency conducting layer, gate patterns, grid line figure, grid line PAD regional graphics among the utility model embodiment one at substrate;
Fig. 2 a to Fig. 2 e is respectively the process schematic diagram that the substrate after Fig. 1 f forms gate insulation layer, active layer and protective layer among the utility model embodiment one;
Fig. 3 a to Fig. 3 e is respectively the process schematic diagram that the substrate after Fig. 2 e forms the second transparency conducting layer, electrode metal layer, passivation layer and data PAD regional graphics among the utility model embodiment one;
Fig. 4 is array base palte sectional view among the utility model embodiment one;
Fig. 5 is array base palte sectional view among the utility model embodiment two;
Fig. 6 is array base palte sectional view among the utility model embodiment three;
Fig. 7 a to Fig. 7 d is respectively the manufacturing process schematic diagram of array base palte among the utility model embodiment three.
Wherein, 1: substrate; 2: the first transparency conducting layers; 2a: strengthen adsorption layer; 2b: public electrode; 3: grid; 4: gate insulation layer; 5: active layer; 6: protective layer; 7: the second transparency conducting layers; 7a: barrier diffusion; 7b: pixel electrode; 8: electrode metal layer; 8a: source electrode; 8b: drain electrode; 9: passivation layer; 10: intrinsic layer; 11:N type layer; 15: photoresist; 110: grid line PAD; 120: data wire PAD.
Embodiment
Below in conjunction with drawings and Examples, embodiment of the present utility model is described in further detail.Following examples are used for explanation the utility model, but are not used for limiting scope of the present utility model.
Embodiment one
The present embodiment be the utility model in the application of ADS mode LCD, wherein active layer is oxide semiconductor material.Fig. 4 is the present embodiment thin-film transistor sectional view, and grid 3, source electrode 8a and drain electrode 8b are copper material in the present embodiment, certainly, also can select the simple substance such as molybdenum, aluminium, neodymium, copper, titanium, perhaps every kind of material such as alloy that simple substance is corresponding as required.Between source electrode 8a and the active layer 5, between drain electrode 8b and the active layer 5 the second transparency conducting layer 7 is arranged.The second transparency conducting layer 7 is between electrode metal copper and the active layer 5, the electrode metal diffusion that can stop electrode metal copper and active layer 5 to react to cause.Grid line PAD110 and data wire PAD120 refer to the array substrate peripheral circuit part, are used for being connected with the external circuit board input gate drive signal and data-signal.
Preferably, the first transparency conducting layer 2 is arranged between grid 3 and substrate 1; The first transparency conducting layer 2 can increase the adhesive force between substrate 1 and grid 3 metallic coppers, improves the stability of product.
The first transparency conducting layer 2 shown in Fig. 4 is divided into again two parts on its function, be respectively grid 3 in the diagram and the enhancing adsorption layer 2a between the substrate 1, and the public electrode 2b between gate insulation layer 4 and the substrate 1.The first transparency conducting layer 2 can form simultaneously and strengthen adsorption layer 2a and public electrode 2b in forming process.Strengthen the adhesive force between adsorption layer 2a increase substrate 1 and grid 3 metallic coppers, improve the stability of product; Form simultaneously public electrode 2b, simplified the making step of independent formation public electrode.Can either improve the quality of thin-film transistor, simplify again its manufacture craft.
The second transparency conducting layer 7 shown in Fig. 4 is divided into again two parts on its function, be respectively between the source electrode 8a and active layer 5 in the diagram, the barrier diffusion 7a between drain electrode 8b and the active layer 5, and pixel region is positioned at the pixel electrode 7b on the gate insulator.The second transparency conducting layer 7 can form barrier diffusion 7a and pixel electrode 7b simultaneously in forming process, can either improve the quality of thin-film transistor, has simplified again its manufacture craft.
The first transparency conducting layer 2 and the second transparency conducting layer 7 can be respectively or are adopted simultaneously zinc oxide, and the transparent conductive materials such as indium tin oxide, indium-zinc oxide, indium zinc tin oxide, poly-ethylenedioxy thiophene or Graphene are such as ITO etc.
Making comprises the embodiment of the transistorized array base palte of said film, may further comprise the steps:
First step:
At first, as shown in Figure 1a, can select as required the substrate of unlike material at substrate 1(, such as glass substrate or quartz base plate) upper one deck the first transparency conducting layer 2 that forms, then form metallic copper grid 3 films at the first transparency conducting layer 2.Wherein, the method for grid 3 film forming is specifically as follows plasma reinforced chemical vapour deposition (PECVD), magnetron sputtering, thermal evaporation or other film build method, and the formation of the first transparency conducting layer 2 can be adopted depositional mode, spin coating mode or roller coating mode.
Secondly, spin coating one deck photoresist 15 on grid 3 films.Wherein, the formation of photoresist 15 can also be adopted spin coating mode or roller coating mode.
Next, form the photoetching agent pattern with difference in height at described grid layer, adopt different exposures to expose and develop subsequently according to its position of photoresist layer, the result forms the photoetching agent pattern method with difference in height and can adopt halftoning or gray tone mask plate to carry out exposure imaging.Shown in Fig. 1 b, photoresist 15 is divided into and removes regional I, fully reserve area II and part reserve area III fully behind the exposure imaging.(grid line PAD and data wire PAD refer to the array substrate peripheral circuit part to the complete reserve area II of photoresist corresponding to forming grid, grid line and grid line PAD110 regional graphics, be used for being connected with the external circuit board, input gate drive signal and data-signal), photoresist part reserve area III is corresponding to forming the common pattern of electrodes zone, and photoresist is removed regional I fully corresponding to the zone outside the complete reserve area II of photoresist and the photoresist part reserve area III.
Then, carry out the multistep etching, its process is: for the first time etching → ashing → second time etching.Shown in Fig. 1 c, etch away the first transparency conducting layer 2 and copper grid 3 films that photoresist is removed regional I fully for the first time; Then shown in Fig. 1 d, the photoresist 15 on the array base palte shown in Fig. 1 c is carried out ashing, the photoresist 15 of part reserve area III is removed; Then the array base palte shown in Fig. 1 d is carried out the etching second time, etch away copper grid 3 films of photoresist part reserve area III, obtain common pattern of electrodes, the sectional view of array base palte is shown in Fig. 1 e after finishing.Shown in Fig. 1 f, after etching is finished, photoresist 15 is peeled off.Wherein, removal photoresist 15 can adopt directly to be peeled off, or adopts PGMEA or EGMEA to carry out ionic liquid as solvent and peel off.
Understandable, when not being increased in this step the first transparency conducting layer 2 of grid 3 and substrate 1, can be in Fig. 1 b part keep regional III and change complete reserve area II into, make a public electrode with grid with layer.
Preferably, the first transparency conducting layer 2 is arranged between grid 3 and substrate 1; The first transparency conducting layer 2 can increase the adhesive force between substrate 1 and grid 3 metallic coppers, improves the stability of product.And, in forming process, can form simultaneously and strengthen adsorption layer 2a and public electrode 2b at the first transparency conducting layer 2, can either improve the quality of thin-film transistor, simplify again its manufacture craft.
Second step: carry out successively following technique on the array base palte of above-mentioned technique finishing:
At first, successive sedimentation gate insulation layer 4, active layer 5, protective layer 6;
Secondly, spin coating one deck photoresist 15 on array base palte;
Next, use halftoning or gray tone mask plate to carry out exposure imaging.Shown in Fig. 2 a, photoresist 15 is divided into and removes regional I, part reserve area II and complete reserve area III fully behind the exposure imaging.The corresponding protective layer zone that forms of the complete reserve area III of photoresist, for the protection of oxide semiconductor, in order to avoid in etching process oxide semiconductor is damaged, photoresist part reserve area II is used to form the contact zone with source electrode and drain electrode.Certainly, do not need protection the layer 6 o'clock, can remove after the exposure imaging operation by photoresist.
Then, carry out the multistep etching, its process is: for the first time etching → ashing → second time etching.Shown in Fig. 2 b, etching etches away active layer 5 and protective layer 6 that photoresist is removed regional I fully for the first time.Then shown in Fig. 2 c, the photoresist 15 on the array base palte shown in Fig. 2 b is carried out ashing, the photoresist 15 of part reserve area II is removed; Then the array base palte shown in Fig. 2 c is carried out the etching second time, etch away the protective layer 6 of photoresist part reserve area II, to expose oxide semiconductor, the sectional view of array base palte is shown in Fig. 2 d after finishing.Shown in Fig. 2 e, after etching is finished, photoresist 15 is peeled off.
Third step: carry out successively following technique on the array base palte of above-mentioned technique finishing:
At first, on array base palte, form continuously the second transparency conducting layer 7 and electrode metal layer 8;
Secondly, spin coating one deck photoresist 15 on array base palte;
Next, use halftoning or gray tone mask plate to carry out exposure imaging.Shown in Fig. 3 a, photoresist 15 is divided into and removes regional I, fully reserve area II and part reserve area III fully behind the exposure imaging.Corresponding protection source electrode 8a, drain electrode 8b, data wire and the data wire PAD120 graphics field of forming of the complete reserve area II of photoresist; photoresist part reserve area III is corresponding to forming the pixel electrode area figure, and photoresist is removed regional I fully corresponding to the zone beyond the complete reserve area II of photoresist and the part reserve area III.
Then, carry out the multistep etching, its process is: for the first time etching → ashing → second time etching.Shown in Fig. 3 b, etching etches away the second transparency conducting layer 7 and electrode metal layer 8 that photoresist is removed regional I fully for the first time.Then shown in Fig. 3 c, the photoresist 15 on the array base palte shown in Fig. 3 b is carried out ashing, the photoresist 15 of part reserve area III is removed; Then the array base palte shown in Fig. 3 c is carried out the etching second time, etch away the electrode metal layer 8 of photoresist part reserve area III, to expose the second transparency conducting layer 7, the sectional view of array base palte is shown in Fig. 3 d after finishing.Shown in Fig. 3 e, after etching is finished, photoresist 15 is peeled off.
At last, finish array base palte deposition one deck passivation layer 9 of above-mentioned steps.As shown in Figure 4, expose grid line PAD zone and data wire PAD zone by the exposure etching.
Namely finish the making of the utility model embodiment thin-film transistor array base-plate behind the stripping photoresist 15.
On the array base palte of the ADS of the present embodiment pattern, described pixel electrode and described public electrode are arranged on the different layers of described array base palte, be provided with insulating barrier between described pixel electrode and the described public electrode, described public electrode roughly covers whole pixel region, described pixel electrode be shaped as slit-shaped.
As can be seen from the above embodiments, the manufacturing process of the utility model thin-film transistor array base-plate has adopted composition technique four times, on the basis that does not increase prior art composition technique number of times, finish the making of the thin-film transistor array base-plate of new structure in the utility model.
Embodiment two
Another embodiment of the utility model is used for the TN mode LCD, and Fig. 5 is the present embodiment thin-film transistor sectional view.Be with ADS mode LCD difference among the embodiment one, the pixel electrode that is formed by the second transparency conducting layer 7 in the ADS mode LCD is slit-shaped and in the TN mode LCD, and the pixel electrode that the second transparency conducting layer 7 forms is tabular.In manufacturing process, for the first time do not need to adopt halftoning or gray tone mask plate to carry out the multistep etching technics of exposure imaging during composition technique.Be with the difference of embodiment one thin-film transistor array base-plate manufacture method, comprise the steps:
At first, after forming the first transparency conducting layer 2 and gate metal layer, use the mask plate of gate pattern to carry out exposure imaging, keep the photoresist 15 of grid, grid line and grid line PAD110 regional graphics;
Secondly, the pair array substrate carries out etching, and grid, grid line and grid line PAD110 regional graphics the first transparency conducting layer and the gate metal layer with exterior domain etched away fully.
Next carrying out forming gate insulation layer 4, active layer 6, protective layer 6, the second transparency conducting layer 7, source electrode 8a, drain electrode 8b and passivation layer 9 with a kind of identical step of embodiment gets final product; wherein; when forming pixel electrode by the second transparency conducting layer 7, guarantee that the block structure of pixel electrode gets final product.
Can find out, among above-mentioned two embodiment, increase transparency conducting layer between the active layer in the utility model thin-film transistor and the electrode metal layer, can stop electrode metal to spread to active layer, improve properties of product.When electrode metal used copper product, its diffusivity to active layer was stronger; For further stoping copper to the absorption affinity of active layer diffusion and increase copper, can increase by a metal level between grid and the first transparency conducting layer and/or between electrode metal layer and the second transparency conducting layer, the material of metal level can be selected simple substance or every kind of materials such as the corresponding alloy of simple substance such as molybdenum, aluminium, neodymium, titanium.
Embodiment three
Active layer among another embodiment of the present utility model is amorphous silicon material, and this embodiment is applicable to ADS mode LCD and TN mode LCD.Fig. 6 is the present embodiment thin-film transistor sectional view.Active layer comprises the intrinsic layer 10 of bottom and the N-type layer 11 on top, and intrinsic layer 10 is a-Si in the present embodiment, and N-type layer 11 is the N+a-Si that are mixed with the N-type dopant atom in a-Si.
The structure of thin-film transistor is similar among the structure of the present embodiment thin-film transistor and the embodiment one, and its difference is that active layer has double-decker in the present embodiment, and does not have the protective layer structure of thin-film transistor among the embodiment one.
When making comprised the array base palte of the present embodiment thin-film transistor, the step that forms gate patterns, grid line figure, grid line PAD regional graphics and the first pattern for transparent conductive layer at substrate was identical with embodiment one.After substrate forms gate metal layer and the first structure of transparent conductive layer, carry out following steps:
At first, on substrate, deposit successively gate insulation layer 4, a-Si material intrinsic layer 10, N+a-Si material N-type layer 11;
Secondly, spin coating photoresist 15 on the N-type layer;
Next, photoresist 15 is carried out exposure imaging, keep the photoresist 15 in active layer pattern zone, the array base palte sectional view is shown in Fig. 7 a after finishing.
Then, etch away intrinsic layer 10 and the N-type layer 11 that does not keep the photoresist zone.
Finish above-mentioned steps and remove photoresist 15 rear array base palte sectional views shown in Fig. 7 b.
Then the array base palte that obtains in the process above-mentioned steps carries out the step among the embodiment one, forms source electrode, drain electrode, data wire and data wire PAD regional graphics at array base palte, and this moment, the array base palte sectional view was shown in Fig. 7 c.
Be with embodiment one difference, the present embodiment thin film transistor active layer is double-decker, and does not have protective layer, so the present embodiment array base palte manufacturing process is further comprising the steps of: the N-type layer that etches away channel region.Etch away the sectional view of array base palte behind the N-type layer of channel region shown in Fig. 7 d.
After finishing above step and removing photoresist 15, at array base palte deposition one deck passivation layer 9, expose grid line PAD zone and data wire PAD zone by the exposure etching, thereby finish the making of the present embodiment thin-film transistor array base-plate.
Increase transparency conducting layer between active layer in the utility model thin-film transistor and the electrode metal layer, can stop electrode metal to spread to active layer, improved properties of product.When electrode metal used copper product, its diffusivity to active layer was stronger; For further stoping copper to the absorption affinity of active layer diffusion and increase copper, can increase by a metal level between grid and the first transparency conducting layer and/or between electrode metal layer and the second transparency conducting layer, the material of metal level can be selected simple substance or every kind of materials such as the corresponding alloy of simple substance such as molybdenum, aluminium, neodymium, titanium.Metal layer pattern and grid layer in the array base palte of said structure, electrode metal layer pattern are identical, and its manufacture method and above embodiment are basic identical, to grid layer, when electrode metal layer is graphical, finish simultaneously the graphical of metal level.
Certainly, the utility model thin-film transistor array base-plate can also be finished by other manufacture methods.Compared to existing technology, the utility model has structurally increased the first transparency conducting layer 2 and the second transparency conducting layer 7, and the two can form by independent composition technique.Although, do like this number of times that certainly will increase composition technique, significantly increased manufacturing cost, still can finish the making of the thin-film transistor array base-plate of the utility model structure.
Embodiment four
The present embodiment provides a kind of manufacture method of thin-film transistor, and it comprises:
Form grid at substrate;
Form gate insulation layer and active layer at described grid;
Form the second transparency conducting layer at described gate insulation layer and active layer, and be positioned at the second transparency conducting layer top electrode metal level;
Form passivation layer at described electrode metal layer and the second transparency conducting layer.
Form in the grid step at substrate, comprising: can on substrate, form first one deck the first transparency conducting layer, as the enhancing adsorption layer between grid and the substrate.Grid and enhancing adsorption layer can form in same step.Meanwhile, the first transparency conducting layer can form the public electrode that strengthens adsorption layer and array base palte simultaneously in forming process, can either improve the quality of thin-film transistor, has simplified again the manufacture craft of making array base palte.
Concrete, on substrate, form continuously the first transparency conducting layer and gate metal layer; Form photoetching agent pattern in described gate metal layer; Described photoetching agent pattern is carried out exposure imaging, respectively described gate metal layer is carried out etching after each exposure imaging, to form corresponding figure.Need to illustrate, when the first transparency conducting layer forms the public electrode of array base palte at the same time, need to form the photoetching agent pattern with difference in height in described gate metal layer, and carry out corresponding photoresist multistep exposure imaging.
In gate insulation layer on forming described grid and the step of active layer, comprising: being formed on continuous gate insulation layer, the active layer of forming on the described grid, form photoetching agent pattern at described active layer; Described photoetching agent pattern is carried out exposure imaging, carry out etching after each exposure imaging, to form corresponding figure.
Preferably, when active layer is oxide semiconductor, is being formed on successive sedimentation gate insulation layer, active layer, protective layer on the described grid, and is forming photoresist at protective layer;
Concrete, successive sedimentation gate insulation layer, oxide semiconductor layer and protective layer on the described grid; Spin coating photoresist on protective layer; Use halftoning or gray tone mask plate to carry out exposure imaging, the photoresist of protective layer graphics field is kept fully, two photoresists for the contact zone that connects with source electrode and drain electrode are partly kept; Form oxide semiconductor layer figure and protective layer figure through the multistep etching.
Preferably, when active layer was amorphous silicon material, active layer comprised intrinsic layer and N-type layer.
Concrete, successive sedimentation gate insulation layer, intrinsic layer and N-type layer; Spin coating photoresist on the N-type layer; Carry out exposure imaging, the photoresist of active layer graphics field is kept; Etch away the intrinsic layer and the N-type layer that do not keep the photoresist zone.
Form the second transparency conducting layer at described gate insulation layer and active layer, and the step that is arranged in the metal level on the second transparency conducting layer, described metal level comprises spaced source electrode and drain electrode, is channel region between the two; Comprise: on described gate insulation layer and active layer, form continuously the second transparency conducting layer and electrode metal layer; Form photoetching agent pattern at electrode metal layer; Photoetching agent pattern is carried out exposure imaging, carry out etching after each exposure imaging, to form corresponding figure.
Preferably, the second transparent conductor layer can also form the required pixel electrode of array base palte in this processing step, and this pixel electrode can be made into slit-shaped or tabular etc. as required.
Concrete, on described gate insulation layer and active layer, successive sedimentation the second transparency conducting layer and electrode metal layer; Spin coating photoresist on electrode metal layer; Use halftoning or gray tone mask plate to carry out exposure imaging, carry out etching after the exposure imaging and form source electrode, drain electrode.
Preferably, when described active layer is amorphous silicon material, also comprise the N-type layer that etches away channel region.
The above only is preferred implementation of the present utility model; should be understood that; for those skilled in the art; under the prerequisite that does not break away from the utility model know-why; can also make some improvement and replacement, these improvement and replacement also should be considered as protection range of the present utility model.
Claims (9)
1. thin-film transistor comprises the grid, gate insulation layer, active layer, electrode metal layer and the passivation layer that are formed on the substrate; Electrode metal layer comprises source electrode and drain electrode, and source electrode and drain electrode are isolated mutually, between be channel region; It is characterized in that, be formed with the second transparency conducting layer between described active layer and the electrode metal layer.
2. thin-film transistor as described in claim 1 is characterized in that, is formed with the first transparency conducting layer between described grid and the substrate.
3. thin-film transistor as described in claim 2 is characterized in that, the material of described grid and electrode metal layer is copper; Be formed with respectively the layer of metal layer between described the first transparency conducting layer and the grid and/or between the second transparency conducting layer and the electrode metal layer, the material of described metal level is a kind of in molybdenum, aluminium, neodymium, titanium or its alloy.
4. thin-film transistor as described in claim 1 is characterized in that, described active layer is amorphous silicon or oxide semiconductor material.
5. thin-film transistor as described in claim 2 is characterized in that, described the first transparency conducting layer and/or the second transparency conducting layer are zinc oxide, indium tin oxide, indium-zinc oxide, poly-ethylenedioxy thiophene or grapheme material.
6. an array base palte is characterized in that, comprises such as each described thin-film transistor among the claim 1-5.
7. array base palte as claimed in claim 6, it is characterized in that, be provided with pixel electrode and public electrode on the described array base palte, described pixel electrode and described public electrode are arranged on the different layers of described array base palte, be provided with insulating barrier between described pixel electrode and the described public electrode, described pixel electrode be shaped as slit-shaped.
8. array base palte as claimed in claim 7 is characterized in that, described public electrode adopts identical material with the first transparency conducting layer, and both are forming with in a photoetching process; Described pixel electrode adopts identical material with the second transparency conducting layer, and both are forming with in a photoetching process.
9. a display unit is characterized in that, comprises each described array base palte among the claims 6-8.
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| CN 201220364647 CN202712193U (en) | 2012-07-25 | 2012-07-25 | Thin-film transistor, array substrate and display apparatus |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102769040A (en) * | 2012-07-25 | 2012-11-07 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate and manufacturing method thereof, display device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102769040A (en) * | 2012-07-25 | 2012-11-07 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate and manufacturing method thereof, display device |
| WO2014015453A1 (en) * | 2012-07-25 | 2014-01-30 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate and manufacturing method thereof, and display device |
| CN102769040B (en) * | 2012-07-25 | 2015-03-04 | 京东方科技集团股份有限公司 | Thin-film transistor, array substrate, array substrate manufacturing method and display device |
| US9209308B2 (en) | 2012-07-25 | 2015-12-08 | Boe Technology Group Co., Ltd. | Thin film transistor, array substrate and method for manufacturing the same, display device |
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