CN202662294U - Programmable static random access memory (SRAM) sequential control circuit based on built-in self-test (BIST) control - Google Patents

Abstract

A programmable static random access memory (SRAM) sequential control circuit based on built-in self-test (BIST) control comprises a BIST module, a control unit and an SRAM module comprising a programmable sequential control module, and is characterized in that the programmable sequential control module is provided with a programmable reading and writing sequential control circuit, a word line wireless local loop (WLL) load copying unit and a reading and writing bit line load copying unit, the input of the programmable reading and writing sequential control circuit is a reading and writing control signal outputted from the control unit; the output of the programmable reading and writing sequential control circuit is respectively connected with the input of the word line load copying unit and the input of the reading and writing bit line load copying unit; the programmable reading and writing sequential control circuit also outputs a Rref signal to be connected with an enable pin of a sensitive amplifier sequential control circuit; and the output of a word line WLL drive copying unit in a secondary decoding and word line driving circuit is connected with a sequential end of the programmable reading and writing sequential control circuit.

Description

A kind of SRAM sequential control circuit able to programme based on BIST control

Technical field

The utility model relates to a kind of based on the embedded self-test of BIST() control SRAM(static RAM able to programme) sequential control circuit, belong to the integrated circuit (IC) design technical field.

Background technology

Development along with application demand, electronic product needs integrated more function, for example 3D video, game, GPS navigation, wireless Internet access business at a high speed etc., more and more higher demand has been brought the requirement to electronic product performance, thereby processing power and the processing speed of integrated circuit proposed higher requirement.The paper " Rapid estimation of the probability of SRAM failure due to MOS Threshold variations " that the people such as Shweta Srivastava in 2007 deliver points out that SoC and microprocessor system require more and more higher to SRAM, along with process descends, the performance of other digital circuit obtains fast lifting, but the speed that the performance of SRAM increases does not catch up with other digital circuit, therefore the performance of SRAM becomes the bottleneck of this type systematic gradually, its problem is, continuous decline along with process, SRAM storage unit and peripheral circuit size are also more and more less, thereby the technique mismatch is increasing on the Performance And Reliability impact of SRAM.The technique mismatch is larger on the impact of SRAM sequential control circuit, and traditional design is to obtain by leaving enough surpluses, but at deep submicron process, tradition leaves the method for design margin can bring larger performance loss, and process consistency is relatively poor.In addition, according to the statistics of this paper, the inside Cache of 70%-90% is comprised of SRAM, and because deal with data is more and more, it is increasing that data and Instruction Cache account for chip area.Therefore under advanced technologies, design high speed high reliability SRAM IP is most important for high-performance SoC and microprocessor system.

The SRAM reliability relates to a lot of aspects, comprises that read-write stability, the read-write sequence of storage unit postpones control etc.SRAM writes the sequential control that sequential time delay is mainly concerned with column selection CMUX switch and word line WLL control signal, and reads the sequential control that sequential time delay relates to WLL control signal, column selection CMUX switch, sense amplifier SA enable signal.Traditional inside sequential control is to obtain by the inverter delay chain, the paper " A high performance embedded SRAM compiler " of delivering such as the people such as Zhongyuan Wu in 2003, the method is very simple, but there is a fatal shortcoming, when existing technique or environmental baseline to change, chain of inverters can not well be followed the tracks of the delay of accessed unit.For this problem, the paper " A replica technique for wordline and sense control in low-power SRAMs " that the people such as B.S.Amrutur in 1998 deliver is used based on the storage unit that copies and is simulated critical path, thereby the delay of control sequential, this is the method for relatively commonly using, and also can follow the tracks of preferably the chip chamber mismatch that technique produces.But along with process descends, the transistor mismatch of chip internal is also more and more outstanding, and the method for traditional replicated critical path need to leave enough surpluses, and this can bring larger performance loss.

The paper " Robust SRAM design via BIST-assisted timing-tracking (BATT) " that the people such as Ya-Chun Lai in 2009 deliver has improved the method for traditional replicated critical path, output terminal at reproduction path adds a long inverter delay chain, select to select different delay output according to MUX, thereby realize programmable control sequential time delay.The control signal of MUX is produced by BIST and peripheral control logical block, whether the method can make mistakes according to the SRAM read-write is regulated the delay of sequential in real time, can follow the tracks of the technique mismatch properties in chip chamber and the chip, but chain of inverters and a plurality of transmission gate have been increased on the delay path, thereby the delay that self brings is longer, is not suitable for the performance application field.

Summary of the invention

The present invention mainly pays close attention to and reads, write sequential time delay to the SRAM reliability effect, the gordian technique that solves is to read for existing high-performance SRAM, write sequential time delay along with technique, temperature etc. change large problem, proposed a kind of based on the embedded self-test of BIST() control SRAM(static RAM able to programme) sequential control system, whether adopt embedded self-test BIST to detect the SRAM read-write works, regulate the control circuit of reading sequential time delay according to the SRAM read data correctness that BIST detects, thereby form the closed-loop system that detects and regulate, employing copies storage unit and reads the critical path of discharge paths the bit-line load that copies is discharged and recharged, thus can more accurate tracking temperature etc. environment sequential is affected.The main body of sequential time delay able to programme adopts the transistor same with storage unit, thereby can overcome technique, temperature etc. to sequential time delay variation impact greatly.

The technical solution adopted in the utility model is: a kind of SRAM sequential control circuit able to programme based on BIST control, comprise the BIST module, control module and the SRAM module that contains time-sequence control module able to programme, the SRAM module comprises: the SRAM storage array that is comprised of 6 transistors, by MUX, sense amplifier and input, the module of the data link that output buffer forms, the word line decoding path that is formed by one-level code translator and two-stage decode and word line driving circuit and by sequential control circuit, the sense amplifier sequential control circuit, the inside sequential control circuit that the MUX sequential control circuit forms; The output of one-level code translator connects the input of two-stage decode and word line driving circuit, the output of two-stage decode device connects the input of SRAM storage array, the output of SRAM storage array connects the input of MUX, the output of MUX connects the input of sense amplifier, the output of sense amplifier connects input, the input of output buffer, input, the SRAM that is output as of output buffer reads, write output and the input end of data, the output of sequential control circuit connects respectively the input of two-stage decode and word line driving circuit and MUX sequential control circuit, it is characterized in that: time-sequence control module able to programme is provided with able to programme reading, write sequential control circuit, word line WLL load copied cells and reading, write bit line load copied cells, able to programme reading, that writes sequential control circuit is input as reading of control module output, write control signal, able to programme reading, the output of writing sequential control circuit is connective word linear load copied cells and reading respectively, the input of write bit line load copied cells, able to programme reading, write sequential control circuit and also export the Enable Pin that the Rref signal connects the sense amplifier sequential control circuit, the output of word line WLL driven replication unit connects able to programme reading in two-stage decode and the word line driving circuit, write the sequential end of sequential control circuit, the connection of circuit is as follows:

Be provided with 3 PMOS pipes P1, P2, P3; 1 NMOS pipe N1; 2 phase inverter INV1, INV2 and n NMOS pipe NPG0, NPG1 ... NPGn and NPD0, NPD1 ... the discharge loop array able to programme that NPDn consists of, wherein, n represents the bit wide of control signal, the numerical value of n is greater than 1, less than the line number of SRAM storage array, NMOS pipe NPG0, NPG1 in the discharge loop array able to programme ... NPGn and NPD0, NPD1 ... NPDn is identical with transistor parameter in the SRAM storage array; NMOS manages NPG0, NPG1 ... the grid end of NPGn interconnects and is connected with the output of WLL driven replication unit, NMOS manages NPG0, NPG1 ... the source of NPGn is managed NPD0 with NMOS respectively, NPD1 ... the drain terminal of NPDn connects, NMOS manages NPD0, NPD1 ... the source of NPDn all is connected to low level VSS, NMOS manages NPD0, NPD1 ... the grid end of NPDn is reading for sequential control circuit able to programme, the write control signal input end, NMOS manages NPG0, NPG1 ... the interconnection of the drain terminal of NPGn and with read, the input end of write bit line load copied cells, the drain terminal of PMOS pipe P1, the drain terminal of the drain terminal of PMOS pipe P2 and NMOS pipe N1 links together, the grid end of PMOS pipe P1 and the output terminal of WLL driven replication unit, the input end of phase inverter INV1, the grid end of the grid end of PMOS pipe P3 and NMOS pipe N1 links together, the output terminal of phase inverter INV1 connects the grid end of PMOS pipe P2, the source of the source of PMOS pipe P2 and NMOS pipe N1, the drain terminal of PMOS pipe P3 and the input end of phase inverter INV2 link together, the source of the source of PMOS pipe P3 and PMOS pipe P1 all connects power vd D, and the output Rref of phase inverter INV2 is the output of whole sequential control circuit.

Advantage of the present utility model and beneficial effect: the present invention detects the SRAM working condition by BIST and regulates respectively SRAM reading and writing sequential time delay, thereby form the closed-loop system that detects and regulate, can carry out respectively the optimization adjusting to read latency and write delay, have more superior reliability.Postpone on the programmable basis not affecting reading and writing, the present invention has also designed the more excellent reading and writing of process tracing performance and has postponed the programmable circuit structure, the reading and writing critical path that employing copies storage unit discharges and recharges the load that copies, thereby can follow the tracks of more accurately the operational characteristic in chip chamber and the chip, more accurate control sequential time delay.Owing to do not increase extra delay cell in the sequential time delay path, therefore can realize the performance that SRAM is higher.

At present, along with the deep submicron process size is more and more less, the SRAM memory cell size is more and more less, not only is subjected to the impact of technique mismatch between the chip, SRAM also more and more is subject to the impact of chip internal transistor technology mismatch, the reduction that the technique mismatch in the chip can be brought reliability.It is low that high-performance SRAM circuit able to programme based on BIST control of the present invention has complexity, and therefore the characteristics of process tracing excellent are fit to the raising of SRAM reliability under the deep submicron process very much, and the increase that can not bring area.

Description of drawings

Fig. 1 is that the utility model adopts the BIST circuit to carry out the block diagram that the SRAM reliability is regulated;

Fig. 2 is a kind of programmable high reliability SRAM structured flowchart of the utility model;

Fig. 3 be a kind of conventional programmable read the sequential time delay circuit;

Fig. 4 is a kind of high performance sequential time delay circuit of reading of the present utility model;

Fig. 5 is the time domain waveform comparison diagram after the different programmable delay circuit temperature variation.

Embodiment

Fig. 1 is for adopting the BIST circuit to carry out the system chart that the SRAM read-write sequence is regulated.Circuit comprises three modules: embedded BIST module 13, control module 12, SRAM module 14(includes time-sequence control module 11 able to programme), wherein SRAM module bodies 14 and control module 12 can adopt existing circuit, referring to paper " Robust SRAM design via BIST-assisted timing-tracking (BATT) ", embedded BIST module 13 can generate by business software (such as Mentor Graphics MBIST ArchitectTM tool) in detail.BIST module 13 connects all input/output signals of SRAM module 14, control module 12 is input as BIST module 13 output signals, the output of control module 12 connects the control end input of time-sequence control module 11 able to programme, the sequential end input of time-sequence control module 11 able to programme connects translator unit output among the SRAM, and the output of time-sequence control module 11 able to programme connects SA Enable Pin among the SRAM.

BIST carries out the flow process that SRAM read-write postpones the adjusting of sequential: the control signal of initialization control module 12 at first, control signal is sent into time-sequence control module 11 able to programme, thereby the read-write of initialization SRAM postpones sequential, SRAM module 14 is read under the control of BIST circuit 13, write operation, whether the BIST circuit 13 relatively generation Done(by SRAM input and output data settling signal) and Fail(rub-out signal whether), control module 12 judges according to the Fail signal whether the SRAM read-write makes mistakes, as there is not a mistake, then control module 12 is regulated control signal, the delay of SRAM read-write sequence is reduced, thereby again carry out bug check circulation, until BIST judge wrong till.Thisly postpone sequential based on BIST circuit conditioning SRAM read-write able to programme and can realize fast Performance And Reliability trade-off optimization under the different technology conditions, and can not increase area and the complexity of circuit.

Fig. 2 is a kind of programmable high reliability SRAM structured flowchart.Wherein, the time-sequence control module able to programme 11 in the SRAM module 14 of Fig. 1 is comprised WLL load copied cells 22, reading and writing sequential control 23 able to programme and reading and writing bit-line load copied cells 25.WLL load copied cells 22 and reading and writing bit-line load copied cells 25 are as the load of the simulation reality of reading and writing sequential control 23 able to programme.In order better to carry out control able to programme, for the large scale SRAM that is formed by a plurality of (Bank), has respectively independently module 22,23 and 25.Other modules are the existing module of traditional SRAM among Fig. 2.SRAM storage array 21 is comprised of traditional 6 pipe units, the module of data link is by MUX CMUX) 212, sense amplifier (SA) 211 and input, output buffer 210 form, the word line decoding path drives 24 by one-level code translator 28 and two-stage decode and word line and forms, and inner sequential control circuit comprises sequential control circuit 29, SA sequential control 27, CMUX sequential control 26.28 outputs of one-level code translator connect two-stage decode and the word line drives 24 input, the word line drive signal that two-stage decode and word line drive 24 outputs connects able to programme reading, write the input of sequential control 23 and SRAM storage array 21, SRAM storage array 21 is output as the input of MUX (CMUX) 212, MUX (CMUX) 212 output connect sense amplifier (SA) 211 inputs, connect sense amplifier (SA) 211 and be output as input, the input of output buffer 210, input, output buffer 210 is output as SRAM and reads, write output and the input of data.Sequential control circuit 29 is the input of two-stage decode and the driving 24 of word line and CMUX sequential control 26, able to programme reading, write the output that is input as two-stage decode and word line driving 24 of sequential control 23, able to programme reading, write the input R0[n:0 of sequential control 23], W0[n:0] be connected to the output of control module 12 among Fig. 1, able to programme reading, the output of writing sequential control 23 connects WLL load copied cells 22 and reads, the input of write bit line load copied cells 25, able to programme reading, another output Rref that writes sequential control 23 is the input of SA sequential control 27, and the output of CMUX sequential control 26 and SA sequential control 27 is respectively the sequential control input end of MUX (CMUX) 212 and sense amplifier (SA) 211.

Sequential control circuit 23 able to programme is by the output signal R0[n:0 of control module among Fig. 1 12] and W0[n:0] carry out the control that reading and writing postpone, wherein n represents the bit wide of control signal.The numerical value of n is chosen and met the following conditions: n control sequential port is simultaneously for high, then WLL word line effectively export the time delay that the Rref signal raises to Fig. 4 should be less than 21 bit line discharges times of main body SRAM storage array in all process corner situations (the bit line discharges time be normally defined WLL and effectively arrives the bit line voltage drop to the time delay of sense amplifier SA offset voltage pressure reduction), usually the numerical value of n is greater than 1, and less than the line number of SRAM storage array 21.

Fig. 3 is a kind of traditional sequential time delay circuit of reading able to programme based on BIST control, in detail referring to paper " Robust SRAM design via BIST-assisted timing-tracking (BATT) ", the input of the output Connection-copy bit line unit 32 of WLL driven replication unit 31, copy the input that bit line unit 32 is output as delay path 33, the output that is input as delay path 33 of selection output 34 able to programme, selection output 34 able to programme is output as final timing control signal.Realize principle: WLL driven replication unit 31 is the duplicate circuit that SRAM word line WLL drives, and is used for driving and the delay of simulation word line WLL, can follow the tracks of preferably the delay of SRAM critical path.Memory cell replicate circuit 32 is comprised of an array storage unit identical with SRAM, wherein uses a plurality of storage unit as the driving of pairs of bit line, the output terminal of the WLL of these storage unit link 31, and the WLL port of other storage unit directly connects power supply ground.The output that copies bit line unit 32 connects chain of inverters 33, then realize the different outputs that postpone requirement by selection path 34, selection path 34 is comprised of transmission gate (M1-M6), the control signal of selecting is by Code[1:0] decide, by Code[1:0 is set] different coding, can select the output of different inhibit signals, thereby output signal OUT can realize programmable delay output.

For the circuit structure of Fig. 3, the selection path that provides typical two control signals postpones output, if actual needs more postpones situation, can obtain by the figure place that increases the Code coding, and principle and selection path 34 are similar.There are following two shortcomings in traditional read latency circuit able to programme: (1) programmable circuit obtains by the delay of chain of inverters, although original state can realize the different selections that postpone of signal, but in case normal operation, the delay of the delay of chain of inverters and actual SRAM storage unit discharge path is subjected to the impacts such as environment, negative bias temperature coefficient (NBTI) inconsistent, the tracing property of delay path is relatively poor, therefore can produce integrity problem when normal operation.(2) traditional delay path has increased chain of inverters, a plurality of transmission gate in path, therefore can limit the minimum delay that programmable delay circuit can reach, if therefore SRAM one row have less storage unit MC, then this programmable delay circuit can damage the performance of SRAM, has limited its application at high-performance SRAM.

Fig. 4 is the more excellent sequential time delay circuit able to programme based on BIST control of a kind of performance that the utility model proposes, and has realized time-sequence control module 11 able to programme among Fig. 1.Time-sequence control module 11 able to programme comprises WLL load copied cells 22, reading and writing sequential control 23 able to programme and reading and writing bit-line load copied cells 25 and WLL driven replication unit 31, and WLL load copied cells 22, reading and writing bit-line load copied cells 25 and WLL driven replication unit 31 all are traditional SRAM modules.Because the sequential time delay control circuit of read and write is similar, carry out selective analysis to read the sequential time delay control circuit as example.The output (output of code translator among the SRAM) that is input as word line (WLL) driven replication circuit 31 of sequential control circuit control end able to programme.Postpone to regulate the input signal R0[n:0 of control end] be the read control signal of 11 of control modules 12 and time-sequence control module able to programme among Fig. 1.The output of WLL driven replication circuit 31 connects transistor NPG0-NPGn grid end in the discharge loop array 42 able to programme, and 22 outputs of WLL load copied cells connect the output of WLL driven replication circuit 31, is used for simulation SRAM word linear load.NMOS pipe NPG0-NPGn grid end connects the output of WLL driven replication circuit 31 in the discharge loop array 42 able to programme, the source of NPG0-NPGn is connected with the drain terminal of NPD0-NPDn respectively, the source of NPD0-NPDn all is connected to low level VSS_core, the output R0[n:0 of control module 12 in the grid end connection layout 1 of NPD0-NPDn], the drain terminal of NPG0-NPGn links to each other as the output of discharge loop array 42 able to programme, the transmission transistor that NPG0-NPGn and NPD0-NPDn represent respectively 6 transistor memory units among the SRAM and pull-down transistor (definition of n and R0[n:0] and W0[n:0] in n identical), wherein NPG and NPD can be that a plurality of 6 transistor memory unit transfer tubes and lower trombone slide are in parallel and get, and number in parallel can suitably be regulated according to the delay requirement of reality.PMOS pipe P1 is used for the output of discharge loop array 42 able to programme is charged to supply voltage VDD.PMOS pipe P2 and NMOS pipe N1 form transmission gate, and P2 is connected discharge loop array 42 outputs able to programme with the N1 drain terminal, and P2 is connected the drain terminal of PMOS pipe P3 with the N1 source, and transistor P3 is used for output signal Rref is pre-charged to low level VSS.The grid end of P1, P3 and N1 goes out to link to each other with WLL driven replication circuit 31, and the output of WLL driven replication circuit 31 connects phase inverter INV1 input, and the output of INV1 connects the grid end of P2.Reading and writing bit-line load copied cells 25 is connected to the output of discharge loop array 42 able to programme, is used for the load of simulation SRAM bit line.The source of the drain terminal of P3, N1 and P2 all is connected to phase inverter INV2 input, and the output Rref of INV2 is the output of whole sequential control circuit.Fully consistent with the SRAM critical path on the delay path shown in Figure 4, bit line discharges also adopts lower trombone slide and the transfer tube of SRAM 6 transistor memory units, and is therefore better on the consistance of the impacts such as environment, negative bias temperature coefficient (NBTI), has more excellent reliability.In addition, programmable delay obtains by the discharge current that increases bit line, does not increase extra delay cell at delay path, therefore also can be fit to high-performance SRAM and use.

Comparison diagram 3 and Fig. 4, under the starting condition, two kinds of programmable delay circuits can both well be followed the tracks of the delay of actual SRAM critical path by extraneous control signal, as shown in Figure 5, after temperature variation, the delay variation of Fig. 3 conventional programmable delay circuit chain of inverters can not well be followed the tracks of the delay variation of actual SRAM critical path, and the programmable delay circuit delay variation of the utility model Fig. 4 can be good at following the tracks of SRAM Key Circuit delay variation, and therefore programmable delay circuit of the present utility model can have more superior reliability.

Claims (1)

1. SRAM sequential control circuit able to programme based on BIST control, comprise the BIST module, control module and the SRAM module that contains time-sequence control module able to programme, the SRAM module comprises: the SRAM storage array that is comprised of 6 transistors, by MUX, sense amplifier and input, the module of the data link that output buffer forms, the word line decoding path that is formed by one-level code translator and two-stage decode and word line driving circuit and by sequential control circuit, the sense amplifier sequential control circuit, the inside sequential control circuit that the MUX sequential control circuit forms; The output of one-level code translator connects the input of two-stage decode and word line driving circuit, the output of two-stage decode device connects the input of SRAM storage array, the output of SRAM storage array connects the input of MUX, the output of MUX connects the input of sense amplifier, the output of sense amplifier connects input, the input of output buffer, input, the SRAM that is output as of output buffer reads, write output and the input end of data, the output of sequential control circuit connects respectively the input of two-stage decode and word line driving circuit and MUX sequential control circuit, it is characterized in that: time-sequence control module able to programme is provided with able to programme reading, write sequential control circuit, word line WLL load copied cells and reading, write bit line load copied cells, able to programme reading, that writes sequential control circuit is input as reading of control module output, write control signal, able to programme reading, the output of writing sequential control circuit is connective word linear load copied cells and reading respectively, the input of write bit line load copied cells, able to programme reading, write sequential control circuit and also export the Enable Pin that the Rref signal connects the sense amplifier sequential control circuit, the output of word line WLL driven replication unit connects able to programme reading in two-stage decode and the word line driving circuit, write the sequential end of sequential control circuit, the connection of circuit is as follows:

Be provided with 3 PMOS pipes P1, P2, P3; 1 NMOS pipe N1; 2 phase inverter INV1, INV2 and n NMOS pipe NPG0, NPG1 ... NPGn and NPD0, NPD1 ... the discharge loop array able to programme that NPDn consists of, wherein, n represents the bit wide of control signal, the numerical value of n is greater than 1, less than the line number of SRAM storage array, NMOS pipe NPG0, NPG1 in the discharge loop array able to programme ... NPGn and NPD0, NPD1 ... NPDn is identical with transistor parameter in the SRAM storage array; NMOS manages NPG0, NPG1 ... the grid end of NPGn interconnects and is connected with the output of WLL driven replication unit, NMOS manages NPG0, NPG1 ... the source of NPGn is managed NPD0 with NMOS respectively, NPD1 ... the drain terminal of NPDn connects, NMOS manages NPD0, NPD1 ... the source of NPDn all is connected to low level VSS, NMOS manages NPD0, NPD1 ... the grid end of NPDn is reading for sequential control circuit able to programme, the write control signal input end, NMOS manages NPG0, NPG1 ... the interconnection of the drain terminal of NPGn and with read, the input end of write bit line load copied cells, the drain terminal of PMOS pipe P1, the drain terminal of the drain terminal of PMOS pipe P2 and NMOS pipe N1 links together, the grid end of PMOS pipe P1 and the output terminal of WLL driven replication unit, the input end of phase inverter INV1, the grid end of the grid end of PMOS pipe P3 and NMOS pipe N1 links together, the output terminal of phase inverter INV1 connects the grid end of PMOS pipe P2, the source of the source of PMOS pipe P2 and NMOS pipe N1, the drain terminal of PMOS pipe P3 and the input end of phase inverter INV2 link together, the source of the source of PMOS pipe P3 and PMOS pipe P1 all connects power vd D, and the output Rref of phase inverter INV2 is the output of whole sequential control circuit.

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