CN202650000U

CN202650000U - Multifunctional all-purpose asynchronous series UART interface module

Info

Publication number: CN202650000U
Application number: CN 201220295173
Authority: CN
Inventors: 王迈; 王磊
Original assignee: Individual
Current assignee: Individual
Priority date: 2012-06-21
Filing date: 2012-06-21
Publication date: 2013-01-02
Anticipated expiration: 2022-06-21

Abstract

The utility model discloses a multifunctional all-purpose asynchronous series UART (Universal Asynchronous Receiver/Transmitter) interface module, which comprises a CPU (Central Processing Unit) interface module, a transmitting FIFO (First-In and First-Out) module used for receiving and storing information, a receiving FIFO module used for storing and transmitting the information and a transmitting/receiving module, wherein the output of the CPU interface module is connected with the input of the transmitting FIFO module; the output of the transmitting FIFO module is connected with the input of a transmitting control module; the output of the transmitting module is connected with the input of the transmitting/receiving module; the output of the transmitting/receiving module is connected with the input of a receiving control module; the output of the receiving control module is connected with the input of the receiving FIFO module; the output of the receiving FIFO module is connected with the input of the CPU interface module; and the transmitting/receiving module is connected with a transmission line. The interface module has strong universal property and is convenient to use by a user, the transmitting/receiving FIFO module can achieve a data screening function, and data capacity is lowered.

Description

Multifunctional universal asynchronous serial UART interface module

Technical field

The utility model relates to a kind of multifunctional universal asynchronous serial UART interface module.

Background technology

UART is called again universal asynchronous serial interface, uses very extensive in fields such as communication, electronics and observing and controlling.The communication protocol of UART comprises start bit, data bit (normally 8), parity check bit and position of rest.Difference according to application scenarios, the agreement of using in the UART communication may be different, this is mainly reflected in the selection of communication format and baud rate (being traffic rate), for example, in the selection of parity check bit, some communication formats are odds, have plenty of even parity check, what also have does not have a verification, and the difference between above-mentioned application is that UART transplants between each system and brought inconvenience.Traditional UART module is receiving and is sending in the data procedures, whenever receive or send the signal (for example interrupts of CPU) of all can giving notice to the outside after the byte data, inform that the operation of its data transmit-receive finishes, to expect next time data manipulation, on this basis, also have now and in the UART module, embedded memory buffer (overwhelming majority is used FIFO), utilize buffer memory and the empty full state of the larger capacity of FIFO, reduce the number of times of UART with the communication handshake in the external world, thereby improved the efficient of UART in data transmission.But in the application scenario that has, need UART that the data that receive are had certain screening capacity and have more flexibly handshake communication ability, for example, in some GPS uses, only need speed and positional information, do not need other almanac datas, this just requires UART to have the data selection ability.The backward CPU of data that some application then require UART to receive certain fixed qty sends interruption.For above-mentioned these i.e. general specific application demands again, present UART does not also accomplish compatibility.

The utility model content

The purpose of this utility model is to solve the deficiencies in the prior art, provides a kind of use more flexible, the multifunctional universal asynchronous serial UART interface module that function is more powerful.

The purpose of this utility model is achieved through the following technical solutions: multifunctional universal asynchronous serial UART interface module, it comprises the cpu i/f module, the reception fifo module that is used for storing received information, the transmission fifo module and the sending/receiving module that are used for storage transmission information, the output of cpu i/f module is connected with the input that sends fifo module, the output that sends fifo module is connected with the input that sends control module, the output that sends control module is connected with the input of sending/receiving module, the output of sending/receiving module is connected with the input that receives control module, the output that receives control module is connected with the input that receives fifo module, and the output that receives fifo module is connected with the input of cpu i/f module; The cpu i/f module also is connected with main frame, and sending/receiving module also is connected with transmission line.

The beneficial effects of the utility model are: powerful versatility is received/is sent out fifo module and can realize the data screening function so that the user uses more easily, has reduced data volume; Adopt FIFO as the sending and receiving buffer memory, greatly reduced the required interruption times of traditional UART, and the minimizing of interruption times helps to improve real-time and the efficient of information handling system.

Description of drawings

Fig. 1 is the utility model structural representation.

Embodiment

Below in conjunction with accompanying drawing the utility model is described further: as shown in Figure 1, multifunctional universal asynchronous serial UART interface module, it comprises the cpu i/f module, the reception fifo module that is used for storing received information, the transmission fifo module and the sending/receiving module that are used for storage transmission information, the output of cpu i/f module is connected with the input that sends fifo module, the output that sends fifo module is connected with the input that sends control module, the output that sends control module is connected with the input of sending/receiving module, the output of sending/receiving module is connected with the input that receives control module, the output that receives control module is connected with the input that receives fifo module, and the output that receives fifo module is connected with the input of cpu i/f module.The cpu i/f module realizes the data interaction of UART and outer CPU, comprises that UART writes various configuration parameters and the data that will send to data and the CPU that CPU sends and receives to UART.The clock generating module produces reception and sends the baud rate clock according to the configuration parameter of CPU; Receive and send fifo module and be used for respectively the data of storing received and transmission, sending/receiving module to outside serial data bus sampling, extracts serial data stream and is combined into 8 bit data of standard when receive data; When sending, according to the communication format of CPU software configuration 8 bit data hytes are dressed up serial bit stream and send.Receive control module receive FIFO and and sending/receiving module between, mainly realize reading receive data and depositing in from sending/receiving module receiving the FIFO, and produce corresponding look-at-me according to the mode of operation configuration of UART.Send control module and sending between FIFO and the sending/receiving module, realize from send FIFO reading out data and send into the function that sends in the sendaisle of sending/receiving module.

The utility model comprises following three kinds of mode of operations:

The complete byte of the every transmitting-receiving of general mode: UART is namely sent (interruption) signal of shaking hands, and informs that its transmitting-receiving task of CPU finishes, and this pattern and traditional UART are compatible.

What data fifo mode: CPU at first receives by the register configuration UART of UART inside, then just sends interruption to CPU.When sending, if send the FIFO storer less than, namely storage sends data inside, when receiving, UART is according to pre-configured data, receives interrupts of CPU after the data of corresponding number, notifies its read data, and tells simultaneously the data amount check that CPU will read.

FIFO frame pattern: UART is according to the configuration of CPU to its frame head postamble, automatic reception belongs to Frame in the frame head postamble scope from communication channel, and simultaneously to the frame byte count, after frame data harvest and deposit FIFO in, send interruption to CPU, and tell the byte data number that CPU will read.

The utility model is a functional module of IC interior, is realized and is realized in integrated circuit by the programming of integrated circuit descriptive language.

Claims

1. multifunctional universal asynchronous serial UART interface module, it is characterized in that: it comprises the cpu i/f module, the reception fifo module that is used for storing received information, the transmission fifo module and the sending/receiving module that are used for storage transmission information, the output of cpu i/f module is connected with the input that sends fifo module, the output that sends fifo module is connected with the input that sends control module, the output that sends control module is connected with the input of sending/receiving module, the output of sending/receiving module is connected with the input that receives control module, the output that receives control module is connected with the input that receives fifo module, and the output that receives fifo module is connected with the input of cpu i/f module; The cpu i/f module also is connected with main frame, and sending/receiving module also is connected with transmission line.