CN202615163U - Main control board circuit based on high-performance DSP - Google Patents
Main control board circuit based on high-performance DSP Download PDFInfo
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- CN202615163U CN202615163U CN 201220081205 CN201220081205U CN202615163U CN 202615163 U CN202615163 U CN 202615163U CN 201220081205 CN201220081205 CN 201220081205 CN 201220081205 U CN201220081205 U CN 201220081205U CN 202615163 U CN202615163 U CN 202615163U
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- control board
- main control
- dsp
- board circuit
- cpld chip
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- 238000004891 communication Methods 0.000 abstract description 8
- 238000006243 chemical reaction Methods 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000005070 sampling Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003278 mimic effect Effects 0.000 description 1
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Abstract
The utility model relates to a main control board circuit belonging to electrical and electronic devices and based on a high-performance DSP (Digital Signal Processor). The main control board circuit is characterized in that a DSP processor is adopted as a control core; a main control board interface is connected with a CPLD chip, an A/D module, a D/A module, a random memory, an RAM memory, an RS485 controller, a CAN bus master, a SPI bus master and a power module respectively through address buses and data buses; the CPLD chip is applied for expanding the DSP control signals and an I/O interface; and the CPLD chip is connected with a dial switch. The main control board circuit which supports a plurality of external communication interfaces enables high-speed data exchanges among control panels and supports multi-path A/D and D/A conversion. Furthermore, the main control board circuit which has the advantages of high running speed and great stability can be applied in various electrical and electronic devices such as high-voltage frequency converters, SVG, APF, etc.
Description
Technical field
The utility model relates to a kind of master control borad circuit based on High Performance DSP.
Background technology
The pwm pulse width modulated is a kind of analog control mode; Its variation according to respective loads comes the biasing of modulation crystal tube grid or base stage; Realize switching power supply output transistor or the change of transistor turns time; This mode can make the output voltage of power supply when operation conditions change, keep constant, is to utilize the numeral of microprocessor to export a kind of very effective technology that mimic channel is controlled.The PWM control technology is simple with its control, flexibly and the good advantage of dynamic response and the control mode of the widespread use of the Power Electronic Technique that becomes also is the focus that people study.The processing speed of pwm circuit of the prior art and arithmetic capability are still waiting to improve.
Summary of the invention
Be to solve prior art problems, the purpose of the utility model provides and a kind ofly supports that multiple correspondence with foreign country function, data-handling capacity are strong, stable, supports multi-channel sampling, the master control borad circuit based on High Performance DSP that extended capability is strong.
For realizing above-mentioned purpose, the utility model is realized through following technical scheme:
A kind of master control borad circuit based on High Performance DSP; Is the control core with the dsp processor, respectively through address bus and data bus with CPLD chip, A/D module, D/A module, random access memory, RAM storer, RS485 controller, CAN bus controller, spi bus controller, reach power module and be connected.
Described CPLD chip is used to expand control signal and the I/O interface of DSP, and the CPLD chip connects toggle switch.
Compared with prior art, the beneficial effect of the utility model is:
1) the master control borad circuit outwards provides data bus and address bus, and expandability is strong.
2) this circuit all uses the technical grade chipset, and data processing speed is fast, and antijamming capability is strong.
3) support 18 road A/D, the D/A conversion.
4) support multiple external communication interface.
5) add toggle switch, support hardware is provided with the address.
Description of drawings
Fig. 1 is the structured flowchart of the utility model.
Embodiment
See Fig. 1; A kind of master control borad circuit based on High Performance DSP; Is the control core with the dsp processor, respectively through address bus and data bus with CPLD chip, A/D module, D/A module, random access memory, RAM storer, RS485 controller, CAN bus controller, spi bus controller, reach power module and be connected.
Described CPLD chip is used to expand control signal and the I/O interface of DSP, and the display control board running status connects the given control panel of toggle switch address etc.
Described dsp processor is the control core, and through address bus and other controller work of data bus control, described dsp processor also is connected with random access memory respectively; Described CPLD chip is used to expand control signal and the IO interface of DSP.
Externally communication part is used two-way RS485 communication and two-way CAN bus communication interface, and the RS485 controller uses the MAX1487ESA chip, and the CAN bus controller uses the PCA82C250T chip.Can also pass through expansion board expanding communication interface, comprise ethernet communication, usb communication etc.
The dsp processor governor circuit can carry out communicating by letter between the control panel through the data bus address bus that spi bus controller, CAN bus controller and expansion are come out.The CAN bus controller uses the PCA82C250T control chip, and the spi bus controller uses the FM25CL64 control chip.Dsp processor also extends out address bus and data bus, and data bus and address bus are connected on the external contact pin after carrying out Signal Spacing through chip SN74LVCH16T245DGGR, can write and read the information of other control panels like this.
The CPLD chip is used to expand the control signal and the I/O interface of dsp processor, and the display control board running status connects the given control panel of toggle switch address etc.State display lamp has four, shows CPU state, running status, malfunction and clock respectively.Toggle switch can 4 hardware address information of given control panel.
The A/D module has used 3 AD7656 chips to sample, and the D/A module has been used a DAC7724U chip.Can carry out the analog digital sampling of 18 tunnel high 16-bit and the digital-to-analogue conversion of 6 road 12-bit.The maximum throughput rate of analog digital conversion is 250KS/s.Can satisfy nearly all control signal sampling request.
Power module uses outside 15V and 5V power supply, and the inner integrated power supply module of plank converts external power source to each control chip required power supply, and has advantages of higher stability and anti-interference.
Dsp processor adopts the TMS320F28335 chip of TI company; It has the high speed processing ability of 150MHz; Possess 32 floating point processing units, 6 DMA passages are supported ADC, McBSP and EMIF, and nearly 18 tunnel PWM output is arranged; Wherein have 6 the tunnel to be the distinctive more high-precision PWM output of TI (HRPWM), 12 16 passage ADC.Have benefited from its FPU Float Point Unit, the user can write control algolithm fast and need not in the operation of processing decimal, to expend too much time and efforts, thereby simplifies software development, shortens the construction cycle, reduces cost of development.
Claims (2)
1. master control borad circuit based on High Performance DSP; It is characterized in that; Is the control core with the dsp processor, respectively through address bus and data bus with CPLD chip, A/D module, D/A module, random access memory, RAM storer, RS485 controller, CAN bus controller, spi bus controller, reach power module and be connected.
2. a kind of master control borad circuit based on High Performance DSP according to claim 1 is characterized in that described CPLD chip is used to expand control signal and the I/O interface of DSP, and the CPLD chip connects toggle switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220081205 CN202615163U (en) | 2012-03-06 | 2012-03-06 | Main control board circuit based on high-performance DSP |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220081205 CN202615163U (en) | 2012-03-06 | 2012-03-06 | Main control board circuit based on high-performance DSP |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202615163U true CN202615163U (en) | 2012-12-19 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220081205 Expired - Fee Related CN202615163U (en) | 2012-03-06 | 2012-03-06 | Main control board circuit based on high-performance DSP |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202615163U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104536918A (en) * | 2014-10-31 | 2015-04-22 | 成都朗锐芯科技发展有限公司 | Method for expanding IO (Input/Output) port of FPGA (Field-Programmable Gate Array) through CPLD (Complex Programmable Logic Device) |
-
2012
- 2012-03-06 CN CN 201220081205 patent/CN202615163U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104536918A (en) * | 2014-10-31 | 2015-04-22 | 成都朗锐芯科技发展有限公司 | Method for expanding IO (Input/Output) port of FPGA (Field-Programmable Gate Array) through CPLD (Complex Programmable Logic Device) |
| CN104536918B (en) * | 2014-10-31 | 2018-01-30 | 成都朗锐芯科技发展有限公司 | A kind of method of I/O port by CPLD spread Fs PGA |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20121219 Termination date: 20150306 |
|
| EXPY | Termination of patent right or utility model |