CN202564280U - Lead frame and semiconductor module - Google Patents
Lead frame and semiconductor module Download PDFInfo
- Publication number
- CN202564280U CN202564280U CN2012201808515U CN201220180851U CN202564280U CN 202564280 U CN202564280 U CN 202564280U CN 2012201808515 U CN2012201808515 U CN 2012201808515U CN 201220180851 U CN201220180851 U CN 201220180851U CN 202564280 U CN202564280 U CN 202564280U
- Authority
- CN
- China
- Prior art keywords
- lead
- lead frame
- lower bolster
- semiconductor module
- belt body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model provides a semiconductor module which is easy to manufacture and electromagnetic noise is hard to enter the semiconductor module through a lead frame and the periphery of the semiconductor module. The lead frame is provided with a lower bolster, an inner lead, a supporting lead, a framework frame, and a lead belt body surrounding the periphery of the lower bolster. Further, the semiconductor module is a resin package semiconductor module which is obtained when the lead frame is loaded with a power semiconductor element and a control semiconductor element in lapping mode and needless parts of the lead frame are cut off and removed, and is further provided with the lead belt body surrounding the periphery of the lower bolster of the lead frame of the loaded power semiconductor element. Further, the lead belt body surrounds a high-end power semiconductor element in a ring shape and is connected with only one grounding terminal. The lead belt body is a ring-shaped lead belt body only surrounding the high-end lower bolster of the power element and connected with only one grounding terminal.
Description
Technical field
The utility model relates to semiconductor module, the semiconductor module that particularly is used to carry the lead frame and a plurality of semiconductor elements of lift-launch of a plurality of semiconductor elements and has carried out resin-encapsulated.
Background technology
When using a plurality of semiconductor chip, the semiconductor modules that use the structure that is described below: on the lower bolster of lead frame, be equipped with semiconductor element, the mold resin high with insulating properties carried out resin-encapsulated more.In this semiconductor module, for example many uses are not to carry out simple switch motion, but have considered that fail safe etc. carries out more complicated action IPM (Intelligent Power Module).In IPM; Use power semiconductor that switch element (IGBT:Insulated Gate Bipolar Transistor etc.) constitutes and the IC (Integrated Circuit) that is used to control this switch element to wait simultaneously and control semiconductor element; They are carried out resin-encapsulated, in power inverters such as inverter, use.
At this moment, use lead frame and these semiconductor elements to constitute the circuit among the IPM, lead frame not only becomes the supporting substrate of these semiconductor elements, but also constitutes the distribution in this circuit.Therefore, in the structure of this semiconductor module, on the lower bolster of patterned lead frame, be equipped with each semiconductor element.In addition, constitute and around lower bolster, be provided with a plurality of lead-in wires, this lead-in wire is from the outstanding structure of mould layer.The part that should give prominence to becomes the input and output terminal in this semiconductor module.Because lead frame becomes the part of distribution, therefore constitute by conductance high copper or copper alloy.
In addition, particularly, receive the influence of electrical noise easily, therefore also require noise immunity high owing to the semiconductor element upper reaches super-high-current that constitutes at switch element.In the structure of the semiconductor module of this structure; Disclose the content that is described below as prior art: on the separating belt of the linearity that separates main circuit block and control circuit piece; On the conductive region of band shape, dispose lead frame (for example, with reference to patent documentation 1, Fig. 5).Thus, can prevent that control circuit is owing to the electromagnetic noise that on main circuit, produces is carried out misoperation.
[patent documentation 1] TOHKEMY 2000-133768 communique
Generally, in carrying the semiconductor module of a plurality of semiconductor elements, the influence of the electromagnetic noise that needs to produce from each element is suppressed at irreducible minimum.
But have the problem be described below in the prior art: though have the structure of separating main circuit block and control circuit piece, the lead frame of 1 band shape is very long, need hang lead-in wire, so instability and on property easy to manufacture, having problems.
In addition, also there is the problem that is described below:, therefore invade electromagnetic noise from the side of opening owing on the separating belt of linearity, form banded lead frame.
The utility model content
Therefore, the utility model is accomplished in order to address the above problem, and its purpose is, provide easy manufacturing, electromagnetic noise is difficult to from lead frame and the semiconductor module that gets on every side.
In order to address the above problem, the utlity model has the structure that is described below.
The lead frame of the utility model has lower bolster, inner lead, supporting wire, outside lead and peripheral frame frame, and lead frame has the lead-in wire belt body on every side around lower bolster.
In addition; The semiconductor module of the utility model; Be on lead frame, to carry power semiconductor and control semiconductor element; And cut off the resin sealed semiconductor module of removing not the needing part of lead frame and obtaining, and semiconductor module has the lead-in wire belt body, and this lead-in wire belt body is around the lower bolster of the lead frame that carries power semiconductor.
In addition, the lead-in wire belt body, only is connected with 1 earth terminal around the high-end semiconductor element of using with tubular shape.
In the utility model,, therefore have to provide and do not use the lead frame of revoking and making easily because the lead-in wire belt body is connected with outside terminal with ring-type.
And owing to use with the lead frame of lead-in wire belt body around the lower bolster that has carried the power semiconductor that receives the electromagnetic noise influence easily, therefore having to provide the semiconductor module that reduces the electromagnetic noise influence, obtains stable action.
Description of drawings
Fig. 1 is the vertical view of lead frame of the embodiment 1 of the utility model.
Fig. 2 is the vertical view of lead frame assembly of the embodiment 1 of the utility model.
Fig. 3 is the vertical view of semiconductor module of the embodiment 1 of the utility model.
Fig. 4 is the perspective plan view of semiconductor module of the embodiment 2 of the utility model.
Symbol description
1: lead frame; 2: lower bolster (low side is used lower bolster); 3: lower bolster (the high-end lower bolster of using); 4: lower bolster (lower bolster is used in control); 5: inner lead; 6: supporting wire; 7: outside lead; 8: tie-rod; 9: the framework frame; 10: the lead-in wire belt body; 11: the lead frame assembly; 12: power semiconductor (low side); 13: power semiconductor (high-end); 14: semiconductor element is used in control; 15: the mold resin; 16: cable; 17: screw portion; 18: protection semiconductor element (diode); 21,31: semiconductor module.
Embodiment
Below, specify the mode that is used to implement the utility model with reference to accompanying drawing.But the utility model at all is not limited to following record.
[embodiment 1]
Below, describe with reference to the lead frame and the semiconductor module of accompanying drawing the embodiment 1 of the utility model.Fig. 1 is the vertical view of lead frame of the embodiment 1 of the utility model.
As shown in Figure 1, lead frame 1 is made up of lower bolster 2,3,4 and inner lead 5, supporting wire 6, outside lead 7, tie-rod 8, framework frame 9, lead-in wire belt body 10.The lead frame 1 that in semiconductor, uses is generally made through flat metallic plate is carried out punch process.For example, can use copper or copper alloy for lead frame 1 with 0.4mm thickness.The pattern of the semiconductor module amount of here, stating after having represented.As the lead frame of reality, be connected with a plurality of these patterns.
Inner lead 5 has an end, and portion uses as wire-bonded.Another end is connected with tie-rod 8.
In supporting wire 6, an end is connected with each lower bolster 2,3,4, and another end is connected with lower bolster 8.Thus, support each lower bolster.
Externally go between in 7, an end is connected with supporting wire 6 with inner lead 5 via lower bolster 8.Another end is connected with the framework frame.This position becomes the outside terminal of semiconductor module.
Tie-rod 8 is connected maintenance with inner lead 5, supporting wire 6 and outside lead 7, and is connected with framework frame 9.Fixing by mechanically thus.
Framework frame 9 is positioned at the peripheral part of lead frame 1, centers on the pattern of lead frame 1 and is connected maintenance with tie-rod 8.
Lead-in wire belt body 10 is connected with tie-rod 8 around the periphery of lower bolster 3, is connected with framework frame 9 through outside lead 7.Owing to be to center on, therefore two places are connected on tie-rod 8 and outside lead 7.Thus, make high distolateral lower bolster independent.
Fig. 2 is the vertical view of lead frame assembly of the embodiment 1 of the utility model.As shown in Figure 2, lead frame assembly 11 carries power semiconductor 12 on the lower bolster 2, power semiconductor 13 is carried on lower bolster 3, will control semiconductor element 14 lift-launchs on lower bolster 4 through (not shown) such as scolders.Afterwards, be electrically connected with an end of inner lead 5 with the surface electrode of cables such as golden fine rule (not shown) through lead wire connecting apparatus each semiconductor element.
Equally, power semiconductor 13 is high distolateral MOS, and overall dimension is 1.8mm * 3.0mm.3 element mountings are on common lower bolster 3.
Afterwards,, carry out resin-encapsulated, form mold resin 15 through the transfer modling device.Resin-encapsulated with covering be equipped with the lower bolster 2,3,4, inner lead 5 of power semiconductor 12,13 and control semiconductor element 14, the mode of lead-in wire belt body 10 is carried out resin-encapsulated, outside lead 7, tie-rod 8, framework frame 9 are exposed to the outside.For example, can use thermosetting epoxy resin for mold resin 15.
Afterwards, cut off to remove lead frame 1 maintaining part, be unwanted position, be tie-rod 8 and framework frame 9.Here, outside lead 7 is outstanding from the mold resin 15 of rectangular shape.This outside lead 7 uses as electric input and output terminal, is shaped to by going between to be suitable for the shape (not shown) that substrate is installed.
More than, accomplished semiconductor module shown in Figure 3 21.In Fig. 3,, become the inner lead-in wire belt body 10 of resin die 15 and the state of lower bolster 3 of being shown in broken lines for the ease of explanation.
Then, the lead frame frame 1 of the foregoing description 1 and the effect of semiconductor module 21 are described.
The lead frame 1 of the embodiment 1 of the utility model has around lower bolster 3 lead-in wire belt body 10 on every side.Thus, in lead frame,, therefore can when the punching press of compression process, make simultaneously, thereby can make stable lead frame easily owing to insert lead-in wire belt body integrated with the lead frame pattern and that be connected with outside lead.
The semiconductor module 21 of the embodiment 1 of the utility model has the lead-in wire belt body 10 on every side around the lower bolster 3 of the lead frame 1 that is equipped with power semiconductor 13.Thus, in semiconductor module, high distolateral MOS is high voltage lower bolster (power supply terminal), and high distolateral MIC is installed on the general lower bolster (public terminal).When the UVW of each MOSFET and MIC has carried out switch motion respectively mutually, propagate electromagnetic noise from MOSFET, might cause the misoperation of high distolateral MIC.Therefore, owing between high voltage lower bolster and public lower bolster, be inserted with the lead-in wire belt body, therefore pass through to absorb electromagnetic noise, thereby can realize the operating stably of MIC.
In addition, owing to enter into high distolaterally easily from the electromagnetic noise of outside, so Min. ground can reduce the electromagnetic noise influence that power semiconductor receives around high distolateral.
In addition, because the lead-in wire belt body has the tubular shape that only centers on the high-end lower bolster of power semiconductor, therefore high distolateral MIC has concurrently for the logical gate that COM is moved with for the high-end island (floating portion) to the high tension voltage action.In order to make 1 MIC according to these 2 different high-voltages and operating stably, need make MOS portion stable according to the ring-type of floating frame, the operating stably of the MOS that can cause through the generation by electric field suppresses the generation of electromagnetic noise.
In addition, owing to the lead-in wire belt body is tubular shape and only is connected with 1 earth terminal, electric current is flow through on the lead-in wire belt body to 1 direction.In addition, be positioned at the high distolateral lower bolster (high pressure position) of ring center through centering on, thereby can be created in the magnetic field that produces on the high distolateral lower bolster on the direction vertical with lead frame.Thus, magnetic field can be become, the stable function of formation that makes raceway groove can be accessed for the raceway groove vertical direction of MOS.
As stated, though put down in writing the mode that is used to implement the utility model, the knowledge capital those skilled in the art can openly obtain various replacement execution modes, embodiment from this.
In above-mentioned example,, also can have 2 according to the circuit condition of installation base plate though earth terminal is 1.At this moment, on installation base plate, become ring circuit.In addition, also can on internal circuit, be fixed as positive potential.
In addition, though allocating power semiconductor element and control semiconductor element point-blank also can be configured in roughly on the plane.For example, as embodiment 2, can use semiconductor module as shown in Figure 4 31.If with the mode configuring semiconductor element that tangles mutually, then can dwindle the area of the pattern of lead frame.Thus, owing to, therefore carry out layout designs at leisure not with straight line separate configuration semiconductor element.Thus, other semiconductor device can be carried, the further miniaturization of encapsulation can be made.In Fig. 4, for the ease of explaining, becoming lead-in wire belt body 10 is intersected, had an X-rayed the state of the inside of mold resin 15.
Here, as other boarded parts, the lower bolster of lift-launch protection semiconductor element 18 (1.2mm * 1.2mm).For electric distribution, use cable 16, use the golden fine rule of 35 microns of diameters.And encapsulation has rectangular shape, on the Width end face, has screw portion 17.Thus, can be directed against the joint of heating panel etc. easily.
Claims (4)
1. lead frame, it has lower bolster, inner lead, supporting wire, outside lead and framework frame, and this lead frame is characterised in that,
This lead frame has the lead-in wire belt body on every side around lower bolster.
2. semiconductor module, it is on lead frame, to carry power semiconductor and control semiconductor element, and cuts off the resin sealed semiconductor module of removing not the needing part of said lead frame and obtaining, this semiconductor module is characterised in that,
This semiconductor module has the lead-in wire belt body, and this lead-in wire belt body is around the lower bolster of the said lead frame that carries said power semiconductor.
3. semiconductor module according to claim 2 is characterized in that,
Said lead-in wire belt body is a tubular shape.
4. according to claim 2 or 3 described semiconductor modules, it is characterized in that,
Said power semiconductor is the high-end power semiconductor of using, and said lead-in wire belt body only is connected with 1 earth terminal.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2012-049854 | 2012-03-06 | ||
| JP2012049854A JP2013187266A (en) | 2012-03-06 | 2012-03-06 | Lead frame and semiconductor module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202564280U true CN202564280U (en) | 2012-11-28 |
Family
ID=47213906
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012201808515U Expired - Fee Related CN202564280U (en) | 2012-03-06 | 2012-04-25 | Lead frame and semiconductor module |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2013187266A (en) |
| CN (1) | CN202564280U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103000536A (en) * | 2012-12-07 | 2013-03-27 | 天水华天微电子股份有限公司 | Preparation technology for intelligent power modules |
| CN112382576A (en) * | 2016-05-26 | 2021-02-19 | 三菱电机株式会社 | Semiconductor device and method for manufacturing the same |
-
2012
- 2012-03-06 JP JP2012049854A patent/JP2013187266A/en active Pending
- 2012-04-25 CN CN2012201808515U patent/CN202564280U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103000536A (en) * | 2012-12-07 | 2013-03-27 | 天水华天微电子股份有限公司 | Preparation technology for intelligent power modules |
| CN103000536B (en) * | 2012-12-07 | 2016-01-20 | 天水华天微电子股份有限公司 | A kind of preparation technology of Intelligent Power Module |
| CN112382576A (en) * | 2016-05-26 | 2021-02-19 | 三菱电机株式会社 | Semiconductor device and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2013187266A (en) | 2013-09-19 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20121128 Termination date: 20210425 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |