CN202712183U - Semiconductor module - Google Patents
Semiconductor module Download PDFInfo
- Publication number
- CN202712183U CN202712183U CN2012201803865U CN201220180386U CN202712183U CN 202712183 U CN202712183 U CN 202712183U CN 2012201803865 U CN2012201803865 U CN 2012201803865U CN 201220180386 U CN201220180386 U CN 201220180386U CN 202712183 U CN202712183 U CN 202712183U
- Authority
- CN
- China
- Prior art keywords
- lead
- belt body
- semiconductor module
- lower bolster
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model provides a miniaturized semiconductor module which can improve heat radiation performance on a lead frame. The semiconductor module is a resin package type semiconductor module which is obtained when the lead frame is loaded with power semiconductor elements and control semiconductor elements. The semiconductor module comprises a lead belt body for separating lower bolsters of the power semiconductor elements. The lead belt body comprises a lead belt body (A) which surrounds lower bolsters loaded with high-end side power semiconductor elements and a lead belt body (b) which separates the side parts of the lower bolsters loaded with lower-end side power semiconductor elements according to a straight line. Besides, the lead belt body is connected with an external terminal and arranged near a screw fixing part of a mold resin.
Description
Technical field
The utility model relates to semiconductor module, particularly carries a plurality of semiconductor elements and has carried out the semiconductor module of resin-encapsulated at lead frame.
Background technology
When using a plurality of semiconductor chip, use the semiconductor module of structure as described below: be equipped with semiconductor element on the lower bolster of lead frame, the mold resin high with insulating properties carried out resin-encapsulated more.In this semiconductor module, for example many uses are not to carry out simple switch motion, but have considered that fail safe etc. carries out more complicated action IPM (Intelligent Power Module).In IPM, use simultaneously the power semiconductor that switch element (IGBT:Insulated Gate Bipolar Transistor etc.) consists of and the control semiconductor elements such as IC (Integrated Circuit) that are used for this switch element of control, they are carried out resin-encapsulated, in the power inverters such as inverter, use.
At this moment, consist of circuit among the IPM with lead frame and these semiconductor elements, lead frame not only becomes the supporting substrate of these semiconductor elements, but also consists of the distribution in this circuit.Therefore, in the structure of this semiconductor module, on the lower bolster of patterned lead frame, be equipped with each semiconductor element.In addition, constitute and be provided with a plurality of lead-in wires around lower bolster, this lead-in wire is from the outstanding structure of mould layer.The part that should give prominence to becomes the input and output terminal in this semiconductor module.Because lead frame becomes the part of distribution, therefore consisted of by conductance high copper or copper alloy.
In addition, particularly owing to the semiconductor element upper reaches super-high-current that consists of at switch element, be subject to easily the impact of electrical noise, therefore also require noise immunity high.In the structure of the semiconductor module of this structure, disclose content as described below as prior art: on the separating belt of the linearity that separates main circuit block and control circuit piece, conductive region in band shape disposes lead frame (for example, with reference to patent documentation 1, Fig. 5).Thus, can prevent that control circuit is owing to the electromagnetic noise that produces at main circuit is carried out misoperation.
[patent documentation 1] TOHKEMY 2000-133768 communique
Generally, in carrying the semiconductor module of a plurality of semiconductor elements, need the impact of the electromagnetic noise that will produce from each element to be suppressed at irreducible minimum.
But have in the prior art problem as described below: although have the structure of separating main circuit block and control circuit piece, owing to do not make the position of the heat release that produces in main circuit, therefore the thermal diffusivity at lead frame has problems.
In addition, owing to separate leads framework on straight line, therefore exist encapsulation to become large problem.
The utility model content
Therefore, the utility model is finished in order to address the above problem, and its purpose is, the semiconductor module that improves the thermal diffusivity on the lead frame and make the encapsulation miniaturization is provided.
In order to address the above problem, the utlity model has structure as described below.
Semiconductor module of the present utility model is the resin sealed semiconductor module of carrying power semiconductor and control semiconductor element at lead frame, and this semiconductor module has the lead-in wire belt body of the lower bolster of separative power semiconductor element.
In addition, have: around the lower bolster that carries high distolateral power semiconductor lead-in wire belt body A on every side; And the sidepiece that will carry the lower bolster of low distolateral power semiconductor comes lead-in wire belt body B separately and lead-in wire belt body C by straight line.
In addition, the lead-in wire belt body is connected with outside terminal, and is provided near the screw fixed part of mold resin.
The utlity model has effect as described below: owing to have the lead-in wire belt body that separates lower bolster, therefore the isolation pyrotoxin can provide the semiconductor module that has improved the thermal diffusivity on the lead frame.
In addition, has effect as described below: owing to around the lower bolster that carries high distolateral power component, therefore need not unnecessarily have very large area, can provide the semiconductor module of having realized miniaturization.
Description of drawings
Fig. 1 is the vertical view of the lead frame of embodiment 1 of the present utility model.
Fig. 2 is the vertical view of the lead frame assembly of embodiment 1 of the present utility model.
Fig. 3 is the perspective plan view of the semiconductor module of embodiment 1 of the present utility model.
Fig. 4 is the perspective plan view of the semiconductor module of embodiment 2 of the present utility model.
Symbol description
1: lead frame; 2: lower bolster (low side lower bolster); 3: lower bolster (the high-end lower bolster of using); 4: lower bolster (control lower bolster); 5: inner lead; 6: supporting wire; 7: outside lead; 8: tie-rod; 9: the framework frame; 10A, 10B, 10C: lead-in wire belt body; 11: the lead frame assembly; 12: power semiconductor (low side); 13: power semiconductor (high-end); 14: the control semiconductor element; 15: the mold resin; 16: cable; 17: the screw fixed part; 18: protection semiconductor element (diode); 21,31: semiconductor module.
Embodiment
Below, describe in detail for implementing mode of the present utility model with reference to accompanying drawing.But the utility model at all is not limited to following record.
[embodiment 1]
Below, describe with reference to lead frame and the semiconductor module of accompanying drawing to embodiment 1 of the present utility model.Fig. 1 is the vertical view of the lead frame of embodiment 1 of the present utility model.
As shown in Figure 1, lead frame 1 by lower bolster 2,3,4 and inner lead 5, supporting wire 6, outside lead 7, tie-rod 8, framework frame 9, lead-in wire belt body 10 consist of.The lead frame 1 of using in semiconductor is generally made by flat metallic plate is carried out punch process.For example, can use copper or the copper alloy with 0.4mm thickness for lead frame 1.The pattern that has represented a semiconductor module amount described later herein.As the lead frame of reality, be connected with a plurality of these patterns.
In supporting wire 6, an end is connected with each lower bolster 2,3,4, and another end is connected with lower bolster 8.Thus, support each lower bolster.
Externally going between in 7, is connected with supporting wire via lower bolster 8 and inner lead 5 and is connected in end.Another end is connected with the framework frame.This position becomes the outside terminal of semiconductor module.
Tie-rod 8 is connected inner lead 5, supporting wire 6 and connect is kept with outside lead, and is connected with framework frame 9.Mechanically fixed thus.
Lead-in wire belt body 10A is connected with tie-rod 8 around the periphery of lower bolster 3, is connected with framework frame 9 by outside lead 7.Owing to be to center on, therefore connect with two places on outside lead is connected at tie-rod 8.Thus, make high distolateral lower bolster independent.
Lead-in wire belt body 10B connects the interval between the lower bolster 2, is connected with up and down tie-rod 8 among the figure, is connected with framework frame 9 by outside lead 7.
Lead-in wire belt body 10C connects the outside (right side among the figure) of lower bolster 2, is connected with up and down tie-rod 8 among the figure, is connected with framework frame 9 by outside lead 7.
Because it is little and divided to hang down each area of distolateral lower bolster, therefore have a plurality of lead-in wire belt bodies.
Because lead-in wire belt body 10B and lead-in wire belt body 10C almost parallel make low distolateral lower bolster independent, therefore mechanically, thermally connect.
Herein, the displacement of the lead frame pattern when preventing resin filling, the width of lead-in wire belt body 10A, 10B, 10C be preferably between the lower bolster more than 1/3.For example, when being spaced apart 1.0mm, can be made as 3.5mm.In addition, when making lead frame by pressure processing, in order to prevent distortion when the processing and manufacturing, preferably become more than the thickness of lead frame 1.For example, when thickness is 0.4mm, can be made as 0.6mm.Select in also can be from 0.4mm to 0.8mm.
Fig. 2 is the vertical view of the lead frame assembly of embodiment 1 of the present utility model.As shown in Figure 2, lead frame assembly 11 carries power semiconductor 12 on the lower bolster 2, power semiconductor 13 is carried on lower bolster 3, will control semiconductor element 14 lift-launchs on lower bolster 4 by (not shown) such as scolders.Afterwards, be electrically connected with an end of inner lead 5 with the surface electrode of the cables such as golden fine rule (not shown) with each semiconductor element by lead wire connecting apparatus.
Equally, power semiconductor 13 is high distolateral MOS, and overall dimension is 1.8mm * 3.0mm.3 element mountings are on common lower bolster 3.
Afterwards, by the transfer modling device, carry out resin-encapsulated, form mold resin 15.Resin-encapsulated with covering be equipped with power semiconductor 12,13 and the lower bolster 2,3,4, inner lead 5 of control semiconductor element 14, the mode of lead-in wire belt body 10 carry out resin-encapsulated, outside lead 7, tie-rod 8, framework frame 9 are exposed to the outside.For example, can use thermosetting epoxy resin for mold resin 15.
Then, shearing cut-out removes the unwanted position of the maintaining part of lead frame 1, is tie-rod 8 and framework frame 9.Herein, outside lead 7 is outstanding from the mold resin 15 of rectangular shape.This outside lead 7 uses as electric input and output terminal, is shaped to by going between to be suitable for the shape (not shown) that substrate is installed.
More than, finished semiconductor module shown in Figure 3 21.In Fig. 3, for convenience of explanation, become lead-in wire belt body 10A, 10B, 10C are intersected, had an X-rayed the state of the inside of mold resin 15.
Then, the effect of the semiconductor module 21 of above-described embodiment 1 described.
By the action (energising) of semiconductor module, power semiconductor alternately generates heat.Produce warping stress at lower bolster by heat, the stress influence for the lower bolster that has carried the control semiconductor element occurs.Resin shrinkage when particularly, the mold resin after the action cools off is large.
The lead frame 1 of embodiment 1 of the present utility model has: around the lower bolster 3 lead-in wire belt body 10A on every side that carries high distolateral power semiconductor 13; And the sidepiece that will carry the lower bolster 2 of low distolateral power semiconductor 12 comes lead-in wire belt body 10B, 10C separately according to straight line.Thus, in semiconductor module, at the power semiconductor adstante febre, because lower bolster is isolated by this lead-in wire belt body, so be cut off for other the heat transfer of semiconductor element.In addition, because this lead-in wire belt body is connected with outside lead, therefore the heat that receives is conducted heat, can dispel the heat to the outside of mold resin.
The semiconductor module of embodiment 1 of the present utility model has the lead-in wire belt body, the lower bolster that this lead-in wire belt body makes the lead frame that carries power semiconductor height distolateral and low distolateral on independence.Thus, in semiconductor module 21 because can independently dispel the heat, heat insulation, therefore in the warming-up effect in the time can suppressing to move, make the encapsulation miniaturization.
In addition, owing to coming around with lead-in wire belt body 10A or cutting apart power semiconductor, therefore can suppress the impact that is caused by electromagnetic noise.Particularly, because high distolateral semiconductor element is subject to the impact of electromagnetic noise easily, be effective therefore.
In addition, lead-in wire belt body 10B, 10C are connected with outside lead 7, as GND terminal (earth terminal).Because this outside lead 7 is two side-prominent from encapsulation (mold resin 15), therefore can when designing, mounting circuit carry out easily the distribution design, and easy to use.
As mentioned above, be used for implementing mode of the present utility model although put down in writing, those skilled in the art can obtain various replacement execution modes, embodiment from the disclosure as can be known.
In above-mentioned example, although point-blank allocating power semiconductor element and control semiconductor element also can be configured in roughly on the plane.For example, as embodiment 2, can use semiconductor module 31 as shown in Figure 4.If with the mode configuring semiconductor element that tangles mutually, then can dwindle the area of the pattern of lead frame.Thus, owing to not with linearity separate configuration semiconductor element, therefore carry out at leisure layout designs.Thus, can make the further miniaturization of encapsulation.In Fig. 4, for convenience of explanation, become lead-in wire belt body 10A, 10B, 10C are intersected, had an X-rayed the state of the inside of mold resin 15.
In addition, herein, as other boarded parts, the lower bolster of lift-launch protection semiconductor element 18 (1.2mm * 1.2mm)., use cable 16 herein, use the golden fine rule of 35 microns of diameters.
In addition, among the figure of lead-in wire belt body 10A among the figure of left side, lead-in wire belt body 10C the right side be positioned near the screw fixed part 17 of encapsulation of mold resin 15.Thus, owing to approach with power semiconductor, therefore can when normal temperature, relax the impact of the stress (temperature cycle during action) of the thermal expansion that causes carrying out resin that screw fixes fixedly the time to generate heat.
In addition, although high distolateral lead-in wire belt body 10A is connected with the outside lead of encapsulation one side in the mode around lower bolster 3, for pattern layout, also can export to the encapsulation sidepiece of opposite side.Thus, the short circuit of mounting circuit is easy to use.
Claims (4)
1. semiconductor module, it is the resin sealed semiconductor module of carrying power semiconductor and control semiconductor element at lead frame,
This semiconductor module is characterised in that to have the lead-in wire belt body, and this lead-in wire belt body separates the lower bolster of described power semiconductor.
2. semiconductor module according to claim 1 is characterized in that,
Described lead-in wire belt body has: around the lower bolster that is equipped with high distolateral power semiconductor lead-in wire belt body (A) on every side; And the sidepiece that will be equipped with the lower bolster of low distolateral power semiconductor the lead-in wire belt body (B) and the belt body (C) that goes between that separate by straight line.
3. semiconductor module according to claim 1 and 2 is characterized in that,
Described lead-in wire belt body is connected with outside terminal.
4. semiconductor module according to claim 1 is characterized in that,
Described lead-in wire belt body is provided near the screw fixed part of mold resin.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2012049855A JP2013187267A (en) | 2012-03-06 | 2012-03-06 | Semiconductor module |
| JP2012-049855 | 2012-03-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202712183U true CN202712183U (en) | 2013-01-30 |
Family
ID=47592459
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012201803865U Expired - Fee Related CN202712183U (en) | 2012-03-06 | 2012-04-25 | Semiconductor module |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP2013187267A (en) |
| CN (1) | CN202712183U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104867839A (en) * | 2014-02-21 | 2015-08-26 | 三垦电气株式会社 | Manufacturing method of semiconductor device and semiconductor device |
-
2012
- 2012-03-06 JP JP2012049855A patent/JP2013187267A/en active Pending
- 2012-04-25 CN CN2012201803865U patent/CN202712183U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104867839A (en) * | 2014-02-21 | 2015-08-26 | 三垦电气株式会社 | Manufacturing method of semiconductor device and semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2013187267A (en) | 2013-09-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6683795B1 (en) | Shield cap and semiconductor package including shield cap | |
| JP2009135444A (en) | Package for power semiconductor device | |
| JP2023033351A (en) | Semiconductor device | |
| CN101142675B (en) | An integrated circuit package device with improved bond pad connections, a leadframe and an electronic device | |
| JP2010267728A (en) | Semiconductor package, lead frame, and method of manufacturing the semiconductor package | |
| US20140103505A1 (en) | Die down integrated circuit package with integrated heat spreader and leads | |
| JP5378683B2 (en) | Circuit device and manufacturing method thereof | |
| KR20020066483A (en) | Semiconductor Package And Mounting Structure On Substrate Thereof And Stack Structure Thereof | |
| JP6668393B2 (en) | Semiconductor package having heat slug and die mounting area without rivets | |
| JP2017017109A (en) | Semiconductor device | |
| US20110278706A1 (en) | Power Electronic Device Package | |
| KR20150072898A (en) | Semi-Conductor Package and the Method of Manufacturing for the same | |
| US20150294925A1 (en) | Quad flat no-lead package and manufacturing method thereof | |
| US20220045025A1 (en) | Semiconductor package structure and manufacturing method thereof | |
| CN202712183U (en) | Semiconductor module | |
| JP6597499B2 (en) | Semiconductor device and manufacturing method thereof | |
| WO2014120894A1 (en) | Circuit assembly | |
| CN107342276B (en) | Semiconductor device and corresponding method | |
| CN202564280U (en) | Lead frame and semiconductor module | |
| CN106328620B (en) | Integrated circuit package and method of manufacturing the same | |
| JP2010109255A (en) | Semiconductor device | |
| CN202549841U (en) | Semiconductor module | |
| JP2005353713A (en) | Semiconductor device | |
| US9324639B2 (en) | Electronic device comprising an improved lead frame | |
| JP2004022968A (en) | Semiconductor device and method of manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130130 Termination date: 20210425 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |