CN202549832U - Cantilever-type stacked integrated circuit (IC) chip packaging piece based on barium titanate (BT) substrate - Google Patents
Cantilever-type stacked integrated circuit (IC) chip packaging piece based on barium titanate (BT) substrate Download PDFInfo
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- CN202549832U CN202549832U CN2012201418088U CN201220141808U CN202549832U CN 202549832 U CN202549832 U CN 202549832U CN 2012201418088 U CN2012201418088 U CN 2012201418088U CN 201220141808 U CN201220141808 U CN 201220141808U CN 202549832 U CN202549832 U CN 202549832U
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
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- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
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- H01L2924/181—Encapsulation
Abstract
The utility model discloses a cantilever-type stacked integrated circuit (IC) chip packaging piece based on a barium titanate (BT) substrate, comprising a substrate carrier to which a BT substrate is adhered. At least three layers of IC chips with the same shape and size are stacked on and adhered to the substrate. A substrate back pad is arranged at the back of the substrate carrier and connected with a substrate front pad. An embossment, solder and a solder ball are successively arranged at the surface of the substrate back pad. The adjacent layers of IC chips are arranged in a stagger way with the same stagger distance and connected by virtue of a bonding line. One layer of IC chips on the substrate is connected with the substrate front pad by virtue of a bonding line. The packaging piece can reduce the height of each layer of bonding line maximumly and avoid line short-circuit among different ring-shaped layers of bonding lines.
Description
Technical field
The utility model belongs to electronic information Element of automatic control manufacturing technology field, relates to the chip-stacked packaging part of a kind of IC, relates in particular to a kind of chip-stacked packaging part of overarm formula IC of BT substrate.
Background technology
Along with the continuous development of microminiaturization and performance boost trend, the designer constantly seeks in as far as possible little space, to obtain high as far as possible electric function and performance.Two critical limitation factors that exist in this course are integrated level and I/O pins limits normally.Chip space be connected restriction and can solve from two different levels: first method is that the technology yardstick through label (or claim nude film) level dwindles and realizes higher integrated level; Second method is through piling up a plurality of labels, and promptly stacked package or stack circuit board are realized higher integrated level.On the basis of existing chip fabrication techniques, chip-stacked mode is to utilize prior art to obtain the prefered method of memory density of future generation, and can realize dissimilar (like numeral, simulation, logic etc.) chip chamber stacked package, realizes systemic function.
Raising along with chip, wafer and package level; In stacked package, the complexity that low profile wire bond technology (or overarm formula wire bond technology) limitation in height and stack technology configuration increase has proposed some special challenges to the brave technology of silk in laminated chips is used.When chip thickness reduces, the corresponding minimizing in gap between the different wire loop layers.Need to reduce the lead-in wire bonding loop of lower level, to avoid the line short circuit between the different annulate lamellas.The annular top layer also need keep low level, to eliminate the phenomenon that goes out bonding wire in the molding compounds outer exposed.The loop that device is maximum should not be higher than the chip thickness that keeps best slit between the annulate lamella.In addition, the increase of line density and line length in the encapsulation of molding technology laminated chips makes the moulding stacked package more difficult more than traditional single-chip package.The annular of the lead-in wire bonding of different layers, the influence of the various tractive effort that changed can form the various changes of bonding wire deviation, thereby has increased the possibility of bonding wire short circuit.
The utility model content
In order to overcome the problem that exists in the above-mentioned prior art; The purpose of the utility model provides a kind of chip-stacked packaging part of overarm formula IC of BT substrate; No warpage does not have the silk of friendship short circuit phenomenon, in order to solve identical stacked package and the monolateral bonding wire problem of chip size size.
For realizing above-mentioned purpose, the technical scheme that the utility model adopted is: a kind of chip-stacked packaging part of overarm formula IC of BT substrate comprises substrate carrier; Be pasted with substrate on the substrate carrier, pile up on the substrate and be pasted with the IC chip, the substrate carrier back side is provided with the substrate back pad; The substrate back pad substrate front side pad positive with being positioned at substrate carrier is connected, and the substrate back bond pad surface is provided with salient point and tin ball successively, it is characterized in that; Substrate is the BT substrate, and the IC chip is at least three layers, and adjacent two-layer IC chip along continuous straight runs shifts to install; And the dislocation distance is identical; The overall dimension of all IC chips is identical, and adjacent two layers IC chip is connected through bonding line, and one deck IC chip that is pasted on the substrate is connected with the substrate front side pad through the triple bond zygonema.
Dislocation distance between the said adjacent two layers IC chip is 0.35mm～2.5mm.
IC chip dislocation in the utility model packaging part is piled up; Form suspension beam structure; And the IC chip that only is pasted on the substrate links to each other with substrate pads through bonding line, makes the height of each layer bonding line reduce to greatest extent, has avoided the line short circuit between the different annulate lamella bonding lines.Make the top layer bonding line also to keep low level simultaneously, eliminated the phenomenon that the molding compounds outer exposed goes out bonding wire.In addition, also avoid the influence of the various tractive effort that the annular of the lead-in wire bonding of different layers changed, reduced the possibility of bonding wire short circuit.Stacked package and monolateral bonding wire problem when the chip size size is identical have been solved.
Description of drawings
Fig. 1 is the structural representation of 3 layers of chip-stacked encapsulation of IC in the utility model stack package.
Fig. 2 is the structural representation of 4 layers of chip-stacked encapsulation of IC in the utility model stack package.
Fig. 3 is the structural representation of 5 layers of chip-stacked encapsulation of IC in the utility model stack package.
Fig. 4 is the structural representation of 6 layers of chip-stacked encapsulation of IC in the utility model stack package.
Among the figure, 1. substrate carrier, 2. first bonding die, 3. an IC chip, 4. second bonding die, 5. substrate; 6. the 2nd IC chip, 7. the 3rd bonding die, 8. the 3rd IC chip, 9. first bonding line, 10. second bonding line, 11. triple bond zygonemas; 12. plastic-sealed body, 13. substrate front side pads, 14. substrate back pads, 15. salient points, 16. tin balls; 17. scolder, 18. the 4th IC chips, 19. the 4th bonding dies, 20. quadruple linkage zygonemas, 21. the 5th bonding dies; 22. the 5th IC chip, 23. the 5th bonding lines, 24. the 6th bonding lines, 25. the 6th IC chips, 26. the 6th bonding dies.
Embodiment
Below in conjunction with accompanying drawing and embodiment the utility model is elaborated.
Several kinds of packing forms such as the chip-stacked packaging part of the utility model overarm formula IC haves three layers that overarm formula IC is chip-stacked, 4 layers of overarm formula IC is chip-stacked, 5 layers of overarm formula IC is chip-stacked, overarm formula IC is chip-stacked more than 5 layers.
As shown in Figure 1, the structure of 3 layers of chip-stacked encapsulation of IC in the utility model stack package comprises substrate carrier 1, is pasted with substrate 5 on the substrate carrier 1, and substrate 5 adopts the BT substrate; Be pasted with an IC chip 3 on the substrate 5; The one IC chip 3 is bonding with substrate 1 through first bonding die 2; Be pasted with the 2nd IC chip 6 on the one IC chip 3; The 2nd IC chip 6 is bonding through second bonding die 4 and an IC chip 3, is pasted with on the 2nd IC chip 6 that the 3rd IC chip 8, the three IC chips 8 pass through the 3rd bonding die 7 and the 2nd IC chip 6 is bonding; The overall dimension of the overall dimension of the one IC chip 3, the 2nd IC chip 6 is identical with the overall dimension of the 3rd IC chip 8; The one IC chip 3, the 2nd IC chip 6 and the 3rd IC chip 8 along continuous straight runs shift to install, and form step, and the horizontal range a of this step is 0.35mm～2.5mm; Make that a side of piling up the IC chip is a ledge structure, opposite side is a suspension beam structure; Substrate 5 is provided with substrate front side pad 13; The one IC chip 3 is connected with substrate front side pad 13 through triple bond zygonema 11; The 2nd IC chip 6 is connected with an IC chip 3 through second bonding line 10; The 3rd IC chip 8 is connected with the 2nd IC chip 6 through first bonding line 9, and all bonding lines are positioned at a side of the ledge structure of IC chip formation; Substrate carrier 1 back side is provided with substrate back pad 14, and substrate back pad 14 is connected with substrate front side pad 13, and the surface of substrate back pad 14 is provided with salient point (UBM) 15, and salient point 15 is welded with tin ball 16 through scolder 17; Be packaged with plastic-sealed body 12 above the substrate 1; Top, all bonding lines of substrate 1, all IC chips, all bonding die glue and substrate front side pads 13 all are packaged in the plastic-sealed body 12.
It is whole that first bonding die 2 in 3 layers of chip-stacked packaging part of IC, an IC chip 3, the 2nd IC chip 6, second bonding die 4, second bonding line 10, the 3rd bonding die 7, the 3rd IC chip 8, first bonding line 9, triple bond zygonema 11, substrate back pad 14, salient point 15, tin ball 16, scolder 17 and substrate 5 have constituted circuit.12 pairs the one IC chips 3 of plastic-sealed body, substrate front side pad 13, the 2nd IC chip 6, the 3rd IC chip 8, first bonding line 9, second bonding line 10 and triple bond zygonema 11 play protection and supporting role.
Constituted the signalling channel of 3 layers of chip-stacked packaging part circuit of IC and power supply by substrate carrier 1, substrate front side pad 13, an IC chip 3, the 2nd IC chip 6, the 3rd IC chip 8, first bonding line 9, second bonding line 10, triple bond zygonema 11, substrate back pad 14, salient point 15, tin ball 16 and scolder 17.
4 layers of chip-stacked packaging part of IC in the utility model stack package; As shown in Figure 2; The structure of its structure and 3 layers of chip-stacked encapsulation of IC shown in Figure 1 is basic identical; Both differences are: it is bonding through the 4th bonding die 19 and the 3rd IC chip 8 to be pasted with the 4th IC chip 18, the four IC chips 18 on the 3rd IC chip 8, and the 4th IC chip 18 is connected with the 3rd IC chip 8 through quadruple linkage zygonema 20; The 4th IC chip 18 and the 3rd IC chip 8 shift to install, and dislocation direction and dislocation distance all with the dislocation direction of other IC chip with misplace apart from identical; The overall dimension of the 4th IC chip 18 is identical with the overall dimension of other IC chip.
It is whole that first bonding die 2 in 4 layers of chip-stacked packaging part of IC, substrate front side pad 13, an IC chip 3, second bonding die 4, the 2nd IC chip 6, first bonding line 9, second bonding line 10, the 3rd bonding die 7, the 3rd IC chip 8, triple bond zygonema 11, the 4th bonding die 19, the 4th IC chip 18, quadruple linkage zygonema 20, substrate back pad 14, salient point 15, tin ball 16, scolder 17 and substrate 5 have constituted circuit.
12 pairs the one IC chips of plastic-sealed body 3 in 4 layers of chip-stacked packaging part of IC, the 2nd IC chip 6, the 3rd IC chip 8, the 4th IC chip 18, first bonding line 9, substrate front side pad 14, second bonding line 10, triple bond zygonema 11 and quadruple linkage zygonema 20 have played protection and supporting role.
Constituted the signalling channel of 4 layers of chip-stacked packaging part circuit of IC and power supply by substrate carrier 1, substrate front side pad 13, an IC chip 3, the 2nd IC chip 6, the 3rd IC chip 8, the 4th IC chip 18, first bonding line 9, second bonding line 10, triple bond zygonema 11, quadruple linkage zygonema 20 substrate back pads 14, salient point 15, tin ball 16 and scolder 17.
5 layers of chip-stacked packaging part of IC in the utility model stack package; As shown in Figure 3; The structure of its structure and 4 layers of chip-stacked encapsulation of IC shown in Figure 2 is basic identical; Both differences are: it is bonding through the 5th bonding die 21 and the 4th IC chip 18 to be pasted with the 5th IC chip 22, the five IC chips 22 on the 4th IC chip 18, and the 5th IC chip 22 is connected with the 4th IC chip 18 through the 5th bonding line 23; The 5th IC chip 22 and the 4th IC chip 18 shift to install, and dislocation direction and dislocation distance all with the dislocation direction of other IC chip with misplace apart from identical; The overall dimension of the 5th IC chip 22 is identical with the overall dimension of other IC chip.
It is whole that first bonding die 2 in 5 layers of chip-stacked packaging part of IC, an IC chip 3, substrate front side pad 13, second bonding die 4, the 2nd IC chip 6, second bonding line 10, the 3rd bonding die 7, the 3rd IC chip 8, triple bond zygonema 11, the 4th bonding die 19, the 4th IC chip 18, quadruple linkage zygonema 20, the 5th bonding die 21, the 5th IC chip 22, the 5th bonding line 23, first bonding line 9, substrate back pad 14, salient point 15, tin ball 16, scolder 17 and substrate 5 have constituted circuit.
12 pairs the one IC chips of plastic-sealed body 3 in 5 layers of chip-stacked packaging part of IC, the 2nd IC chip 6, the 3rd IC chip 8, the 4th IC chip 18, the 5th IC chip 22, first bonding line 9, second bonding line 10, triple bond zygonema 11, quadruple linkage zygonema 20, the 5th bonding line 23 and substrate front side pad 13 have played protection and supporting role.
Constituted the signalling channel of 5 layers of chip-stacked packaging part circuit of IC and power supply by substrate carrier 1, substrate front side pad 13, an IC chip 3, the 2nd IC chip 6, the 3rd IC chip 8, the 4th IC chip 18, the 5th IC chip 22, first bonding line 9, second bonding line 10, triple bond zygonema 11, quadruple linkage zygonema 20, the 5th bonding line 23, substrate back pad 14, salient point 15, scolder 17 and tin ball 16.
As shown in Figure 4; 6 layers of chip-stacked packaging part of IC in the utility model stack package; The structure of its structure and 5 layers of chip-stacked encapsulation of IC shown in Figure 3 is basic identical; Both differences are: it is mutually bonding with the 5th IC chip 22 through the 6th bonding die 26 to be pasted with the 6th IC chip 25, the six IC chips 25 on the 5th IC chip 22, and the 6th IC chip 25 is connected with the 5th IC chip 22 through the 6th bonding line 24; The 6th IC chip 25 and the 5th IC chip 22 shift to install, and dislocation direction and dislocation distance all with the dislocation direction of other IC chip with misplace apart from identical; The overall dimension of the 6th IC chip 25 is identical with the overall dimension of other IC chip.
First bonding die 2 in 6 layers of chip-stacked packaging part of IC; The one IC chip 3; Substrate front side pad 13; Second bonding die 4; The 2nd IC chip 6; Second bonding line 10; The 3rd bonding die 7; The 3rd IC chip 8; Triple bond zygonema 11; The 4th bonding die 19; The 4th IC chip 18; Quadruple linkage zygonema 20; The 5th bonding die 21; The 5th IC chip 22; The 5th bonding line 23; The 6th bonding die 26; The 6th IC chip 25; The 6th bonding line 24; First bonding line 9; Substrate back pad 14; Salient point 15; Scolder 17; Tin ball 16 has constituted circuit integral body with substrate 5.
12 pairs the one IC chips of plastic-sealed body 3 in 6 layers of chip-stacked packaging part of IC, the 2nd IC chip 6, the 3rd IC chip 8, the 4th IC chip 18, the 5th IC chip 22, the 6th IC chip 25, first bonding line 9, second bonding line 10, triple bond zygonema 11, quadruple linkage zygonema 20, the 5th bonding line 23, the 6th bonding line 25, substrate front side pad 13 etc. have played protection and supporting role.
Constituted the signalling channel of 6 layers of chip-stacked encapsulated circuit of IC and power supply by substrate carrier 1, substrate front side pad 13, an IC chip 3, the 2nd IC chip 6, the 3rd IC chip 8, the 4th IC chip 18, the 5th IC chip 22, the 6th IC chip 25, first bonding line 9, second bonding line 10, triple bond zygonema 11, quadruple linkage zygonema 20, the 5th bonding line 23, the 6th bonding line 25, substrate back pad 14, salient point 15, scolder 17 and tin ball 16.
First bonding die 2 adopts insulating cement.Second bonding die 4, the 3rd bonding die 7, the 4th bonding die 19, the 5th bonding die 21 and the 6th bonding die 26 adopt insulating cement or glue films.During use, second bonding die 4, the 3rd bonding die 7, the 4th bonding die 19, the 5th bonding die 21 and the 6th bonding die 26 adopt insulating cement simultaneously; Perhaps second bonding die 4, the 3rd bonding die 7, the 4th bonding die 19, the 5th bonding die 21 and the 6th bonding die 26 adopt glue film simultaneously.
The technological process of the chip-stacked packaging part of the utility model overarm formula IC is following:
1) the chip-stacked encapsulation of 3 layers of overarm formula IC
Attenuate-scribing-core on core-second time on the first time-go up for the third time core and baking-plasma cleaning-pressure welding-plastic packaging and after solidify-plant ball and Reflow Soldering-cleaning-printing-cutting and separating-test-check-packing-warehouse-in.
2) the chip-stacked encapsulation of 4 layers of overarm formula IC
Attenuate-scribing-core on core-second time on the first time-go up for the third time core-the 4th go up core and baking-plasma cleaning-pressure welding-plastic packaging and after solidify-plant ball and Reflow Soldering-cleaning-printing-cutting and separating-test-check-packing-warehouse-in.
3) the chip-stacked encapsulation of 5 layers of overarm formula IC
Attenuate-scribing-core on core-second time on the first time-go up for the third time core-four go up core-the 5th go up core and baking-plasma cleaning-pressure welding-plastic packaging and after solidify-plant ball and Reflow Soldering-cleaning-printing-cutting and separating-test-check-packing-warehouse-in.
4) the chip-stacked encapsulation of 6 layers of overarm formula IC
Attenuate-scribing-core on core-second time on the first time-go up for the third time core-the 4th go up core-the 5th go up core-the 6th go up core and baking-plasma cleaning-pressure welding-plastic packaging and after solidify-plant ball and Reflow Soldering-cleaning-printing-cutting and separating-test-check-packing-warehouse-in.
During the chip-stacked encapsulation of overarm formula IC, every increase one deck IC chip just increases once goes up the core operation, and toasts after going up core the last time more than six layers, and all the other operations are undertaken by the 6 layers of chip-stacked encapsulation flow process of formula IC of hanging oneself from a beam.
The production method of the chip-stacked packaging part of the utility model overarm formula IC:
Step 1: wafer attenuate
Employing possesses 8 inch of correct grinding, polishing function and above ultra-thin chip attenuate machine carries out the wafer attenuate, and obtaining final thickness is the wafer that is used for 3 layers of stacked package of 90～110 μ m and the wafer that is used for 4 layers, 5 layers stacked package that final thickness is 50～75 μ m; Employing has the attenuate machine attenuate wafer of etch polishing function, and the final thickness that obtains the back side and be the mirror finish effect is the wafer that is used for encapsulation more than 5 layers of 35～50 μ m; In the wafer thinning process, the corase grind scope of wafer from original wafer thickness+film thickness to the wafer final thickness+65 μ m+ film thickness, corase grind speed: 3 layers of stacked package are 50～120 μ m/min, stacked package is 40～100 μ m/min more than 3 layers; To wafer final thickness+film thickness+5 μ m, fine grinding speed is 11～14 μ m/min to the fine grinding scope from wafer final thickness+65 μ m+ film thickness; To wafer final thickness+film thickness, polishing velocity is 0.025～0.035 μ m/s to the polishing scope from wafer final thickness+film thickness+5 μ m.
The wafer thinning technique is most important aspect the laminated type chip encapsulation technology, mounts height because it has reduced encapsulation, chip stack and do not increase the total height of laminated type chip system.Because this packaging part is the chip-stacked encapsulation of multilayer overarm formula, chip thickness requires to belong to the ultra-thin chip attenuate at 35 μ m～110 μ m, and wafer size be 8 inches and more than, be main with 12 inches.Therefore, the challenge of reduction process is very strong, and technology difficulty is bigger, 12 inches wafers particularly, and 75 μ m are thin as a piece of paper, and are higher to equipment and technological requirement.General selection possesses 8 inch of correct grinding, polishing function and above ultra-thin chip attenuate machine such as PRG300R thereof, full-automatic pad pasting film stripping machine such as DR3000 III etc., and fine grinding, polishing thickness have increased by 15 μ m than usual, and purpose is in order to reduce the grinding affected layer;
Step 2: scribing
Wafer to step 1 attenuate carries out scribing, obtains the IC chip; Adopt anti-fragment software control feed velocity≤5～8mm/min in the scribing processes;
Ultrathin wafer scribing mainly is to want to prevent crackle and fragment, adopts A-WD-300TXB or DAD3350 scribing machine.
Step 3: go up core
On substrate 5, paste an IC chip through insulating cement; The number of plies of piling up as required then; On this IC chip, adopt insulating cement or glue film to stack gradually and paste corresponding number of I C chip, the overall dimension of all IC chips is identical, and all IC chips that on first IC chip, pile up all shift to install to same direction; Dislocation distance between adjacent two IC chips is identical, and this dislocation distance is 0.35～2.5mm; All went up behind the cores baking 3 hours, its roasting plant and technology are toasted after going up core with common BGA, but technology is according to the bonding die material with pile up number of plies adjustment, and when promptly adopting insulating cement as adhesive material, baking temperature is 175 ℃; When adopting glue film as adhesive material, roasting temperature is 150 ℃;
Owing to be stacked package, adopt insulating cement and two kinds of materials of glue film, therefore need the die Bonder of bonding die glue and two kinds of materials of glue film.The characteristics of core are that multilayer chiop is gone up core respectively in the chip-stacked encapsulation of overarm formula, once baking, and lower floor's chip surface is reserved 0.35mm～2.5mm (being a size), the unsettled 0.35mm～2.5mm of upper strata chip right-hand member (being a size).General ground floor uses the insulating cement bonding die; The second layer and above use insulating cement or glue film bonding die; When adopting insulating part to paste, the amount of used insulating cement guarantees that the position bondline thickness that contacts between the two-layer IC chip of covering is even between the adjacent two layers IC chip, and outwards not overflowing (both influences bonding wire in case overflow; Cause chip back and substrate contamination again, cause plastic packaging material and bonding die gluing to close the bad absciss layer that is easy to generate).Used roasting plant and technology are toasted after going up core with common BGA during baking, but technology according to the bonding die material with pile up number of plies adjustment.
Step 4: plasma cleans
Adopting BT substrate single-chip package cleaning equipment and technology to carry out plasma cleans;
Step 5: pressure welding
With the low radian bonding machine that possesses below the 100 μ m; With spun gold or copper wire, begin routing from top IC chip, press the IC of the superiors chip bonding pad to bonding wire between time upper strata IC chip bonding pad earlier; Then folding routing on lower floor's chip bonding pad of ball collar silk arcing at this chip by chip on the solder joint of inferior upper strata IC chip; And the like, the bonding wire at last from the folded ball collar silk arcing of orlop IC chip bonding wire to substrate pads, bonding wire adopts BGA arc (height arc) basically; Form the multilayer bonding line, the camber of the superiors' bonding line is 80 μ m～100 μ m, and the camber of all the other every layer bonding line is 70 μ m～90 μ m, avoids between line and the line intersection short circuit or solder joint to come off;
Perhaps; Low radian bonding machine with possessing below the 100 μ m with spun gold or copper wire, begins routing from orlop IC chip; Press earlier the bonding wire of lowermost layer IC chip bonding pad on the BT substrate pads; Then folded ball on orlop IC chip welding spot, the arcing of arch silk with the second layer IC chip bonding pad of orlop IC chip by chip on play a ball, fold above that then on the 3rd layer of IC chip bonding pad that is pressed under the arcing of ball collar silk with second layer IC chip by chip and play a ball; And the like, last solder joint drops on the IC of the superiors bonding pads; Bonding wire adopts BGA arc (height arc) basically; Form the multilayer bonding line, the camber of the superiors' bonding line is 80 μ m～100 μ m, and the camber of all the other every layer bonding line is 70 μ m～90 μ m, avoids between line and the line intersection short circuit or solder joint to come off;
Step 6: solidify plastic packaging and back
Use full-automatic encapsulation system; Adopt the ep-type material of low stress (coefficient of expansion a1＜1), low water absorption (water absorption rate＜0.25%); (the software registration number: 0276826) control, adjustment optimize that technology is carried out plastic packaging and solidify the back to use the multistage injection model software of applicant's exploitation of the application; Plastic package process parameter: 165 ℃～185 ℃ of mould temperature, clamping pressure 85kgf/cm
2～125kgf/cm
2, injection pressure 38kgf/cm
2～46kgf/cm
2, plastic packaging need satisfy the requirement of the rate of breasting the tape＜5%, no absciss layer, angularity＜0.1, the common BT substrate of back curing apparatus and technology single-chip package;
Step 7: plant ball and Reflow Soldering
Ball is planted at the back side at substrate carrier 1, plants the ball flow process to be: the reflow soldering furnace temperature detects-plants ball-plant ball and inspection-Reflow Soldering-water cleaning-tin ball thrust detection-ion and depth test-commentaries on classics preface.Specifically: the M705 tin ball that adopts Au800 ball attachment machine, WF-6400 scaling powder and diameter of phi 35mm; Elder generation's print fluxing on substrate back pad 14; On substrate back pad 14, form scolder 17, M705 tin ball aligning is placed on the scolder 17, become tin ball 16; After having planted tin ball 16 on the whole piece substrate back pad 14, earlier automatic detection record is delivered to the rewinding folder then; Adopt above-mentioned same quadrat method, planted the whole tin balls 16 of this batch after, deliver to the feeder of Reflow Soldering; The semi-finished product substrate that this feeder will have been planted ball successively is positioned over the transmission band of Reflow Soldering, sends into the PrRMAX100N reflow soldering, mixes up temperature (8 warm areas in advance by the temperature curve of setting; 120 ℃～255 ℃, per 20 ℃ of warm areas, 4,5 districts are 180 ℃); (Reflow Soldering furnace superintendent 4.5～4.6m, line speed 0.71～0.84 m/min) carried out the time in setting, continues to feed nitrogen (the nitrogen pressure 0.14Mpa～0.16 Mpa of certain flow and pressure; Nitrogen flow: 260～280L/min), carry out Reflow Soldering, utilize tin ball 16 effect that automatically resets at high temperature; Tin ball 16, scolder 17 and substrate back pad 14 are closely linked, satisfy the shearing force requirement of tin ball; Continue to feed the anti-oxidation of nitrogen protection, guarantee good reliability.
Planting ball and Reflow Soldering is principal character and the master operation thereof that substrate package is different from framework (LF) encapsulation.The quality of its quality has not only determined the final finished rate of product, and the reliability of reliability of products and final assembly is played main effect.Thereby when planting ball, need carry out: Incoming Quality Control and control, plant the ball chuck tool and clean inspection, the fixing and detection of reflow soldering temperature curve, tin ball thrust detects, and water cleaning temperature, resistivity detect ionic pollution degree detection etc.
It is following to plant the ball technological parameter:
Pick up the scaling powder action
Z axle decrease speed: 145～155mm/s;
After descending, the Z axle keeps in touch the time: 70～90ms with scaling powder;
Scaling powder is placed action
After descending, the Z axle keeps in touch the time: 145～155ms with substrate;
0.35～0.45mm leaves;
Z axle and substrate disengaging time: 380～420ms
Plant ball
Z axle decrease speed: 145～155mm/s
Pick up the ball action
Z axle fall time: 90～110ms; The Z axle is picked up ball time: 280～320ms after descending;
Vacuum is opened delay time: 45～55 ms; The vacuum duration: 380～420ms;
The vacuum breaking delayed start-up time: 90～110ms; The vacuum breaking duration: 180～220ms;
Time-delay: 90～110ms is opened in the shop spheroidal vibration; Shop spheroidal vibration duration 280～320ms;
The tin ball is placed action
Z axle fall time: 90～110ms; Z axle and substrate contacts time: 480～520ms;
The Z axle is placed the tin spheroidal vibration and is opened delay time: 90～110ms 0;
The Z axle is placed tin spheroidal vibration duration: 90～110ms
The vacuum breaking delayed start-up time: 90～110ms; The vacuum breaking duration: 80～120ms;
Z axle and substrate separating distance (mm): 0.0; Axle separates the used time (ms) with substrate: 0;
Vibration delayed start-up time: 145～155ms; Vibration time-delay duration: 80～120ms;
Plant and use the BL-370 water washer to clean after ball is accomplished, during cleaning: line speed is 0.45 ± 0.05m/min, and the three-flute rinse liquid temperature is 45 ± 5 ℃, and cleaning hydraulic pressure is 3.1kg～3.5kg, and air-dry temperature is 60 ℃;
Step 8: print
Adopt the special-purpose printing anchor clamps of substrate, the tin ball is not abraded, the equipment of its use and technology are printed with common substrate single-chip package product;
Step 9: cutting and separating
Adopt dedicated substrate cutting clamper and DAD3350 diced system, control cutting groove width, groove depth, feed size prevent sliver;
Step 10: test, detection, packing, warehouse-in
With common BGA test, check, packing, warehouse-in, make the chip-stacked packaging part of overarm formula IC of BT substrate.
This packaging part is the encapsulation of chip multiple-level stack, is on the BT substrate, to realize the chip-stacked encapsulation of multilayer overarm formula IC.Be characterized in the big or small identical of all IC chips, and the upper strata chip moves right, make lower floor's chip surface reserve the distance of 0.35～2.5mm, make the unsettled 0.35～2.5mm of upper strata chip right-hand member, the IC chip that piles up is overarm formula structure.
Do not influence lower floor's routing and prevent that glue from overflowing through glue amount control art control point glue amount, and adopt and repeatedly go up core, once toast and a bonding wire.The upper strata chip adopts insulating cement and glue film dual mode bonding die; The routing mode is that lower floor's chip bonding wire is stacked on above the solder joint of upper strata or the upper strata solder joint is stacked on lower floor's solder joint; Have only the ground floor bonding pads directly with substrate on bonding wire link to each other, employing overarm formula wire bond is technological.Plastic packaging adopts anti-warped pattern software of QFN and multistage injection model software control plastic package process process; The plastic package process parameter is optimized in adjustment; The chip-stacked no warpage of realization multilayer overarm formula IC does not have the silk of friendship short circuit encapsulation, has solved the stacked package and the monolateral bonding wire problem of size identical chips.
Claims (2)
1. the chip-stacked packaging part of overarm formula IC of a BT substrate comprises substrate carrier (1), is pasted with substrate (5) on the substrate carrier (1); Pile up on the substrate (5) and be pasted with the IC chip, at least three layers of IC chip, substrate carrier (1) back side is provided with substrate back pad (14); Substrate back pad (14) the substrate front side pad (13) positive with being positioned at substrate carrier (1) is connected; Substrate back pad (14) surface is provided with salient point (15), scolder (17) and tin ball (16) successively, it is characterized in that, described substrate (5) is the BT substrate; Described IC chip is at least three layers; Adjacent two-layer IC chip along continuous straight runs shifts to install, and the dislocation distance is identical, and the overall dimension of all IC chips is identical; Adjacent two layers IC chip is connected through bonding line, and one deck IC chip that is pasted on the substrate (5) is connected with substrate front side pad (13) through triple bond zygonema (11).
2. the chip-stacked packaging part of overarm formula IC as claimed in claim 1 is characterized in that, the dislocation distance between the described adjacent two layers IC chip is 0.35mm～2.5mm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012201418088U CN202549832U (en) | 2012-04-06 | 2012-04-06 | Cantilever-type stacked integrated circuit (IC) chip packaging piece based on barium titanate (BT) substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012201418088U CN202549832U (en) | 2012-04-06 | 2012-04-06 | Cantilever-type stacked integrated circuit (IC) chip packaging piece based on barium titanate (BT) substrate |
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| CN202549832U true CN202549832U (en) | 2012-11-21 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017166325A1 (en) * | 2016-04-02 | 2017-10-05 | Intel Corporation | Semiconductor package with supported stacked die |
| CN108063095A (en) * | 2017-12-15 | 2018-05-22 | 路军 | A kind of method for packing of Intelligent Fusion sensor chip |
| CN109002806A (en) * | 2018-07-27 | 2018-12-14 | 星科金朋半导体（江阴）有限公司 | A kind of rear road packaging method of QFN product |
-
2012
- 2012-04-06 CN CN2012201418088U patent/CN202549832U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017166325A1 (en) * | 2016-04-02 | 2017-10-05 | Intel Corporation | Semiconductor package with supported stacked die |
| US10796975B2 (en) | 2016-04-02 | 2020-10-06 | Intel Corporation | Semiconductor package with supported stacked die |
| CN108063095A (en) * | 2017-12-15 | 2018-05-22 | 路军 | A kind of method for packing of Intelligent Fusion sensor chip |
| CN109002806A (en) * | 2018-07-27 | 2018-12-14 | 星科金朋半导体（江阴）有限公司 | A kind of rear road packaging method of QFN product |
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