CN101192599A - Stack type chip package structure with wire frame inner pin installed with transfer welding pad - Google Patents
Stack type chip package structure with wire frame inner pin installed with transfer welding pad Download PDFInfo
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- CN101192599A CN101192599A CNA2006101450896A CN200610145089A CN101192599A CN 101192599 A CN101192599 A CN 101192599A CN A2006101450896 A CNA2006101450896 A CN A2006101450896A CN 200610145089 A CN200610145089 A CN 200610145089A CN 101192599 A CN101192599 A CN 101192599A
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- 238000012546 transfer Methods 0.000 title description 4
- 238000003466 welding Methods 0.000 title description 2
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- 238000013508 migration Methods 0.000 claims description 138
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- 239000010410 layer Substances 0.000 claims description 54
- 238000005516 engineering process Methods 0.000 claims description 37
- 238000000034 method Methods 0.000 claims description 35
- 238000005476 soldering Methods 0.000 claims description 23
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- 238000000576 coating method Methods 0.000 claims description 22
- 230000008569 process Effects 0.000 claims description 22
- 239000011241 protective layer Substances 0.000 claims description 20
- 238000004806 packaging method and process Methods 0.000 claims description 17
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- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 239000000565 sealant Substances 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 5
- 238000010276 construction Methods 0.000 claims 1
- 238000009713 electroplating Methods 0.000 claims 1
- 239000004020 conductor Substances 0.000 description 131
- 239000000758 substrate Substances 0.000 description 19
- 238000013461 design Methods 0.000 description 18
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
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- Wire Bonding (AREA)
Abstract
The invention provides an encapsulation structure of a stackable chip with a chovr wielding pad for an inner draw foot of a wire frame, which includes: a wire frame comprising of a plurality of inner draw feet groups arranged face to face, a plurality of outer draw feet groups and a chip abuttal, wherein, the chip abuttal is positioned among the plurality of inner draw feet groups arranged face to face and a height difference is formed among the plurality of inner draw feet groups arranged face to face; a stackable structure with the migrating multi-chip which is formed by the stack of a plurality of chips and is arranged on the chip abuttal and is electrically connected with the plurality of inner draw feet groups arranged face to face; and an encapsulation body which coats the stackable structure with the migrating multi-chip and the wire frame and juts the plurality of outer draw feet groups out of the encapsulation body. The invention is characterized in that the inner draw feet in the wire frame are covered by an insulating layer and a plurality of metal wielding pads are selectively formed on the insulating layer.
Description
Technical field
The present invention relates to a kind of multi-chip migration stack package structure, the interior pin that particularly relates to a kind of lead frame is provided with the multi-chip migration stack package structure of switch-over soldering pad.
Background technology
In recent years, semi-conductive last part technology is all carrying out three dimensions (Three Dimension; Encapsulation 3D) reaches big relatively semiconductor integrated level (Integrated) or capacity of internal memory etc. in the hope of utilizing minimum area.In order to reach this purpose, the mode that present stage has been developed use chip stack (chip stacked) is reached three dimensions (Three Dimension; Encapsulation 3D).
In known technology, the storehouse mode of chip is stacked over a plurality of chips on the substrate mutually, uses the technology (wire bonding process) of routing that a plurality of chips are connected with substrate then.Figure 1A is known generalized section with storehouse cake core encapsulating structure of identical or close chip size.Shown in Figure 1A, known storehouse cake core encapsulating structure 100 comprises circuit substrate (packagesubstrate) 110, chip 120a, chip 120b, sept (spacer) 130, many leads 140 and sealant (encapsulant) 150.Have a plurality of weld pads 112 on the circuit substrate 110, and also have a plurality of weld pad 122a and 122b respectively on chip 120a and the 120b, wherein weld pad 122a and 122b are arranged on chip 120a and the 120b with kenel (peripheral type) on every side.Chip 120a system is arranged on the circuit substrate 110, and chip 120b is arranged at the top of chip 120a by sept 130.The two ends of lead 140 are connected to weld pad 112 and 122a by routing technology, so that chip 120a is electrically connected on circuit substrate 110.And the two ends of other parts lead 140 also are connected to weld pad 112 and 122b by routing technology, so that chip 120b is electrically connected on circuit substrate 110.Be arranged on the circuit substrate 110 as for 150 of sealants, and coat these leads 140, chip 120a and 120b.
Because weld pad 122a and 122b are arranged on chip 120a and the 120b with kenel on every side, therefore the direct carries chips 120b of chip 120a, be sept 130 to be set between chip 120a and 120b with known technology, make between chip 120a and the 120b at a distance of suitable distance, in order to the carrying out of follow-up routing technology.Yet the use of sept 130 but causes the thickness of known storehouse cake core encapsulating structure 100 to reduce further easily.
In addition, known technology proposes another kind of storehouse cake core encapsulating structure with different chip sizes, and its generalized section is shown in Figure 1B.Please refer to Figure 1B, known storehouse cake core encapsulating structure 10 comprises circuit substrate (package substrate) 110, chip 120c, chip 120d, many leads 140 and sealant 150.Have a plurality of weld pads 112 on the circuit substrate 110.The size of chip 120c is greater than the size of chip 120d, and also has a plurality of weld pad 122c and 122d on chip 120c and the 120d respectively, and wherein weld pad 122c and 122d are arranged on chip 120c and the 120d with kenel (peripheral type) on every side.Chip 120c is arranged on the circuit substrate 110, and chip 120d is arranged at the top of chip 120c.The two ends of part lead 140 are connected to weld pad 112 and 122c by routing technology (wire bondingprocess), so that chip 120c is electrically connected on circuit substrate 110.And the two ends of other parts lead 140 also are connected to weld pad 112 and 122d by routing technology, so that chip 120d is electrically connected on circuit substrate 110.Be arranged on the circuit substrate 110 as for 150 of sealants, and coat these leads 140, chip 120c and 120d.
Because chip 120d is less than chip 120c, therefore when chip 120d was arranged on the chip 120c, chip 120d can not cover the weld pad 122c of chip 120c.But when known technology goes out storehouse cake core encapsulating structure 10 with the chip of a plurality of different size sizes with above-mentioned mode storehouse,, be the restriction that the storehouse quantity of chip is arranged with storehouse cake core encapsulating structure 10 because the chip size on upper strata must be more little more.
In above-mentioned two kinds of traditional storehouse modes, except there being Figure 1A to use the mode of sept 130, shortcoming and Figure 1B of causing the thickness of storehouse cake core encapsulating structure 100 to reduce further easily, because the chip size on upper strata must be more little more, so can produce outside the problem that chip can be restricted in design or when using; Make owing to the chip design on the storehouse cake core encapsulating structure is complicated day by day that also the circuit on the chip connects necessary wire jumper or cross-line, and then the problem that on technology, produces, for example: when injecting the mould stream of high pressure because carrying out moulding (molding), may cause the plain conductor of these mutual wire jumpers or cross-line to produce displacement and cause short circuit, make the production capacity of storehouse cake core encapsulating structure or reliability may reduce.
Summary of the invention
Because the shortcoming and the problem of the chip stack mode described in the background of invention the invention provides a kind of mode of using the multi-chip migration storehouse, the akin chip stack of a plurality of sizes is become a kind of three-dimensional encapsulating structure.
Main purpose of the present invention is to provide the structure that a plurality of metal pads are set on a kind of interior pin in lead frame again to carry out the structure of multi-chip migration storehouse encapsulation, makes it have preferable circuit design elasticity and better reliability degree by having increased the structure that a plurality of metal pads are set on the interior pin.
Another main purpose of the present invention is to provide a kind of structure that the frame that confluxes is set in lead frame to carry out the structure of multi-chip migration storehouse encapsulation, makes it have preferable circuit design elasticity and better reliability degree by the conflux structure of frame of increase.
In view of the above, the invention provides the stack type chip package structure that has switch-over soldering pad on a kind of interior pin of lead frame, comprise: the lead frame that the interior pin group by a plurality of relative arrangements, a plurality of outer pin group and chip bearing are formed, its chips bearing is arranged between the interior pin group of a plurality of relative arrangements, and forms difference in height with the interior pin group of a plurality of relative arrangements; The multi-chip migration stack architecture is formed by a plurality of chip stacks, and the multi-chip migration stack architecture is arranged on the chip bearing and with the interior pin group of a plurality of relative arrangements and forms electrical connection; And packaging body, coat multi-chip migration stack architecture and lead frame and also a plurality of outer pin groups are stretched out in outside this packaging body; It is characterized in that the interior pin in the lead frame is also optionally formed a plurality of metal pads again on insulating layer coating and the insulating barrier.
The present invention then provides the conducting wire frame structure that has switch-over soldering pad on a kind of interior pin, formed by a plurality of interior pin group of relative arrangement, a plurality of outer pin group and chip bearings of being, the chip bearing is arranged between the interior pin group of a plurality of relative arrangements and with the interior pin group of these a plurality of relative arrangements and forms difference in height, and the pin part is optionally formed a plurality of metal pads on insulating layer coating and this insulating barrier in it is characterized in that.
The present invention then provides a kind of conducting wire frame structure again, constituted by pin in a plurality of and a plurality of outer pin, interior pin includes a plurality of first parallel interior pin groups and the second parallel interior pin group, the pin group and the second interior pin group's end is with relative arrangement at interval in first, the pin group has heavy interposed structure and the terminal position that forms pin group in first has different vertical heights with the second interior pin group's terminal position in first, it is characterized in that pin group or the second interior pin group or this first interior pin group and the second interior pin group's etc. terminal vicinity in first, the part is optionally formed a plurality of metal pads on insulating layer coating and this insulating barrier.
Description of drawings
Figure 1A, 1B are the schematic diagram of prior art;
Fig. 2 A is the vertical view of chip structure of the present invention;
Fig. 2 B is the cutaway view of chip structure of the present invention;
Fig. 2 C～E is the cutaway view of multi-chip migration stack architecture of the present invention;
Fig. 3 A～C is the schematic diagram of putting layer manufacture process of reseting of the present invention;
Fig. 4 A～B is a cutaway view of reseting the wire bonds district of putting in the floor of the present invention;
Fig. 5 A～C is the cutaway view of reseting the multi-chip migration stack architecture of putting layer that has of the present invention;
Fig. 6 is the vertical view of multi-chip migration stack architecture encapsulation of the present invention;
Fig. 7 A～7B is the vertical view of another embodiment of multi-chip migration stack architecture encapsulation of the present invention;
Fig. 8 A～8B is the vertical view of another embodiment of multi-chip migration stack architecture encapsulation of the present invention;
Fig. 9 A～9B is the vertical view of an embodiment again of multi-chip migration stack architecture encapsulation of the present invention;
Figure 10 is the cutaway view of the multi-chip migration stack architecture encapsulation of Fig. 6 of the present invention;
Figure 11 is the cutaway view of an embodiment of multi-chip migration stack architecture encapsulation of the present invention;
Figure 12 is the cutaway view of another embodiment of multi-chip migration stack architecture encapsulation of the present invention;
Figure 13 is the cutaway view of another embodiment of multi-chip migration stack architecture of the present invention;
Figure 14 is the cutaway view of another embodiment of multi-chip migration stack architecture of the present invention;
Figure 15 is the cutaway view of another embodiment of multi-chip migration stack architecture of the present invention;
Figure 16 is the cutaway view of another embodiment of multi-chip migration stack architecture of the present invention;
Figure 17 is the cutaway view of another embodiment of multi-chip migration stack architecture of the present invention;
Figure 18 is the cutaway view of another embodiment of multi-chip migration stack architecture of the present invention;
Figure 19 is the cutaway view of another embodiment of multi-chip migration stack architecture of the present invention;
Figure 20 is the cutaway view of another embodiment of multi-chip migration stack architecture of the present invention;
Figure 21 is the cutaway view of another embodiment of multi-chip migration stack architecture of the present invention;
Figure 22 is the cutaway view of another embodiment of multi-chip migration stack architecture of the present invention;
Figure 23 is the cutaway view of another embodiment of multi-chip migration stack architecture of the present invention;
Figure 24 is the vertical view of lead frame embodiment of the present invention;
Figure 25 is the lead frame cutaway view of Figure 24 of the present invention;
Figure 26 is the cutaway view of another embodiment of multi-chip migration stack architecture of the present invention;
Figure 27 is the cutaway view of another embodiment of multi-chip migration stack architecture of the present invention;
Figure 28 is the cutaway view of another embodiment of multi-chip migration stack architecture of the present invention.
The main element description of symbols
10,100,400: storehouse cake core encapsulating structure
110,410: circuit substrate
112,122a, 122b, 122c, 122d: weld pad
120a, 120b, 120c, 120d: chip
130: sept
140,242,420,420a, 420b: lead
150,430: sealant
200: chip
210: the chip active surface
220: chip back
230: adhesion layer
240: weld pad
250: the wire bonds district
260: the wire welding area edge
30: the multi-chip migration stack architecture
310: the chip body
312a: first weld pad
312b: second weld pad
320: the wire bonds district
330: the first protective layers
332: the first openings
340: reset and put line layer
344: the three weld pads
350: the second protective layers
352: the second openings
300: chip structure
400: reset and put layer
50: the multi-chip migration stack architecture
500 (a, b, c, d): chip structure
600: lead frame
610: interior pin group
6101～6104: interior pin
611: insulating barrier
6121～6124: interior pin
613: metal pad
Pin group in 615: the first
Pin group in 616: the second
617: connecting portion
618: platform part
620: the chip bearing
630: frame confluxes
6301～63010: frame confluxes
632: insulating barrier
634: metal pad
6341～6343: metal pad
640 (a～n): plain conductor
70: the multi-chip migration stack architecture
A～f: weld pad
A '～f ': weld pad
Embodiment
The present invention is a kind of mode of using chip offset amount storehouse in this direction of inquiring into, and the akin chip stack of a plurality of sizes is become a kind of three-dimensional encapsulating structure.In order to understand the present invention up hill and dale, detailed step and composition thereof will be proposed in following description.Apparently, execution of the present invention does not limit the specific details that the person of ordinary skill in the field understood of the mode of chip stack.On the other hand, the detailed step of last part technologies such as well-known chip generation type and chip thinning is not described in the details, with the restriction of avoiding causing the present invention unnecessary.Yet, for preferred embodiment of the present invention, can be described in detail as follows, yet except these were described in detail, the present invention can also implement in other embodiments widely, and scope of the present invention not limited, it is as the criterion with claim.
In the semiconductor packaging process in modern times, all be a wafer (wafer) of having finished FEOL (FrontEnd Process) to be carried out thinning earlier handle (Thinning Process), the thickness of chip is ground between 2～20mil; Then, coating (coating) or wire mark (printing) one deck macromolecule (polymer) material are in the back side of chip again, and this macromolecular material can be a kind of resin (resine), particularly a kind of B-Stage resin.By a baking or irradiation technology, make macromolecular material present a kind of semi-curing glue again with stickiness; Follow again, an adhesive tape that can remove (tape) is attached on the macromolecular material of semi-solid preparation shape; Then, carry out the cutting (sawing process) of wafer, make wafer become many chip (die); At last, just many chip can be connected with substrate and chip is formed the stack chip structure.
With reference to Fig. 2 A and Fig. 2 B, finish the floor map and the generalized section of the chip 200 of aforementioned technology.Shown in Fig. 2 A, chip 200 has the back side 220 of active surface 210 and relative active surface, and has formed adhesion layer 230 on the chip back 220; To emphasize at this, adhesion layer 230 of the present invention is not defined as aforesaid semi-curing glue, the purpose of this adhesion layer 230 is to form with lead frame or chip to engage, therefore, so long as have the adhesion material of this function, be embodiments of the present invention, for example: glued membrane (die attached film).In addition, in an embodiment of the present invention, the active surface 210 of chip 200 is provided with a plurality of weld pads 240, and a plurality of weld pad 240 has been arranged on the side of chip 200, therefore, can form a kind of multi-chip migration stack architecture 30, shown in Fig. 2 C.And the structure 30 of multi-chip migration storehouse is that alignment line forms with the edge line 260 in wire bonds district 250, therefore can form similar stair-stepping multi-chip migration stack architecture 30, be noted that at this that edge line 260 is actually and do not exist on the chip 200 that it is only as a line of reference.
In addition, in an embodiment of the present invention, form the uppermost chip of the structure 30 of multi-chip migration storehouse, a plurality of weld pads 240 on it also can further be arranged on another side of chip, shown in Fig. 2 D,, more tie point can be arranged so that when engaging with substrate.Simultaneously, forming the uppermost chip of multi-chip migration stack architecture 30, also can be the chip of another size, and chip that size is less for example is shown in Fig. 2 E.Be stressed that once more, weld pad 240 for the chip of the structure of above-mentioned formation multi-chip migration storehouse is provided with or the sizes of chip, the present invention is not limited, as long as the structure of formed multi-chip migration storehouse that can be according to the previous description is embodiments of the present invention.
The present invention uses a kind of reseting to put layer (Redistribution Layer in another embodiment of multi-chip migration storehouse; RDL) weld pad on the chip is set on the side of chip, so that can form the structure of multi-chip migration storehouse, and this resets the execution mode of putting line layer and is described as follows.
Please refer to Fig. 3 A～3C, have a manufacture process schematic diagram of reseting the chip structure of putting line layer for of the present invention.As shown in Figure 3A, chip body 310 at first is provided, and cook up wire bonds district 320 at the single side that is adjacent to chip body 310, and a plurality of weld pads 312 on the active surface of chip body 310 are divided into the first weld pad 312a and the second weld pad 312b, wherein the first weld pad 312a is positioned at wire bonds district 320, the second weld pad 312b and then is positioned at outside the wire bonds district 320.Then please refer to Fig. 3 B, form first protective layer 330 on chip body 310, wherein first protective layer 330 has a plurality of first openings 332, to expose the first weld pad 312a and the second weld pad 312b.On first protective layer 330, form to reset then and put line layer 340.Put line layer 340 and comprise many leads 342 and a plurality of the 3rd weld pads 344 and reset, wherein the 3rd weld pad 344 is to be positioned at wire bonds district 320, and these leads 342 extend to the 3rd weld pad 344 from the second weld pad 312b respectively, so that the second weld pad 312b is electrically connected on the 3rd weld pad 344.In addition, reset the material of putting line layer 340, can be gold, copper, nickel, titanizing tungsten, titanium or other electric conducting material.Please refer to Fig. 3 C again; formation reset put line layer 340 after, second protective layer 350 is covered in to reset puts on the line layer 340, and form the structure of chip 300; wherein second protective layer 350 has a plurality of second openings 352, to expose the first weld pad 312a and the 3rd weld pad 344.
Be stressed that, though the first above-mentioned weld pad 312a and the second weld pad 312b are arranged on the active surface of chip body 310 with kenel on every side, yet the first weld pad 312a and the second weld pad 312b can also be arranged on the chip body 310 by face array kenel (area array type) or other kenel, and certain second weld pad 312b is electrically connected on the 3rd weld pad 344 by lead 342.In addition, present embodiment does not also limit the arrangement mode of the 3rd weld pad 344, though the 3rd weld pad 344 and the first weld pad 312a are arranged in two row in Fig. 3 B, and the single side along chip body 310 is arranged, but the 3rd weld pad 344 and the first weld pad 312a can also be single-row, multiple row or other mode is arranged in the wire bonds district 320.
Please continue with reference to Fig. 4 A and Fig. 4 B, among Fig. 3 C respectively along hatching A-A ' and the represented generalized section of B-B '.By above-mentioned Fig. 3 as can be known chip 300 mainly comprise chip body 310 and reset and put 400 on layer and form, wherein reset put layer 400 by first protective layer 330, reset and put line layer 340 and second protective layer 350 is formed.Chip body 310 has wire bonds district 320, and wire bonds district 320 is adjacent to the single side of chip body 310.In addition, chip body 310 has a plurality of first weld pad 312a and the second weld pad 312b, and wherein the first weld pad 312a is positioned at wire bonds district 320, and the second weld pad 312b is positioned at outside the wire bonds district 320.
First protective layer 330 is arranged on the chip body 310, and wherein first protective layer 330 has a plurality of first openings 332, to expose these the first weld pad 312a and the second weld pad 312b.Reset and put line layer 340 and be arranged on first protective layer 330, wherein reset and put line layer 340 and extend in the wire bonds district 320 from the second weld pad 312b, and reset and put line layer 340 and have a plurality of the 3rd weld pads 344, it is arranged in the wire bonds district 320.Second protective layer 350 is covered in to reset and puts on the line layer 340, and wherein second protective layer 350 has a plurality of second openings 352, to expose these first weld pad 312a and the 3rd weld pad 344.Because the first weld pad 312a and the 3rd weld pad 344 all are positioned at wire bonds district 320; therefore the zone beyond the wire bonds district 320 on second protective layer 350 just can provide the platform of a carrying; to carry another chip structure; therefore, can form a kind of structure 30 of multi-chip migration storehouse.
Please refer to Fig. 5 A, be the structure 50 of a kind of multi-chip migration storehouse of the present invention.Multi-chip migration stack architecture 50 is formed by a plurality of chip 500 storehouses, have on its chips 500 to reset and put layer 400, so the weld pad 312b on the chip can be arranged on the wire bonds district 320 of chip, therefore this multi-chip migration stack architecture 50 is that alignment line forms with the edge in wire bonds district 320.And connect with the formed adhesion layer 230 of a macromolecular material between a plurality of chips 500.In addition, in an embodiment of the present invention, form the uppermost chip of multi-chip migration stack architecture 50, can select to keep the contact of weld pad 312b, shown in Fig. 5 B, so that when engaging with substrate, more tie point can be arranged, and the mode that forms this chip structure is shown in Fig. 4 B.Simultaneously, forming the uppermost chip of multi-chip migration stack architecture 50, also can be the chip of another size, and chip that size is less for example is shown in Fig. 5 C.Be stressed that once more, for the weld pad setting of the chip of above-mentioned formation multi-chip migration stack architecture or the size of chip, the present invention is not limited, as long as the structure of formed multi-chip migration storehouse that can be according to the previous description is embodiments of the present invention.In addition, in other embodiments of the invention, can also the wire bonds district be set, for example cook up the wire bonds district at the opposite side or the adjacent dual-side in wire bonds district 320 at other fringe region of chip 500.Because these embodiment are the change of wire bonds zone position, thus relevant details, this no longer giving unnecessary details more.
Then, the present invention also proposes a kind of stack type chip package structure according to above-mentioned multi-chip migration stack architecture 30 and 50, and is described in detail as follows.Simultaneously, in following declarative procedure, will be that example carries out, yet be stressed that multi-chip migration stack architecture 30 also is suitable for the disclosed content of present embodiment with multi-chip migration stack architecture 50.
At first, please refer to Fig. 6, be the floor map of stack type chip package structure of the present invention.As shown in Figure 6, stack type chip package structure comprises that lead frame 60 and multi-chip migration stack architecture 50 form, wherein formed relatively by interior pin group 610, a plurality of outer pin groups (not being shown on the figure) and the chip bearing 620 of arrangement by a plurality of one-tenth for lead frame 60, its chips bearing 620 is arranged between the interior pin group 610 of a plurality of relative arrangements, and the interior pin group 610 and the chip bearing 620 of a plurality of relative arrangements simultaneously also can form difference in height.In the present embodiment, multi-chip migration stack architecture 50 is arranged on the chip bearing 620, and affixed by adhesion layer 230.And adhesion layer 230 of the present invention also is not defined as aforesaid semi-curing glue, the purpose of this adhesion layer 230 is to engage multi-chip migration stack architecture 50 and chip bearing 620, therefore, so long as have the adhesion material of this function, be embodiments of the present invention, for example: glued membrane (die attached film).Then, by plain conductor 640 multi-chip migration stack architecture 50 is connected with the interior pin group 610 of lead frame 60 again.In addition, 320 li weld pad 312a/344 can be single-row arrangement in the wire bonds district of chip 500, also can be that biserial is arranged, and the present invention does not limit.
Continue please refer to Fig. 6, in the lead frame 60 of stack type chip package structure of the present invention, in order to make lead frame 60 that more electric contact can be provided, with electrical connection as power supply contact, ground contact or signal contact, insulating barrier 611 also further is set on the local location of interior pin 610 in the present invention, and at least one metal pad 613 is set on insulating barrier 611 again.Thus, many many switch-over soldering pads on the pin 610 in making are so can provide more elasticity and application on the circuit design.
In addition, with regard to above-mentioned insulating barrier 611, it can utilize coating (coating) or wire mark (printing) macromolecular material forms, for example: pi (polyimide, PI), or also can utilize the mode of pasting (attaching) to form, for example use adhesive tape (die attached film).Metal pad 613 then can utilize plating (plating) technology or etching (etching) technology, and metal level is formed on the insulating barrier 611.Will emphasize that at this insulating barrier 611 of the present invention can be arranged on whole interior pin 610 or the local interior pin 610, can certainly use multisegment mode to be formed on the interior pin 610, the present invention is not limited yet.In addition, the present invention can also form insulating barrier and again formation metal pad on this insulating barrier more again on the metal pad 611, many more many switch-over soldering pads on the pin 610 in so can making.
Illustrate that then the present invention uses the metal pad on the interior pin 610 to reach the process that plain conductor 640 wire jumpers connect, referring again to Fig. 6.Fig. 6 show one with the weld pad b on the chip 500 (b ') and weld pad c (c ') and interior pin 6103 (6123) and in the schematic diagram that is connected of pin 6102 (6122).Clearly, a plurality of metal pads 613 in present embodiment can utilize on the pin 610 as transit point reach with weld pad b (b ') and weld pad c (c ') and interior pin 6103 (6123) and in pin 6102 (6122) wire jumpers is connected, and can not produce the situations of plain conductor 640 mutual leaps.For example, on the metal pad 613 in the weld pad b on the chip 500 being connected to earlier earlier on the pin 6102, and then the metal pad 613 on the interior pin 6102 is connected with interior pin 6103 with another strip metal lead 640 with a strip metal lead 640.Therefore, can reach weld pad b finished with interior pin 6103 and be connected, and institute must another connection weld pad of leap c reaches the plain conductor 640 of interior pin 6102 when avoiding weld pad b directly is connected with interior pin 6103.Then, carry out weld pad a is connected with a strip metal lead 640 with interior pin 6101, again the weld pad c on the chip 500 is connected to earlier on the frame 6102 that confluxes, then with another strip metal lead 640 weld pad d is connected on the frame 6104 that confluxes again.Therefore, can reach weld pad b is finished in the process that is connected with interior pin 6103, avoid crossing over the plain conductor 640 of another connection weld pad c and interior pin 6102.And the weld pad b ' of another side and weld pad c ' and interior pin 6123 and in pin 6122 wire jumper connection procedures also be to use identical process to finish to be connected, therefore finish weld pad b ' and weld pad c ' and interior pin 6123 and in after being connected of pin 6122, can not produce the situations of plain conductor 640 mutual leaps yet.
Continue please refer to Fig. 7 A and Fig. 7 B, in the lead frame 600 of stack type chip package structure of the present invention, comprise further that also at least one frame 630 that confluxes (bus bar) is arranged between the interior pin group 610 of chip bearing 620 and a plurality of relative arrangements, the frame 630 that wherein confluxes can adopt the strip setting, shown in Fig. 6 A and Fig. 6 B; The frame 630 that confluxes simultaneously also can adopt ring-type setting (not being shown among the figure).In addition, as previously mentioned, 320 li weld pad 312/344 can be single-row arrangement in the wire bonds district of chip 500, also can be that biserial is arranged, and the present invention does not limit.
Illustrate that then the present invention uses the frame 630 that confluxes to reach interior pin 610 and reaches the process that plain conductor 640 wire jumpers connect, referring again to Fig. 7 A.Fig. 7 A shows a schematic diagram that the weld pad on the chip 500 is connected with conflux frame 630 and interior pin group 610.Clearly, present embodiment can utilize conflux frame 6301 and the frame 6302 that confluxes as the transit point of ground connection, with weld pad a and weld pad a ' and interior pin 6101 and in pin 6121 be connected; Then, with the weld pad c on the chip 500 (c ') and weld pad d (d ') and interior pin 6101 (6121) and in the schematic diagram that is connected of pin 6103 (6123).Clearly, metal pad 6131 in present embodiment can be earlier be connected to the weld pad c on the chip 500 and weld pad c ' earlier with a strip metal lead 640 on the pin 6102 and on the metal pad 6132 on the pin 6122, and then metal pad 6131 and metal pad 6132 are connected with interior pin 6101 and interior pin 6121 with another strip metal lead 640; Then, metal pad 6133 in weld pad d and weld pad d ' be connected to earlier on the pin 6103 and on the metal pad 6134 on the pin 6123, and then metal pad 6133 and metal pad 6134 are connected with interior pin 6104 and interior pin 6124 with another strip metal lead 640.Therefore, can reach weld pad c and weld pad c ' are finished in the process that is connected with interior pin 6101 and interior pin 6121, when avoiding weld pad c (c ') directly is connected with interior pin 6101 (6121), the plain conductor 640 that another connection weld pad b (b ') reaches interior pin 6102 (6122) must be crossed over by institute; Simultaneously, to with weld pad d and weld pad d ' and interior pin 6104 and in pin 6124 finish when being connected, when avoiding weld pad d (d ') directly is connected with interior pin 6104 (6124), the plain conductor 640 that another connection weld pad e (e ') reaches interior pin 6103 (6123) must be crossed over by institute.
And in another embodiment, shown in Fig. 7 B, use the structure of the many framves 630 that conflux to reach the schematic diagram that wire jumper connects.At Fig. 7 B promptly is to show a schematic diagram that the weld pad c on the chip 500 (c '), weld pad d (d ') and weld pad e (e ') are connected with pin 6103 (6123) in interior pin 6101 (6121), interior pin 6104 (6124) reach, wherein weld pad a and weld pad a ' are connected with the conflux frame 6301 and the frame 6302 that confluxes, to connect as the ground connection transit point.Clearly, present embodiment can utilize conflux frame 6301 and the frame 6302 that confluxes as the ground connection transit point, and utilizes the conflux frame 6305 and the frame 6304 signal transit points that conflux.For example, metal pad 6131 in the weld pad c on the chip 500 and weld pad c ' being connected to earlier earlier on the pin 6102 with a strip metal lead 640 and on the metal pad 6132 on the pin 6122, and then metal pad 6131 and metal pad 613 are connected with interior pin 6101 and interior pin 6121 with another strip metal lead 640; In addition, metal pad 6133 in weld pad d and weld pad d ' be connected to earlier on the pin 6103 and on the metal pad 6134 on the pin 6123, and then metal pad 6133 and metal pad 6134 are connected with interior pin 6104 and interior pin 6124 with another strip metal lead 640; Follow again, weld pad e and weld pad e ' be connected to earlier on the conflux frame 6305 and the frame 6304 that confluxes, and then with another strip metal lead 640 will conflux frame 6305 and conflux frame 6304 and interior pin 6103 and in pin 6123 be connected.Therefore, can reach with weld pad c and weld pad c ' and interior pin 6101 and in pin 6121 finish and be connected, and when avoiding weld pad c (c ') directly is connected with interior pin 6101 (6121), the plain conductor 640 that another connection weld pad b (b ') reaches interior pin 6102 (6122) must be crossed over by institute; And with weld pad d and weld pad d ' and interior pin 6104 and in pin 6124 finish and be connected, and when avoiding weld pad d (d ') directly is connected with interior pin 6104 (6124), the plain conductor 640 that another connection weld pad e (e ') reaches interior pin 6103 (6123) must be crossed over by institute.
Therefore, the present invention is used as the structure of a plurality of transit points by the metal pad 613 on the interior pin in the lead frame 600 (promptly 6131～6134) and the frame 630 that confluxes (promptly 6301～63010), make when necessary wire jumper connects carrying out circuit to connect, can avoid the staggered leap of plain conductor, and cause unnecessary short circuit, chip that feasible encapsulation is finished produces the problem of reliability, elasticity more in the time of also can making circuit design.
Then, please refer to shown in Fig. 8 A and Fig. 8 B floor map of another embodiment of stack type chip package structure of the present invention.Shown in Fig. 8 A and Fig. 8 B, stack type chip package structure comprises that lead frame 600 and multi-chip migration stack architecture 50 form, wherein formed relatively by interior pin group 610, a plurality of outer pin groups (not being shown on the figure) and the chip bearing 620 of arrangement by a plurality of one-tenth for lead frame 600, its chips bearing 620 is arranged between the interior pin group 610 of a plurality of relative arrangements, also can form difference in height or form a copline between the interior pin group 610 of a plurality of relative arrangements simultaneously and the chip bearing 620.In the present embodiment, also in order to make lead frame 600 that more electric contact can be provided, with electrical connection, so insulating barrier 611 also further is being set on interior pin group's 610 the local location and at least one metal pad 613 is set on insulating barrier 611 again as power supply contact, ground contact or signal contact.Thus, many many switch-over soldering pads 613 on the pin 610 in making are so can provide more elasticity and application on the circuit design.In addition, in the present embodiment, lead frame 600 comprises further that also at least one frame 630 that confluxes (bus bar) is arranged between the interior pin group 610 of chip bearing 620 and a plurality of relative arrangements, the frame 630 that wherein confluxes can adopt at least one strip setting, and each strip setting conflux frame 630 with a plurality of metal segments (promptly 6301～63010) formed, shown in Fig. 8 A and Fig. 8 B; The frame 630 that confluxes simultaneously also can adopt the ring-type setting, and the frame 630 that confluxes of each ring-type setting also is to form with a plurality of metal segments, and the present invention is not limited.In addition, as previously mentioned, 320 li weld pad 312/344 can be single-row arrangement in the wire bonds district of chip 500, also can be that biserial is arranged, and the present invention is restriction also.In addition, because the frame 630 that confluxes of the present invention with a plurality of metal segments (for example: 6301～6306) form all is, therefore each metal segments is all independent separately, make lead frame 600 increase the formed frame 630 that confluxes of many metal segments virtually, these metal segments then can be in order to the electrical connection as power supply contact, ground contact or signal contact, so more elasticity and application on the circuit design can further be provided.
Illustrate that then the present invention uses the frame 630 that confluxes to reach the process that plain conductor 640 wire jumpers connect, referring again to Fig. 8 A.Fig. 8 A shows the schematic diagram that the weld pad on the multi-chip migration stack architecture 50 is connected with the interior pin of lead frame.Clearly, metal pad 613 in the present embodiment utilization on the pin group 610 and a plurality of metal segments of forming the frame 630 that confluxes are (for example: 6301～6306) as transit point, be used for reaching weld pad a (a ') is connected with interior pin 6101 (6121) to interior pin 6105 (6125) wire jumpers to weld pad f (f '), and can not produce plain conductor 640 situations of leaps mutually.For example, earlier the weld pad a on the multi-chip migration stack architecture 50 is connected to the metal segments 6301 of the frame 630 that confluxes earlier, and this metal segments 6301 is as a ground connection tie point with a strip metal lead 640; Pin 6101 in then weld pad b being directly connected to; With a strip metal lead 640 the weld pad c on the multi-chip migration stack architecture 50 is connected to the metal segments 6303 of the frame 630 that confluxes earlier then, and then is connected with interior pin 6103 with will the conflux metal segments 6303 of frame 630 of another strip metal lead 640; Then, on the metal pad 6131 in a strip metal lead 640 the weld pad d on the chip 500 being connected to earlier on the pin 6102, and then metal pad 6131 is connected with interior pin 6101 with another strip metal lead 640.Therefore, when weld pad c and weld pad d and interior pin 6103 and in pin 6101 finish when being connected, can avoid and will connect the mutual leap of 640 of the plain conductor 640 of weld pad c and interior pin 6103 and plain conductors that weld pad d reaches interior pin 6101.Then, carry out weld pad e is connected with the wire jumper of interior pin 6105, earlier the weld pad e on the multi-chip migration stack architecture 50 is connected to the metal segments 6305 of the frame 630 that confluxes earlier, and then is connected with interior pin 6105 with will the conflux metal segments 6305 of frame 630 of another strip metal lead 640 with a strip metal lead 640.Therefore, finish when being connected when weld pad e and interior pin 6105, can avoid connecting weld pad e and the plain conductor 640 of interior pin 6105 must cross over another be connected weld pad f and in the plain conductor 640 of pin 6104.And in the weld pad a ' of another side setting to weld pad f ' and interior pin 6121 to interior pin 6125 as hereinbefore, so its wire jumper connection procedure is also as hereinbefore, so repeat no more.Therefore finishing weld pad a ' after being connected to weld pad f ' and interior pin 6121 to interior pin 6125, can not produce plain conductor 640 situations of leaps mutually yet.
And in another embodiment, when having a plurality of weld pads must carry out the wire jumper connection on the multi-chip migration stack architecture 50, can use the structure of the many framves 630 that conflux to reach, shown in Fig. 8 B.Fig. 8 B shows the schematic diagram that the weld pad on the multi-chip migration stack architecture 50 is connected with interior pin.Clearly, in the present embodiment, insulating barrier 611 is set and at least one metal pad 613 is set on insulating barrier 611 again on the pin group 610 in also being to use, and cooperate that (for example: 6301～63010) the formed frame 630 that confluxes is used as transit point by a plurality of metal segments, be used for reaching weld pad (a/a '～f/f ') is connected with interior pin 610 wire jumpers, and can not produce the situations that plain conductor 640 is crossed over mutually.For example, earlier the weld pad a on the multi-chip migration stack architecture 50 or a ' are connected to metal segments 6305 or 6306 on the frame 630 that confluxes earlier, and this metal segments 6305 or 6306 is as a ground connection tie point with a strip metal lead 640; With a strip metal lead 640 weld pad b on the multi-chip migration stack architecture 50 or b ' are directly connected to earlier on the metal segments 6301 or 6302 of the frame 630 that confluxes then, then again with another strip metal lead 640 will conflux the metal segments 6301 or 6302 of frame 630 be connected on the metal pad 6131 or 6132 on the pin 6102 or 6122, and then in another strip metal lead 640 metal pad 6131 and interior pin 6101 being connected on the pin 6104 or 6124.Then, on the metal pad 6133 or 6134 in a strip metal lead 640 the weld pad d on the multi-chip migration stack architecture 50 or d ' being directly connected to earlier on the pin 6103 or 6123, and then metal pad 6133 or 6134 is connected with interior pin 6105 or 6125 with another strip metal lead 640.
Therefore, when weld pad b or b ' and interior pin 6102 or 6122 and weld pad d or d ' and interior pin 6105 or 6125 finish when being connected, can avoid connecting the mutual leap of weld pad b or b ' and plain conductor 640 with 640 of the plain conductors that is connected weld pad d or d ' and interior pin 6105 or 6122 of interior pin 6102 or 6122.Then weld pad e or e ' are connected to earlier on the metal segments 6307 or 6308 of the frame 630 that confluxes again, and then finish with interior pin 6102 or 6122 and be connected with will the conflux metal segments 6307 or 6308 of frame 630 of another strip metal lead 640, so, also can avoid effectively crossing over the plain conductor 640 that another is connected weld pad f or f ' and interior pin 6103 or 6123 with the plain conductor 640 of interior pin 6102 or 6122 with connecting weld pad e or e '.
Therefore, (for example: 6301～63010) the formed frame 630 that confluxes is used as the structure of a plurality of transit points to present embodiment with a plurality of metal segments by a plurality of metal pads on the interior pin group 610 in the lead frame 600 613, when necessary wire jumper connects carrying out circuit to connect, can avoid the staggered leap of plain conductor, and cause unnecessary short circuit, so can improve the reliability of packaged chip.Simultaneously, elasticity more in the time of also can making circuit design.
Please refer to Fig. 9 A and Fig. 9 B, the floor map of an embodiment again of stack type chip package structure of the present invention.Shown in Fig. 9 A and Fig. 9 B, stack type chip package structure comprises that lead frame 600 and multi-chip migration stack architecture 50 form, wherein formed relatively by interior pin group 610, a plurality of outer pin groups (not being shown on the figure) and the chip bearing 620 of arrangement by a plurality of one-tenth for lead frame 600, its chips bearing 620 is arranged between the interior pin group 610 of a plurality of relative arrangements, also can form difference in height between the interior pin group 610 of a plurality of relative arrangements simultaneously and the chip bearing 620.In the present embodiment, multi-chip migration stack architecture 50 is to be arranged on the chip bearing 620, and by plain conductor 640 multi-chip migration stack architecture 50 is connected with pin group 610 within the lead frame 600.
Continue please refer to Fig. 9 A and Fig. 9 B, in the lead frame 600 of stack type chip package structure of the present invention, insulating barrier 611 is set on the interior pin group 610 and at least one metal pad 613 is set on insulating barrier 611 again, thus, many many switch-over soldering pads on the pin group 610 in making are so can provide more elasticity and application on the circuit design.In addition, insulating barrier 632 also is set and at least one metal pad 634 is set on insulating barrier 632 again on the frame 630 that confluxes in the present invention, more elasticity and application on the circuit design make the also many many switch-over soldering pads on the frame 630 that conflux, so can be provided.
Be stressed that the frame 630 that confluxes can adopt the strip setting, shown in Fig. 9 A and Fig. 9 B; The frame 630 that confluxes simultaneously also can adopt ring-type setting (not being shown among the figure), and the present invention does not limit.In addition, as previously mentioned, 320 li weld pad 312a/344 can be single-row arrangement in the wire bonds district of chip 500, also can be that biserial is arranged, and the present invention is restriction also.
The process that present embodiment uses plain conductor 640 wire jumpers to connect then is described, clearly, metal pad 613 in the present embodiment utilization on the pin group 610 and a plurality of metal pads 634 on the conflux frame 6301 and the frame 6302 that confluxes reach as transit point weld pad a (a ') are connected with interior pin 6101 (6121) to interior pin 6105 (6125) wire jumpers to weld pad f (f '), and can not produce the situations of plain conductor 640 mutual leaps.For example, with a strip metal lead 640 the weld pad a on the multi-chip migration stack architecture 50 is connected to the frame 6301 that confluxes earlier earlier, and this frame 6301 that confluxes is as a ground connection tie point; Pin 6102 in then weld pad b being directly connected to; On the metal pad 6131 in a strip metal lead 640 the weld pad c on the multi-chip migration stack architecture 50 being connected to earlier then on the pin 6102, and then metal pad 6131 is connected with interior pin 6101 with another strip metal lead 640.Therefore, finish when being connected when weld pad c and interior pin 6101, the plain conductor 640 that can avoid connecting weld pad c and interior pin 6101 and weld pad b reach the mutual leap of 640 of the plain conductors of interior pin 6102.
Follow again, on the metal pad 6133 in a strip metal lead 640 the weld pad d on the multi-chip migration stack architecture 50 being connected to earlier on the pin 6103, and then metal pad 6133 is connected with interior pin 6104 with another strip metal lead 640; Then, carry out weld pad e is connected with the wire jumper of interior pin 6105, on the metal pad 6135 in the weld pad e on the multi-chip migration stack architecture 50 being connected to earlier earlier on the pin 6104, and then metal pad 6135 is connected with interior pin 6105 with another strip metal lead 640 with a strip metal lead 640; At last, carry out weld pad f is connected with the wire jumper of interior pin 6103, earlier the weld pad f on the multi-chip migration stack architecture 50 is connected to the metal pad 6341 of the frame 6301 that confluxes earlier, and then is connected with interior pin 6103 with will the conflux metal pad 6341 of frame 6301 of another strip metal lead 640 with a strip metal lead 640.Therefore, when weld pad d, weld pad e, weld pad f and interior pin 6103, interior pin 6104, when interior pin 6105 is finished and is connected, can avoid connecting weld pad d (e) and the plain conductor 640 of interior pin 6104 (6105) must cross over another be connected weld pad f and in the plain conductor 640 of pin 6103.And in the weld pad a ' of another side setting to weld pad f ' and interior pin 6121 to interior pin 6125 as hereinbefore, so its wire jumper connection procedure is also as hereinbefore, so repeat no more.Therefore finishing weld pad a ' after being connected to weld pad f ' and interior pin 6121 to interior pin 6125, can not produce plain conductor 640 situations of leaps mutually yet.
And in another embodiment, shown in Fig. 9 B, when having a plurality of weld pads must carry out the wire jumper connection on the chip 500, can use the structure of the many framves 630 that conflux to reach.In the present embodiment, on metal pad 611 more than being provided with on the interior pin group 610 and a plurality of frame 630 that confluxes a plurality of metal pads 634 are set also and are used as transit point, wherein metal pad 611 and metal pad 634 and interior pin group 610 and 630 on the frame that confluxes are isolated by insulating barrier.Because the actual online and wire jumper process of present embodiment is identical with aforesaid Fig. 9 A, so repeat no more.
In addition, to emphasize once more, multi-chip migration stack architecture 50 of the present invention is fixed on the lead frame 600, a plurality of chips 500 in the multi-chip migration stack architecture 50 wherein, its can be same size and identical function chip (for example: memory chip), or the chip size in a plurality of chips 500 and function (for example: the chip of the superiors is that other chip of chip for driving then is a memory chip) inequality, shown in Fig. 2 E and 5C.And for the chip size of multi-chip migration storehouse or chip functions etc., be not feature of the present invention, just repeat no more in this.
Then please refer to Figure 10, the present invention is along the generalized section of Fig. 6 along the multi-chip migration stack package structure of AA line segment section.As shown in figure 10, be connected by many strip metals lead 640 between lead frame 60 and the multi-chip migration stack architecture 50, wherein lead frame 60 is made up of interior pin group 610, a plurality of outer pin groups (not being shown on the figure) and the chip bearing 620 of a plurality of relative arrangements, and chip bearing 620 is to be arranged between the interior pin group 610 of a plurality of relative arrangements, and forms difference in height with the interior pin group 610 of a plurality of relative arrangements.Insulating barrier 611 is set on the interior in the present embodiment pin group 610 and at least one metal pad 613 is set on insulating barrier 611 again.Thus, many many switch-over soldering pads on the pin group 610 in making are so can provide more elasticity and application on the circuit design.
As shown in figure 10, plain conductor 640 is connected in the first weld pad 312a or the 3rd weld pad 344 (the first weld pad 312a or the 3rd weld pad 344 among for example aforementioned the 3rd figure) of chip 500a with routing technology with the end of plain conductor 640a, and the other end of plain conductor 640a then is connected in the first weld pad 312a or the 3rd weld pad 344 of chip structure 500b; Then, the end of plain conductor 640b is connected on the first weld pad 312a or the 3rd weld pad 344 of chip 500b, and then the other end of plain conductor 640b is connected on the first weld pad 312a or the 3rd weld pad 344 of chip 500c; Then repeat the process of plain conductor 640a and 640b again, chip 500c is finished being electrically connected with chip 500d with plain conductor 640c; Follow again, with the interior pin group 610 of chip 500a and a plurality of relative arrangements of lead frame 600 (for example: interior pin 6101 or 6121) finish electrical connection with plain conductor 640d.Thus, successively finish connection by plain conductor 640a, 640b, 640c and 640d etc. after, just chip 500a, 500b, 500c and 500d can be electrically connected on lead frame 600, wherein the material of these plain conductors 640 can be used gold.
Simultaneously, because the interior pin group 610 of the lead frame 600 of present embodiment is provided with metal pad 613, it can be used as the switch-over soldering pad that comprises power supply contact, ground contact or signal contact.For example, when signaling transfer point that metal pad 613 connects as circuit, so the weld pad that the end of plain conductor 640e can be connected in chip 500d (for example: weld pad b '), and the other end of plain conductor 640e be connected to metal pad 613 (for example: metal pad 6132), and then by plain conductor 640f with metal pad 6132 be connected to some in pin (for example: interior pin 6123).In addition, the chip 500d of multi-chip migration stack architecture 50 the superiors, it also can be arranged at a plurality of weld pads on it on another side of chip, shown in Fig. 2 D and 5B again.So at another side of chip 500a, then can by many strip metals lead 640g with chip 500a (for example: weld pad a) with interior pin group 610 (for example: interior pin 6101) be connected.The weld pad that then end of plain conductor 640h is connected in chip 500a (for example: weld pad b), and the other end of plain conductor 640h be connected to metal pad 613 (for example: metal pad 6131), and then by plain conductor 640i with metal pad 6131 be connected to some in pin (for example: interior pin 6103).So, switching by metal pad 613, increase with regard to not producing the radian that makes the plain conductor that to cross in order to cross over other plain conductor, also so not only can increase the elasticity in circuit design or the application, also can effectively improve the production capacity and the reliability of packaging technology.
In addition, also be stressed that, chip 500b directly is stacked on the chip 500a, be fixed together as adhesion layer with macromolecular material 230 between the two, and chip 500b is the zone in addition, wire bonds district 320 that is stacked over chip 500a, shown in Fig. 5 a to Fig. 5 c, be successfully to carry out with follow-up routing technology.In addition, present embodiment does not limit the routing technology of plain conductor 640, so it also can select to be connected in regular turn by the direction of the weld pad on the chip 500d to chip 500a, chip 500a is connected with lead frame 600 at last again.
Then please refer to Figure 11, the generalized section of multi-chip migration stack package structure of the present invention (be Fig. 7 A along AA line segment or Fig. 8 A along the AA line segment generalized section).As shown in figure 11, be connected by many strip metals lead 640 between lead frame 600 and the multi-chip migration stack architecture 50, wherein lead frame 600 is made up of interior pin group 610, a plurality of outer pin groups (not being shown on the figure) and the chip bearing 620 of a plurality of relative arrangements, and chip bearing 620 is arranged between the interior pin group 610 of a plurality of relative arrangements, and form differences in height with the interior pin group 610 of a plurality of relative arrangements, and at least one conflux frame 630 be arranged between pin group 610 and the chip bearing 620.The frame 630 that confluxes in the present embodiment is and 620 one-tenth coplanar settings of chip bearing.In the present embodiment, on the interior pin group 610 insulating barrier 611 is set and at least one metal pad 613 is set on insulating barrier 611 again.
As shown in figure 11, plain conductor 640 is connected in the first weld pad 312a or the 3rd weld pad 344 (for example first weld pad 312a or the 3rd weld pad 344 in the earlier figures 3) of chip 500a with routing technology with the end of plain conductor 640a, and the other end of plain conductor 640a then is connected in the first weld pad 312a or the 3rd weld pad 344 of chip structure 500b; Then, the end of plain conductor 640b is connected on the first weld pad 312a or the 3rd weld pad 344 of chip 500b, and then the other end of plain conductor 600b is connected on the first weld pad 312a or the 3rd weld pad 344 of chip 500c; Then repeat the process of plain conductor 640a and 640b again, chip 500c is finished being electrically connected with chip 500d with plain conductor 640c; Follow again, with the interior pin group 610 of chip 500a and a plurality of relative arrangements of lead frame 600 (for example: interior pin 6102 or 6122) finish electrical connection with plain conductor 640d.Thus, successively finish connection by plain conductor 640a, 640b, 640c and 640d etc. after, just chip 500a, 500b, 500c and 500d can be electrically connected on lead frame 600, wherein the material of these plain conductors 640 can be used gold.
Simultaneously, because the lead frame 600 of present embodiment also is provided with the frame 630 that confluxes except interior pin group 610 is provided with a plurality of metal pads 613, it can be used as electric connection point or the signaling transfer point that comprises power supply contact, ground contact or signal contact.For example, with Fig. 8 A is example, when the transit point that connects as circuit with the frame 630 that confluxes, so the end of plain conductor 640e can be connected on the weld pad (for example: weld pad b ' c ' or e ') of chip 500a, and the other end of plain conductor 640e is connected on the frame that confluxes (for example: frame 6302 confluxes), and then by plain conductor 640f the frame 6302 that confluxes (for example: interior pin 6123) is connected to some interior pins.Then, with the end of plain conductor 640g be connected in chip 500a weld pad (for example: weld pad d '), and the other end of plain conductor 640g be connected on the pin 6122 metal pad (for example: metal pad 6132); And then with another strip metal lead 640h with metal pad 6132 be connected to some in pin (for example: interior pin 6121).
In addition, the chip 500d of multi-chip migration stack architecture 50 the superiors, it also can be arranged at a plurality of weld pads on it on another side of chip, shown in Fig. 2 D and 5B again.So at another side of chip 500d, then can by many strip metals lead 640i with the weld pad on the chip 500d (for example: weld pad b) with interior pin group 610 (for example: interior pin 6102) be connected.Then, the weld pad that is connected in chip 500d with the end of plain conductor 640j (for example: weld pad c), and the other end of plain conductor 640j is connected on the frame that confluxes (for example: frame 6303 confluxes), and then by plain conductor 640k will conflux frame 6303 be connected to some in pin (for example: interior pin 6103).Follow again, with the end of plain conductor 640m be connected in chip 500a weld pad (for example: weld pad d), and the other end of plain conductor 640m be connected on the pin 6102 metal pad (for example: metal pad 6131); And then with another strip metal lead 640n with metal pad 6131 be connected to some in pin (for example: interior pin 6101).
In addition, be stressed that also chip 500b directly is stacked on the chip 500a, is fixed together as adhesion layer with a macromolecular material between the two, and chip 500b is the zone in addition, wire bonds district 320 that is stacked over chip 500a, is can successfully carry out with follow-up routing technology.In addition, present embodiment does not limit the routing technology of plain conductor 640, so it also can select to be connected in regular turn by the direction of the weld pad on the chip 500d to chip 500a, chip 500a is connected with lead frame 600 at last again.
Then please refer to Figure 12～Figure 14, for along Fig. 7 A along the AA line segment or Fig. 8 A along the generalized section of AA line segment, the generalized section of another embodiment of multi-chip migration stack architecture of the present invention.Difference between Figure 12～Figure 14 of the present invention and above-mentioned Figure 11 be the frame 630 that confluxes in the lead frame 600 be arranged in geometric position between pin group 610 and the chip bearing 620 inequality, Figure 12 in the present embodiment for example, its frame 630 that confluxes is and 610 one-tenth coplanar settings of interior pin group; Figure 13 in the present embodiment becomes into the setting of difference in height between its conflux frame 630 and interior pin group 610 and chip bearing 620; And Figure 14 in the present embodiment is a copline between pin group 610 and the chip bearing 620 in the difference between itself and above-mentioned Figure 11～Figure 13 is in the lead frame 600, the then formation difference in height between frame 630 and interior pin group 610 and the chip bearing 620 of confluxing.Clearly, Figure 12～Figure 14 is except the structure of lead frame 600 slightly the difference, comes connection procedure then identical by many strip metals lead 640 between lead frame 600 and the multi-chip migration stack architecture 50, and routing technology is not feature of the present invention, so repeat no more.
Again then referring again to Figure 15, the again generalized section of an embodiment of Fig. 7 B of the present invention along BB line segment or Fig. 8 B along the BB line segment.Difference between Figure 15 and Figure 11～Figure 14 is that the frame 630 that confluxes among Figure 15 is to use the structure of a plurality of framves that conflux, and the set-up mode of these a plurality of framves 630 that conflux can be the strip setting of Fig. 7 B, the ring-type setting that also can be, and the present invention is not then limited.Same, also can be further (for example: 6301～63010) form on the frame 630 that confluxes in the present embodiment with a plurality of metal segments.Clearly, because the increase of the frame quantity of confluxing makes the quantity that can be used as electrical connection also just increase, therefore can be so that the weld pad (312a on the multi-chip stack structure 50; 344) connection has more elasticity, so, increase with regard to not producing the radian that makes the plain conductor that to cross in order to cross over other plain conductor, also so not only can increase the elasticity in circuit design or the application, also can effectively improve the production capacity and the reliability of packaging technology.Owing to come connection procedure then identical by many strip metals lead 640 between lead frame 600 and the multi-chip migration stack architecture 50, and routing technology is not feature of the present invention, so repeat no more.
Please refer to Figure 16～Figure 19, the present invention is along the generalized section of Fig. 9 A along the multi-chip migration stack package structure of AA line segment section.As shown in figure 16, be connected by many strip metals lead 640 between lead frame 600 and the multi-chip migration stack architecture 50, wherein lead frame 600 is made up of interior pin group 610, a plurality of outer pin groups (not being shown on the figure) and the chip bearing 620 of a plurality of relative arrangements, and chip bearing 620 is arranged between the interior pin group 610 of a plurality of relative arrangements, and form differences in height with the interior pin group 610 of a plurality of relative arrangements, and at least one conflux frame 630 be arranged between pin group 610 and the chip bearing 620.Insulating barrier 611 is set on the interior in the present embodiment pin group 610 and at least one metal pad 613 is set on insulating barrier 611 again.Thus, many many switch-over soldering pads on the pin group 610 in making are so can provide more elasticity and application on the circuit design.In addition, become the setting of a copline between conflux frame 630 and the chip bearing 620 in the present embodiment, the frame 630 that wherein confluxes can adopt the strip setting, shown in Fig. 9 A and Fig. 9 B; The frame 630 that confluxes simultaneously also can adopt ring-type setting (not being shown among the figure).In addition, in order to make lead frame 600 that more electric contact can be provided, with electrical connection, insulating barrier 632 more is set and at least one metal pad 634 is set on insulating barrier 632 again on the frame 630 that confluxes in the present invention as power supply contact, ground contact or signal contact.More elasticity and application on the circuit design thus, make the many many switch-over soldering pads on the frame 630 that conflux, so can be provided.
As shown in figure 16, plain conductor 640 is connected in the first weld pad 312a or the 3rd weld pad 344 (the first weld pad 312a or the 3rd weld pad 344 among for example aforementioned the 3rd figure) of chip 500a with routing technology with the end of plain conductor 640a, and the other end of plain conductor 640a then is connected in the first weld pad 312a or the 3rd weld pad 344 of chip structure 500b; Then, the end of plain conductor 640b is connected on the first weld pad 312a or the 3rd weld pad 344 of chip 500b, and then the other end of plain conductor 600b is connected on the first weld pad 312a or the 3rd weld pad 344 of chip 500c; Then repeat the process of plain conductor 640a and 640b again, chip 500c is finished being electrically connected with chip 500d with plain conductor 640c; Follow again, with plain conductor 640d with the weld pad on the chip 500a (for example: weld pad b ') with the interior pin group 610 of a plurality of relative arrangements of lead frame 600 (for example: interior pin 6102 or 6122) finish electrical connection.Thus, successively finish connection by plain conductor 640a, 640b, 640c and 640d etc. after, just chip 500a, 500b, 500c and 500d can be electrically connected on lead frame 600, wherein the material of these plain conductors 640 can be used gold.
Simultaneously, because the lead frame 600 of present embodiment is except interior pin group 610 is provided with a plurality of metal pads 613, also be provided with a plurality of metal pads 634 on the frame 630 that confluxes again, it can be used as electric connection point or the signaling transfer point that comprises power supply contact, ground contact or signal contact.For example, with Fig. 9 A is example, when the transit point that connects as circuit with the metal pad 634 on the frame 630 that confluxes, so the weld pad that the end of plain conductor 640e can be connected in chip 500a (for example: weld pad f '), and the other end of plain conductor 640e is connected on the frame that confluxes (for example: frame 6342 confluxes), and then by plain conductor 640f the frame 6342 that confluxes (for example: interior pin 6123) is connected to some interior pins.Then, with the end of plain conductor 640g be connected in chip 500a weld pad (for example: weld pad c '), and the other end of plain conductor 640g be connected on the pin 6122 metal pad (for example: metal pad 6132); And then with another strip metal lead 640h with metal pad 6132 be connected to some in pin (for example: interior pin 6121).In addition, the chip 500d of multi-chip migration stack architecture 50 the superiors, it also can be arranged at a plurality of weld pads on it on another side of chip, shown in Fig. 2 D and 5B again.So at another side of chip 500d, then can by many strip metals lead 640i with the weld pad on the chip 500d (for example: weld pad b) with interior pin group 610 (for example: interior pin 6102) be connected.Then, the weld pad that is connected in chip 500d with the end of plain conductor 640j (for example: weld pad f), and the other end of plain conductor 640j is connected on the frame that confluxes (for example: frame 6341 confluxes), and then by another plain conductor 640k will conflux frame 6341 be connected to some in pin (for example: interior pin 6103).Follow again, with the end of plain conductor 640m be connected in chip 500d weld pad (for example: weld pad d), and the other end of plain conductor 640m be connected on the pin 6102 metal pad (for example: metal pad 6133); And then with another strip metal lead 640n with metal pad 6133 be connected to some in pin (for example: interior pin 6104).
Then please refer to Figure 17～Figure 19, for along the generalized section of Fig. 9 A along the AA line segment, the generalized section of another embodiment of multi-chip migration stack architecture of the present invention.Difference between Figure 17～Figure 19 of the present invention and above-mentioned Figure 16 be the frame 630 that confluxes in the lead frame 600 be arranged in geometric position between pin group 610 and the chip bearing 620 inequality, Figure 17 in the present embodiment for example, its frame 630 that confluxes is and 610 one-tenth coplanar settings of interior pin group; Figure 18 in the present embodiment becomes the setting of difference in height between its conflux frame 630 and interior pin group 610 and chip bearing 620; And Figure 19 in the present embodiment is a copline between pin group 610 and the chip bearing 620 in the difference between itself and above-mentioned Figure 16～Figure 18 is in the lead frame 600, the then formation difference in height between frame 630 and interior pin group 610 and the chip bearing 620 of confluxing.Clearly, Figure 17～Figure 19 is except the structure of lead frame 600 slightly the difference, is to come connection procedure then identical by many strip metals lead 640 between lead frame 600 and the multi-chip migration stack architecture 50, and routing technology is not feature of the present invention, so repeat no more.
Then referring again to Figure 20, Fig. 9 B of the present invention is along the generalized section of an embodiment again of BB line segment again.Difference between Figure 20 and Figure 16～Figure 19 is that the frame 630 that confluxes among Figure 20 is to use the structure of a plurality of framves that conflux, and the set-up mode of these a plurality of framves 630 that conflux can be the strip setting of Fig. 9 B, the ring-type setting (not being shown among the figure) that yet can be, the present invention is not then limited.Clearly, because the increase of the frame quantity of confluxing makes the quantity that can be used as electrical connection also just increase, therefore can be so that the weld pad (312a on the multi-chip stack structure 50; 344) connection has more elasticity, so, increase with regard to not producing the radian that makes the plain conductor that to cross in order to cross over other plain conductor, also so not only can increase the elasticity in circuit design or the application, also can effectively improve the production capacity and the reliability of packaging technology.Owing to come connection procedure then identical by many strip metals lead 640 between lead frame 600 and the multi-chip migration stack architecture 50, and routing technology is not feature of the present invention, so repeat no more.
By above explanation, embodiment described in the present invention does not limit the quantity of stack chip 500, all persons of ordinary skill in the field should be according to above-mentioned disclosed method, and produces the stack type chip package structure of the chip 500 that has more than three.Simultaneously, the storehouse direction of multi-chip migration stack architecture 50 of the present invention does not limit person disclosed in the embodiment yet, and it also can be with the storehouse direction of chip 500 to carry out the storehouse of side-play amount with respect to the direction disclosed in the previous embodiment.Because the mode that chip join mode between the multi-chip migration stack architecture (being called 70) of different directions and multi-chip migration stack architecture 70 engage with lead frame 600, and use plain conductor 640 to connect mode of multi-chip migration stack architecture 70 and lead frame 600 or the like, all identical with previous described embodiment, therefore for the execution mode of multi-chip migration stack architecture and lead frame 600, just repeat no more in this.
Because the interior pin group 610 on the lead frame 600 arranges relatively, and on interior pin group 610, be provided with a plurality of metal pads 613, so the present invention also proposes a kind of multi-chip migration stack architecture 50,70 with different directions and is arranged at jointly on the chip bearing 620 of lead frame 600, as shown in figure 21.Same, multi-chip migration stack architecture 50,70 among Figure 21 and the mode of lead frame 600 joints and the mode that is connected multi-chip migration stack architecture 50,70 and lead frame 600 with plain conductor 640, all identical with previous described embodiment, just repeat no more in this.
Then, please refer to Figure 22 and Figure 23, clearly, the difference between Figure 22 and Figure 21 is also to be provided with among Figure 22 at least one frame 630 that confluxes, and also can a plurality of metal pads 634 be set on the frame 630 that confluxes optionally again, as shown in figure 23.Same, multi-chip migration stack architecture 50,70 among Figure 22 and Figure 23 and the mode of lead frame 600 joints and the mode that is connected multi-chip migration stack architecture 50,70 and lead frame 600 with plain conductor 640, all identical with previous described embodiment, just repeat no more in this.Be provided with by this, make the quantity that can be used as electrical connection also just increase, therefore can be so that the weld pad (312a on the multi-chip stack structure 50,70; 344) connection has more elasticity, so, increase with regard to not producing the radian that makes the plain conductor that to cross in order to cross over other plain conductor, also so not only can increase the elasticity in circuit design or the application, also can effectively improve the production capacity and the reliability of packaging technology.To emphasize at this, aforementioned about interior pin group 610, chip bearing 620 among the lead frame 600 and the height setting between frame 630 and the three of confluxing, in the embodiment of Figure 22 and Figure 23, all be suitable for.
To emphasize again at this, in all above-mentioned embodiment of the present invention, insulating barrier 632 on the insulating barrier 611 on the interior pin group 610 and the frame 630 that confluxes, all can utilize coating (coating) or wire mark (printing) macromolecular material forms, for example: pi (polyimide, PI), or also can utilize the mode of pasting (attaching) to form, for example use adhesive tape (die attachedfilm).Metal pad 613 and metal pad 634 then can utilize plating (plating) technology or etching (etching) technology, and metal level is formed on insulating barrier 611 and the insulating barrier 632.Will emphasize that at this insulating barrier 611 of the present invention and insulating barrier 632 can be arranged on the whole interior pin 610 and the frame 630 that confluxes, on the pin 610 and the frame 630 that confluxes, the present invention is not limited yet in can certainly being formed on multisegment mode.In addition, the present invention can also form insulating barrier and again formation metal pad on this insulating barrier more again on metal pad 611 and metal pad 634, so can make many more many switch-over soldering pads on the lead frame of the present invention.
The present invention then discloses a kind of multi-chip stack packaging structure that many switch-over soldering pads are set again in the interior pin group 610 of asymmetric lead frame.Please refer to Figure 24, the lead frame generalized section of another embodiment of the present invention.As shown in figure 24, interior pin 610 and outer pin 620 that lead frame 600 is arranged relatively by a plurality of one-tenth are formed, wherein interior pin 610 includes pin group 616 in a plurality of parallel first interior pin groups 615 and second, pin group 616 end separates with a gap in the first interior pin group 615 and second simultaneously, make 616 one-tenth relative arrangements of pin group in win interior pin group 615 and second, and pin group 616 height is inequality in the first interior pin group 615 and second.In addition, in first pin group 615 and the second interior pin group 616 near the end, an insulating barrier 611 is set and at least one metal pad 613 is set on insulating barrier 611 again.
Continue please refer to Figure 25, the first interior pin group 615 is for having heavy structure of putting (downset), and this heavy interposed structure is formed by platform part 619 and connecting portion 617, and wherein the height of platform part 619 is identical with pin group 616 height in second.In addition, the present invention does not limit the shape of connecting portion 617, and it can be inclined-plane or near normal face.To emphasize also that at this platform part 619 also can be the part of pin group 615 in first with connecting portion 617.
Then, please refer to Figure 26, the generalized section of multi-chip migration stack package structure of the present invention.At first, in first of lead frame 600 between pin group 615 and the multi-chip migration stack architecture 50 by with adhesion layer 230 as the material that engages; And in second, on the pin group 616, insulating barrier 611 then is set and at least one metal pad 613 is set on insulating barrier 611 again.Clearly, the adhesion layer 230 in Figure 26 is attached on the back side of chip 500, as shown in Figure 2; In addition, this adhesion layer 230 also can be selected to be arranged on the first interior pin group 615 of lead frame 600, is connected with multi-chip migration stack architecture 50 then.In addition, in the present embodiment, for first interior pin group 615 of lead frame 600 and the juncture between the multi-chip migration stack architecture 50, also can select to use adhesive tape to be used as connecting material particularly a kind of two-sided adhesive tape (dieattached film) with tackness.
After finishing being connected of lead frame 600 and multi-chip migration stack architecture 50, carry out the connection of plain conductor immediately.Please continue with reference to Figure 26, plain conductor 640 is connected in the end of plain conductor 640a with routing technology the weld pad of chip 500a, the for example first weld pad 312a or the 3rd weld pad 344 in the earlier figures 3, the other end of plain conductor 640a then is connected on the first weld pad 312a or the 3rd weld pad 344 of chip 500b; Then the end of plain conductor 640b is connected in the first weld pad 312a or the 3rd weld pad 344 of chip 500b, and the other end of plain conductor 640b then is connected on the first weld pad 312a or the 3rd weld pad 344 of chip 500c; Then, repeat the process of plain conductor 640b again, chip 500c and 500d are finished electrical connection with plain conductor 640c.Then, with plain conductor 640d with chip 500d and lead frame 600 first in pin group 615 finish and be electrically connected, then, with plain conductor 640e chip 500d is finished with the second interior pin group 616 again and is connected.Thus, after successively finishing connection by plain conductor 640a, 640b, 640c, 640d and 640e etc., just chip 500a, 500b, 500c and 500d can be electrically connected on the first interior pin group 615 and the second interior pin group 616 of lead frame 600, wherein the material of these plain conductors 640 can be used gold.Then, can be optionally connect the metal pad 613 on the pin group 616 in chip 500d and second, and then finish with a certain second interior pin group 616 with another plain conductor 640g and to be connected with plain conductor 640f.At last, the multi-chip migration stack package structure that to finish electrical connection again is covered on the platform part 619 and the second interior pin group 616 of multi-chip migration stack architecture 50, lead frame 600 with sealant 70, and the outer pin 620 of lead frame 600 is exposed to outside the sealant 70, can forms stack type chip package structure.
In addition, the mode that connects lead frame 600 and multi-chip migration stack architecture 50 with plain conductor 640, except above-mentioned process, after also can being chosen in the structure of finishing multi-chip migration stack architecture 50, promptly carry out chip 500a earlier, 500b, the plain conductor of 500c and 500d is electrically connected technology, the process of its connection is identical with aforementioned process, then, after the multi-chip migration stack architecture 50 that will finish electrical connection again and lead frame 600 stick together and are integral, carry out the technology that plain conductor connects again, multi-chip migration stack architecture 50 is finished with the interior pin 610 of lead frame 600 be connected.
By above explanation, embodiment described in the present invention does not limit the quantity of stack chip 500, all persons of ordinary skill in the field should be according to above-mentioned disclosed method, and produces the stack type chip package structure of the chip 500 that has more than three.Simultaneously, the multi-chip migration stack architecture 50 in the embodiment of Figure 26 also can change multi-chip migration stack architecture 30 into.Because therefore these two multi-chip migration stack architectures 30 and multi-chip migration stack architecture 50 repeat no more all identical with plain conductor connection procedure after lead frame 600 engages.
Then, please continue with reference to Figure 27 the generalized section of another embodiment of multi-chip migration stack package structure of the present invention.As shown in figure 27, interior pin 610 and outer pin 620 that lead frame 600 is arranged relatively by a plurality of one-tenth are formed, wherein interior pin 610 includes pin group 616 in a plurality of parallel first interior pin groups 615 and second, pin group 616 end separates with a gap in the first interior pin group 615 and second simultaneously, make 616 one-tenth relative arrangements of pin group in win interior pin group 615 and second, and pin group 616 height is inequality in the first interior pin group 615 and second.As shown in figure 27, the first interior pin group's 615 part forms heavy structure of putting by platform part 618 and connecting portion 617; And in second pin group 616 part, except locating to form the recessed approximate stair-stepping structure 6161 endways, and on recessed approximate stair-stepping structure 6161, insulating barrier 611 then is set and at least one metal pad 613 is set on insulating barrier 611 again, also the second interior pin group 616 with Figure 26 is identical for all the other.Clearly, present embodiment and Figure 26 difference place, pin group 616 end can form recessed approximate stair-stepping structure 6161 in second, and pin group 616 is low in the terminal aspect ratio second of this recessed approximate stair-stepping structure 6161, therefore when carrying out the connection technology of plain conductor 640, plain conductor 640e can be connected to the end of recessed approximate stair-stepping structure 615 from chip 500d, so, can reduce the radian of plain conductor 640e.Because Figure 26 is all identical with the plain conductor connection procedure of Figure 27, therefore repeat no more.
Then, please refer to Figure 28, the generalized section of an embodiment again of multi-chip migration stack package structure of the present invention.The difference of Figure 28 and Figure 27 be in Figure 28 first in pin group 615 also be provided with insulating barrier 611 and at least one metal pad 613 be set on insulating barrier 611 again with last, and pin group 616 end is the approximate stair-stepping structure 6162 of formation epirelief second in.Clearly, pin group 616 height in the terminal aspect ratio second of the approximate stair-stepping structure 6162 of this epirelief.When carrying out the connection technology of plain conductor 640, plain conductor 640d can be connected to the metal pad 613 on the pin group 615 in first from chip 500d, and then is connected the approximate stair-stepping structure 6162 of the metal pad 613 on the pin group 615 and epirelief in first by another plain conductor 640e.So, also can form the encapsulating structure of multi-chip stack.Because Figure 26, Figure 27 are all identical with the plain conductor connection procedure of Figure 28, therefore repeat no more.And being stressed that metal pad 613 can be arranged on the first interior pin group 615 and the second interior pin group 616, person described in above-mentioned Figure 26, Figure 27 and Figure 28 is embodiments of the invention, is not to be used for limiting embodiments of the present invention.
Apparently, according to the description among the top embodiment, the present invention has many corrections and difference.Therefore need be understood in the scope of its additional claim item, except above-mentioned detailed description, the present invention can also implement widely in other embodiments.Above-mentioned is preferred embodiment of the present invention only, is not in order to limit claim of the present invention; All other do not break away from the equivalence of being finished under the disclosed spirit and changes or modification, all should be included in the claim scope.
Claims (22)
1. have the stack type chip package structure of switch-over soldering pad on the interior pin of a lead frame, it is characterized in that comprising:
Lead frame is made up of the interior pin group of a plurality of relative arrangements, a plurality of outer pin group and chip bearing, and wherein said chip bearing system is arranged between the interior pin group of these a plurality of relative arrangements, and forms difference in height with the interior pin group of these a plurality of relative arrangements;
The multi-chip migration stack architecture is formed by a plurality of chip stacks, and above-mentioned multi-chip migration stack architecture is arranged on this chip bearing and with the interior pin group of above-mentioned a plurality of relative arrangements and forms electrical connection; And
Packaging body coats above-mentioned multi-chip migration stack architecture and above-mentioned lead frame, and above-mentioned a plurality of outer pin groups stretch out in outside the above-mentioned packaging body;
Also optionally formed a plurality of metal pads on insulating layer coating and the above-mentioned insulating barrier on the local location of the interior pin in the wherein above-mentioned lead frame.
2. encapsulating structure according to claim 1 is characterized in that the above-mentioned metal pad on the above-mentioned interior pin can be to be formed on the above-mentioned insulating barrier by electroplating technology or etch process.
3. have the stack type chip package structure of switch-over soldering pad on the interior pin of a lead frame, it is characterized in that comprising:
Lead frame, formed by the interior pin group of a plurality of relative arrangements, a plurality of outer pin group and chip bearing, the said chip bearing is arranged between the interior pin group of above-mentioned a plurality of relative arrangements and with the interior pin group of above-mentioned a plurality of relative arrangements and forms difference in height, is also optionally formed a plurality of metal pads on insulating layer coating and the above-mentioned insulating barrier on the local location of pin in above-mentioned;
The multi-chip migration stack architecture is formed by a plurality of chip stacks, and above-mentioned multi-chip migration stack architecture is arranged on the said chip bearing and with the interior pin group of above-mentioned a plurality of relative arrangements and forms electrical connection; And
Packaging body coats above-mentioned multi-chip migration stack architecture and above-mentioned lead frame, and above-mentioned a plurality of outer pin groups stretch out in outside the above-mentioned packaging body;
Each said chip in the wherein above-mentioned multi-chip migration stack architecture comprises:
The chip body, has the wire bonds zone, above-mentioned wire bonds region adjacent is in the single side or the adjacent dual-side of said chip body, and wherein the said chip body has a plurality of first weld pad and a plurality of extra-regional second weld pads of above-mentioned wire bonds that are positioned at that are positioned at above-mentioned wire bonds zone;
First protective layer is arranged on the said chip body, and wherein above-mentioned first protective layer has a plurality of first openings, to expose above-mentioned these first weld pads and above-mentioned these second weld pads;
Reset and put line layer, be arranged on above-mentioned first protective layer, wherein above-mentioned reseting put line layer and extended in the above-mentioned wire bonds zone from above-mentioned these second weld pads, and above-mentioned reseting put line layer and had a plurality of the 3rd weld pads that are positioned at above-mentioned wire bonds zone; And
Second protective layer is covered in above-mentioned reseting and puts on the line layer, and wherein above-mentioned second protective layer has a plurality of second openings, to expose above-mentioned these first weld pads and above-mentioned these the 3rd weld pads.
4. have the stack type chip package structure of switch-over soldering pad on the interior pin of a lead frame, it is characterized in that comprising:
Lead frame, formed by the interior pin group of a plurality of relative arrangements, a plurality of outer pin group and chip bearing, the said chip bearing is arranged between the interior pin group of above-mentioned a plurality of relative arrangements and with the interior pin group of above-mentioned a plurality of relative arrangements and forms difference in height, is also optionally formed a plurality of metal pads on insulating layer coating and the above-mentioned insulating barrier on the local location of pin in above-mentioned;
The multi-chip migration stack architecture is formed by a plurality of chip stacks, and above-mentioned multi-chip migration stack architecture is arranged on the said chip bearing and with the interior pin group of above-mentioned a plurality of relative arrangements and forms electrical connection; And
Packaging body coats above-mentioned multi-chip migration stack architecture and above-mentioned lead frame, and above-mentioned a plurality of outer pin groups stretch out in outside the above-mentioned packaging body;
Comprise at least one frame that confluxes in the wherein above-mentioned lead frame, be arranged between the interior pin group and said chip bearing of above-mentioned a plurality of relative arrangements.
5. have the stack type chip package structure of switch-over soldering pad on the interior pin of a lead frame, it is characterized in that comprising:
Lead frame, formed by the interior pin group of a plurality of relative arrangements, a plurality of outer pin group and chip bearing, the said chip bearing is arranged between the interior pin group of above-mentioned a plurality of relative arrangements and with the interior pin group of above-mentioned a plurality of relative arrangements and forms difference in height, is also optionally formed a plurality of metal pads on insulating layer coating and the above-mentioned insulating barrier on the local location of pin in above-mentioned;
The multi-chip migration stack architecture is formed by a plurality of chip stacks, and above-mentioned multi-chip migration stack architecture is arranged on the said chip bearing and with the interior pin of above-mentioned a plurality of relative arrangements and forms electrical connection;
Packaging body coats above-mentioned a plurality of semiconductor chiop and above-mentioned lead frame, and above-mentioned a plurality of outer pins stretch out in outside the above-mentioned packaging body; And
At least one frame that confluxes be arranged between the interior pin group and said chip bearing of above-mentioned a plurality of relative arrangements, and the above-mentioned frame that confluxes is formed with a plurality of metal segments.
6. have the stack type chip package structure of switch-over soldering pad on the interior pin of a lead frame, it is characterized in that comprising:
Lead frame, formed by the interior pin group of a plurality of relative arrangements, a plurality of outer pin group and chip bearing, the said chip bearing is arranged between the interior pin group of above-mentioned a plurality of relative arrangements and with the interior pin group of above-mentioned a plurality of relative arrangements and forms difference in height, is also optionally formed a plurality of metal pads on insulating layer coating and the above-mentioned insulating barrier on the local location of pin in above-mentioned;
Multi-chip migration stack architecture system is formed by a plurality of chip stacks, and above-mentioned multi-chip migration stack architecture is arranged on the said chip bearing and with the interior pin of above-mentioned a plurality of relative arrangements and forms electrical connection;
Packaging body coats above-mentioned a plurality of semiconductor chiop and above-mentioned lead frame, and above-mentioned a plurality of outer pins stretch out in outside the above-mentioned packaging body; And
At least one frame that confluxes is arranged between the interior pin and said chip bearing of above-mentioned a plurality of relative arrangements, is also optionally formed a plurality of metal pads on insulating layer coating and the above-mentioned insulating barrier on the above-mentioned frame that confluxes.
7. have the stack type chip package structure of switch-over soldering pad on the interior pin of a lead frame, it is characterized in that comprising:
Lead frame is made up of the interior pin group and the chip bearing of a plurality of outer pin groups, a plurality of relative arrangements, and wherein the said chip bearing is arranged between the interior pin group of above-mentioned a plurality of relative arrangements, and forms difference in height with the interior pin group of above-mentioned a plurality of relative arrangements;
A plurality of multi-chip migration stack architectures are arranged on the said chip bearing and with the interior pin group of above-mentioned a plurality of relative arrangements and form electrical connection; And
Packaging body coats above-mentioned a plurality of multi-chip migration stack architecture and above-mentioned lead frame, and above-mentioned a plurality of outer pin groups stretch out in outside the above-mentioned packaging body;
Also optionally formed a plurality of metal pads on insulating layer coating and the above-mentioned insulating barrier on the local location of the interior pin in the wherein above-mentioned lead frame.
8. encapsulating structure according to claim 7 is characterized in that further comprising at least one frame that confluxes in the above-mentioned lead frame, is arranged between the interior pin group and said chip bearing of above-mentioned a plurality of relative arrangements.
9. encapsulating structure according to claim 8 is characterized in that the above-mentioned frame that confluxes is formed with a plurality of metal segments
10. have the stack type chip package structure of switch-over soldering pad on the interior pin of a lead frame, it is characterized in that comprising:
Lead frame, formed by the interior pin group of a plurality of relative arrangements, a plurality of outer pin group and chip bearing, the said chip bearing is arranged between the interior pin group of above-mentioned a plurality of relative arrangements and with the interior pin group of above-mentioned a plurality of relative arrangements and forms difference in height, is also optionally formed a plurality of metal pads on insulating layer coating and the above-mentioned insulating barrier on the local location of pin in above-mentioned;
A plurality of multi-chip migration stack architectures are arranged on the said chip bearing and with the interior pin group of above-mentioned a plurality of relative arrangements and form electrical connection;
Packaging body coats above-mentioned a plurality of semiconductor chiop and above-mentioned lead frame, and above-mentioned a plurality of outer pins stretch out in outside the above-mentioned packaging body; And
At least one frame that confluxes is arranged between the interior pin and said chip bearing of above-mentioned a plurality of relative arrangements, is also optionally formed a plurality of metal pads on insulating layer coating and the above-mentioned insulating barrier on the above-mentioned frame that confluxes.
11. have the conducting wire frame structure of switch-over soldering pad in one kind on the pin, formed by a plurality of interior pin group of relative arrangement, a plurality of outer pin group and chip bearings of being, the said chip bearing is arranged between the interior pin group of above-mentioned a plurality of relative arrangements and with the interior pin group of above-mentioned a plurality of relative arrangements and forms difference in height, it is characterized in that
The pin part is optionally formed a plurality of metal pads on insulating layer coating and the above-mentioned insulating barrier in above-mentioned.
12. conducting wire frame structure according to claim 11 is characterized in that further comprising at least one frame that confluxes, and is arranged between the interior pin and said chip bearing of above-mentioned a plurality of relative arrangements.
13. conducting wire frame structure according to claim 11 is characterized in that also optionally being formed a plurality of metal pads on insulating layer coating and the above-mentioned insulating barrier on the above-mentioned frame that confluxes.
14. encapsulating structure according to claim 11 is characterized in that above-mentioned frame and copline of said chip bearing formation of confluxing.
15. encapsulating structure according to claim 11 is characterized in that above-mentioned conflux frame and interior pin group form a copline.
16. encapsulating structure according to claim 11 is characterized in that the above-mentioned frame that confluxes forms difference in height with the interior pin group and the said chip bearing of above-mentioned a plurality of relative arrangements.
17. encapsulating structure according to claim 11 is characterized in that the above-mentioned frame that confluxes is annular arrangement.
18. encapsulating structure according to claim 11 is characterized in that the above-mentioned frame that confluxes is a stripe-arrangement.
19. a stacking-type chip encapsulation construction comprises:
Lead frame, constituted by pin in a plurality of and a plurality of outer pin, pin includes a plurality of first parallel interior pin groups and the second parallel interior pin group in above-mentioned, pin group's end is with relative arrangements at interval in the pin group and second in above-mentioned first, and the above-mentioned first interior pin group has heavy interposed structure and forms the above-mentioned first interior pin group's terminal position and the above-mentioned second interior pin group's terminal position has different vertical heights;
Multi-chip stack structure is fixed on the above-mentioned first interior pin group, and above-mentioned multi-chip stack structure is electrically connected pin group in the pin group and above-mentioned second in the metal bond pad on the edge, the same side and above-mentioned first by many strip metals lead; And
Sealant coats above-mentioned multi-chip stack structure and above-mentioned a plurality of interior pin, and above-mentioned a plurality of outer pins stretch out in outside the above-mentioned sealant;
It is characterized in that:
Pin group's terminal vicinity in the pin group or the second interior pin group or the above-mentioned first interior pin group and second in above-mentioned first, the part is optionally formed a plurality of metal pads on insulating layer coating and the above-mentioned insulating barrier.
20. encapsulating structure according to claim 19 is characterized in that the end of pin group in above-mentioned second also has recessed approximate hierarchic structure.
21. encapsulating structure according to claim 19 is characterized in that the also lobed approximate hierarchic structure of end of pin group in above-mentioned second.
22. conducting wire frame structure, constituted by pin in a plurality of and a plurality of outer pin, pin includes a plurality of first parallel interior pin groups and the second parallel interior pin group in above-mentioned, the pin group and the second interior pin group's end is with a relative arrangement at interval in above-mentioned first, the pin group has heavy interposed structure and the terminal position that forms pin group in above-mentioned first has different vertical heights with the above-mentioned second interior pin group's terminal position in above-mentioned first, it is characterized in that:
Pin group's terminal vicinity in the pin group or the second interior pin group or the above-mentioned first interior pin group and second in above-mentioned first, the part is optionally formed a plurality of metal pads on insulating layer coating and the above-mentioned insulating barrier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101450896A CN100505247C (en) | 2006-12-01 | 2006-12-01 | Stack type chip package structure with wire frame inner pin installed with metal welding pad |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101450896A CN100505247C (en) | 2006-12-01 | 2006-12-01 | Stack type chip package structure with wire frame inner pin installed with metal welding pad |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101192599A true CN101192599A (en) | 2008-06-04 |
| CN100505247C CN100505247C (en) | 2009-06-24 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006101450896A Active CN100505247C (en) | 2006-12-01 | 2006-12-01 | Stack type chip package structure with wire frame inner pin installed with metal welding pad |
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| CN (1) | CN100505247C (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102224586A (en) * | 2008-09-25 | 2011-10-19 | Lg伊诺特有限公司 | Structure and manufacture method for multi-row lead frame and semiconductor package |
| CN101604684B (en) * | 2008-06-13 | 2012-02-08 | 南茂科技股份有限公司 | Staggered and stacked chip-packaging structure of lead frame with switching bonding pad on inner pins |
| WO2013155681A1 (en) * | 2012-04-18 | 2013-10-24 | Sandisk Semiconductor (Shanghai) Co., Ltd. | Slope die stack |
| CN106128742A (en) * | 2016-07-14 | 2016-11-16 | 重庆理工大学 | The connection method for packing of pin in a kind of SMD magnetic elements |
-
2006
- 2006-12-01 CN CNB2006101450896A patent/CN100505247C/en active Active
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101604684B (en) * | 2008-06-13 | 2012-02-08 | 南茂科技股份有限公司 | Staggered and stacked chip-packaging structure of lead frame with switching bonding pad on inner pins |
| CN102224586A (en) * | 2008-09-25 | 2011-10-19 | Lg伊诺特有限公司 | Structure and manufacture method for multi-row lead frame and semiconductor package |
| CN102224586B (en) * | 2008-09-25 | 2013-12-11 | Lg伊诺特有限公司 | Structure and manufacture method for multi-row lead frame and semiconductor package |
| US8659131B2 (en) | 2008-09-25 | 2014-02-25 | Lg Innotek Co., Ltd. | Structure for multi-row lead frame and semiconductor package capable of minimizing an under-cut |
| WO2013155681A1 (en) * | 2012-04-18 | 2013-10-24 | Sandisk Semiconductor (Shanghai) Co., Ltd. | Slope die stack |
| CN106128742A (en) * | 2016-07-14 | 2016-11-16 | 重庆理工大学 | The connection method for packing of pin in a kind of SMD magnetic elements |
| CN106128742B (en) * | 2016-07-14 | 2018-07-03 | 重庆理工大学 | The connection packaging method of pin in a kind of patch type magnetic elements |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100505247C (en) | 2009-06-24 |
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