CN202548579U - Antenna digital control device based on DSP (digital signal processor) - Google Patents

Abstract

The utility model relates to an antenna digital control device based on an DSP (digital signal processor) which comprises an FPGA module, an interface module, an A/D conversion module and a DSP module, wherein the DSP module comprises a DSP chip, an extended Flash memory and an extended SDRAM, the DSP chip is connected with the extended Flash memory, the extended SDRAM and the A/D conversion module, and further bi-directionally connected with the FPGA module; the FPGA module is bi-directionally connected with an upper computer and an antenna driving unit through the interface module, meanwhile, the FPGA module is also connected with the A/D conversion module. The antenna digital control device has fast calculation speed, possesses strong data processing ability, and can adapt to various complicated algorithms. In addition, a highly integrated design of an antenna servo controller is realized, and meanwhile, the antenna digital control device has strong flexibility, thereby being convenient for system upgrading.

Description

A kind of antenna digital control device based on DSP

Technical field

The utility model relates to a kind of antenna digital control device based on DSP, is used for the High Accuracy Control to antenna servo system.

Background technology

Antenna servo system is an ingredient important in the telemetry system; It mainly acts on is when target gets in the visual line of sight; Make receiving antenna search for and catch target automatically; Tracking accuracy Continuous Tracking target with certain is near the center line of main beam target all the time, thereby receives telesignalisation reliably continuously with maximum receiving gain.Particularly ought break down, when target departs from predetermined flight track, antenna servo system can be in the scope of big spatial domain the line trace of going forward side by side of code acquisition target, obtain important telemetry with failure judgement.In Tracking Through Telemetry equipment, the superiority of digital servosystem is obvious day by day.

Existing antenna controller is divided into analog controller and digitial controller two big classes.Because analog controller is difficult to realize the control algolithm of more complicated, be difficult to satisfy the needs of antenna servo system High Accuracy Control, so digitial controller is an inevitable choice.The advantage of digitial controller shows: parameter modification is convenient, can realize complicated controller algorithm, can satisfy the requirement of High Accuracy Control.Digitial controller is fit to integratedly in addition, and modular design is dwindled with respect to its volume of analog controller greatly, and power consumption obviously reduces, and this haves a great attraction for AEROSPACE APPLICATION.The update of system is more easy owing to only relate to software in addition.

Chinese patent ZL201020697906.0 discloses a kind of integrated antenna digital control device based on the NIOSII microprocessor; The antenna digital control device of this structure mainly is the computing system of realizing with the built-in NIOSII microprocessor core of FPGA; Though it has overcome the many shortcomings of Peripheral Interface; But its arithmetic speed is slow, is difficult to the dealing with complicated algorithm, also inapplicable to the demanding occasion of real-time.

The utility model content

The utility model technology is dealt with problems: overcome the deficiency of prior art, a kind of antenna digital control device based on DSP is provided, improved the real-time of antenna servo system, further improve the performance of entire antenna servo-drive system.

The technical solution of the utility model: based on the antenna digital control device of DSP, its characteristics are to comprise: FPGA module, interface module, A/D modular converter and DSP module; Said DSP module comprises that dsp chip, first extends out Flash storer and first and extends out SDRAM; Said dsp chip extends out Flash storer, first and extends out SDRAM and be connected with the A/D modular converter with first respectively, and said dsp chip also is connected with the FPGA module is two-way simultaneously; Said FPGA module is connected with the antenna driver element is two-way with host computer through interface module, and the FPGA module also is connected with the A/D modular converter simultaneously.

Said FPGA module comprises that fpga chip, configuring chip, second extend out Flash storer and second and extend out SDRAM; Said fpga chip extends out Flash storer and second with configuring chip, second respectively and extends out SDRAM and be connected, and is connected with dsp chip is two-way simultaneously.

Said interface module is made up of the PCI bridging chip.

Said A/D modular converter comprises A/D conversion chip and multichannel selection chip composition; The A/D conversion chip is connected with dsp chip with the FPGA module respectively, and multichannel selects chip to be connected with dsp chip.

Said dsp chip is the floating type dsp chip, can adopt the DSPTMS320C6000 series of American TI Company.

The embedded NIOS II of said fpga chip microprocessor is convenient to the function expansion and the upgrading of system; Fpga chip adopts the Stratix family chip of U.S. altera corp.

The principle of the utility model: the dsp chip fast operation, as the rear end of data processing, mainly be responsible for algorithm process; The fpga chip pin is numerous, possesses abundant peripheral hardware resource, as the front end of data processing; Be that data message is at first gathered through FPGA; After handled is done in FPGA inside, deliver to DSP and do further processing, the data after DSP handles are also delivered to FPGA, outwards send through FPGA.FPGA connects the two-way serial ports and is used to gather antenna position information and duplexer amount signal; Receiver signal and push rod signal are delivered to FPGA through the AD module; Wherein receiver and push rod signals sampling are controlled by DSP; Push button signalling, time code signal are also delivered to FPGA and are carried out handled; The control information of host computer and the monitor message of antenna controller are all transmitted through cpci bus, and antenna controller has been reserved, and the two-way serial interface can receive the digital received machine information and three road serial interfaces can receive three tunnel inertial navigation information.Utilize the every 10ms of timer to produce a look-at-me among the DSP.After the timing interruption generating, antenna controller is gathered antenna position information, receiver signal, push rod signal, push button signalling, time code signal, and the steering order that issues according to host computer; Select corresponding work mode; Like comprehensive tracking, from motion tracking, and then select the control corresponding algorithm to generate controlled quentity controlled variable, like low elevation angle algorithm, Fuzzy PID; Pass to the antenna driver element through serial ports then, thereby realize High Accuracy Control antenna servo system.

The utility model advantage compared with prior art is:

(1) the utility model adopts the mode of DSP and FPGA combination to realize the high-precision digital control to antenna servo system; Improved the processing speed of antenna servo control device to a great extent; Improve the real-time of antenna servo system, further improved the performance of entire antenna servo-drive system.

(2) the utility model adopts DSP to handle and FPGA assist control in addition; Not only solved the not enough shortcoming of dsp interface, done Peripheral Interface control with CPLD simultaneously and compare, can examine by embedded NIOSII; Can combine to realize double-core control with DSP, be convenient to the upgrading expansion of this ACU antenna control unit.

(3) DSP of the utility model employing is high performance floating type digital signal processor; Fast operation; Clock frequency can reach 225MHZ, and single clock cycle can be carried out 8 instructions, and possesses jumbo on-chip memory and large-scale addressing capability; The greatly real-time requirement of satisfying antenna servo system of degree, the control accuracy of raising antenna servo system.

(4) the utility model adopts the front end of FPGA as the DSP data processing, has overcome the not enough shortcoming of DSP Peripheral Interface, has satisfied system for the numerous demand of Peripheral Interface, makes the integrated level of system further improve.Some data can only be handled in FPGA simultaneously, have reduced the operating pressure of DSP, make DSP can focus on algorithm data, give full play to the performance of DSP.

(5) this utility model has realized digitizing, the modularization, integrated of system; And FPGA can be through generating the demand that different NIOS II microprocessors satisfies system's different peripheral on the basis that does not change circuit design; Be convenient to the upgrading and the function expansion of system, realized High Accuracy Control antenna servo system.

Description of drawings

Fig. 1 is the structure composition frame chart of the utility model;

Fig. 2 is the control principle block diagram of the utility model;

Fig. 3 is the DSP module and the FPGA module connection layout of the utility model;

Fig. 4 is the change-over circuit of the A/D modular converter of the utility model;

Fig. 5 is for extending out the SDRAM synoptic diagram in the DSP module of the utility model;

Fig. 6 is for extending out Flash storer synoptic diagram in the DSP module of the utility model;

Fig. 7 is the PCI bridging chip circuit of the utility model;

Fig. 8 is the control flow chart of the DSP inside modules of the utility model.

Embodiment

As shown in Figure 1, the hardware module of the utility model mainly is made up of DSP module 11, FPGA module 3, interface module 5, A/D modular converter 9.Wherein DSP module 11 comprises that dsp chip 10, first extends out Flash storer 12, first and extends out SDRAM13; FPGA module 3 comprises that fpga chip 2, configuring chip 16, second extend out Flash storer 14, second and extend out SDRAM15; Interface module 5 is made up of PCI bridging chip 6; A/D modular converter 9 comprises multichannel selection chip 8 and A/D conversion chip 7.

The control command that host computer 4 issues is passed to fpga chip 26 times through the PCI bridging chip; And then give DSP module 11; The various monitor messages that dsp chip 10 in the DSP module 11 sends are delivered to fpga chip 2; And then report host computer 4, and be presented on the monitoring interface of host computer 4 through PCI bridging chip 6.Multichannel selects chip 8 to select wherein a tunnel sending in the A/D conversion chip 7 in the azimuth information of AGC signal, azimuth error signal, pitch error signal and the push rod of first receiver to the, four receivers, the pitching information; Control the initial of A/D conversion by dsp chip 10,12 bit digital information behind the EOC are sent in the fpga chip 2.Fpga chip 2 can embedded NIOS II microprocessor, cooperates second to extend out Flash storer 14 and second and extend out SDRAM storer 15, has constituted a powerful embedded processor system, is convenient to the function expansion and the upgrading of system.Receiver signal, push rod signal, push button signalling, time code signal are delivered to fpga chip 2 pre-service, and then deliver to DSP module 11 and do further processing.Dsp chip 10 utilizes fpga chip 2 to receive steering order and the information of antenna driver element 1 through defeated antenna pedestal angle information, switching value information and power amplifier self of difference string oral instructions that host computers 4 issue through PCI bridging chip 6, through sticking with paste the High Accuracy Control of mould pid control algorithm realization to antenna pedestal.

As shown in Figure 2; Provided the control principle of the utility model; DSP module 11 combines the detection of FPGA module 3 control time-code information, receiver information, push rod information and key information, and generates certain controlled quentity controlled variable according to the control signal that host computer 4 issues, and is transferred to antenna driver element 1 through the RS422 serial ports; Antenna driver element 1 generates the Control current drive motor according to this controlled quentity controlled variable and rotates, thereby realizes the High Accuracy Control of antenna servo system.

As shown in Figure 3; Dsp chip 10 and fpga chip 2 connection layout for the utility model; The data line of dsp chip 10 and address wire and control line all are connected on the fpga chip 2; Be that dsp chip 10 links to each other with the EMIF interface of fpga chip 2 through dsp chip 10, fpga chip 2 is equivalent to the external memory storage of dsp chip 10 here, can be configured in fpga chip 2 the CE2 space or the CE3 space of dsp chip 10.The GPIO interface of dsp chip 10 also links to each other with fpga chip 2 in addition, is used for fpga chip 2 on the one hand and sends look-at-me and switching signal to dsp chip 10, for the expansion of fpga chip 2 functions surplus is provided on the other hand.

As shown in Figure 4, be the A/D modular converter 9 of the utility model.That the modulus conversion chip of the utility model adopts is the AD1674 of AD company, and this chip has the sampling rate of 12 precision, 10us, can support ± 5V, ± input voltage range of 10V, 0～10V, 0～20V.Multichannel selects chip 8 to select the DG406 of MAXIM company for use, and this chip support is selected 1 operation to 16 of input signal.Connect through chip OP37 between the two, satisfied the demand of system acquisition receiver signal and push rod signal fully.The beginning of the selection of signal and A/D conversion is by 11 controls of DSP module, and 12 bit digital information of AD1674 output are delivered to FPGA2 behind the A/D EOC.

Like Fig. 5, shown in 6,, the DSP module 11, first of the utility model extends out SDRAM13 for extending out Flash storer 12 and first.Wherein a SDRAM13 is mapped to the CE0 space of dsp chip 10; For first extend out SDRAM13 operation if the configuration corresponding EMIF the CE0 space on each controller; Read and write first then when extending out SDRAM13, only need read and write and get final product according to the general memory mode; Because system application operates on SDRAM or the SRAM; The power down meeting is lost; Therefore need external first to extend out Flash storer 12; First extend out the CE1 space that Flash storer 12 is mapped to DSP here, when system powered at every turn, the Flash program was loaded among the first memory SDRAM13 and moves.FPGA module 3 has also extended out second and has extended out Flash storer 14 and second memory SDRAM15, under the needs situation so that the little processing of embedded NIOS II realizes the double-core control of entire controller.

As shown in Figure 7, the PCI bridging chip 6 of the utility model has been selected PCI9054 for use.PCI9054 is the pci bus interface chip that U.S. PLX company produces, and it satisfies PCI V2.2 agreement, supports 32 33MHz clock pci buss, is specially adapted to the exploitation of pci bus peripheral product.PCI9054 adopts leading data pipeline framework (the Data Pipe Architecture) technology of PLX, is equipped with DMA engine, direct master control able to programme and immediate subordinate data transmission and PCI information transfer capability.PCI9054 has three equipment local bus options: M pattern, C pattern and J pattern.The utility model has adopted PCI9054 local bus J pattern.

The control flow of DSP inside is as shown in Figure 8: dsp chip 10 inside at first are provided with interrupt system; Simultaneously also to carry out initialization design to the whole procedure flow process; After initialization is accomplished; The timing that gets into a 10ms is interrupted, and the general data of dsp chip 10 is handled and accomplished in break period at this 10ms, in interrupt routine; Dsp chip 10 reads the control information that fpga chip 2 sends host computer 4; Carry out the selection of mode of operation (manually, from motion tracking) again according to the control information of host computer 4, and carry out the controlled quentity controlled variable that control corresponding algorithm (like the fuzzy algorithm) calculates antenna driver element 1 and deliver to fpga chip 2, fpga chip 2 sends to antenna driver element 1 to controlled quentity controlled variable through the RS422 serial ports.Dsp chip 10 is in giving fpga chip 2 back entering interruption determining programs controlled quentity controlled variable.

The utility model provides enough hardware resource and advanced control algolithm, can satisfy the demand of high-precision antenna servo-drive system, and in antenna servo system, have certain versatility.

Claims (8)

1. the antenna digital control device based on DSP is characterized in that comprising: FPGA module (3), interface module (5), A/D modular converter (9) and DSP module (11); Said DSP module (11) comprises that dsp chip (10), first extends out Flash storer (12) and first and extends out SDRAM (13); Said dsp chip (10) extends out Flash storer (12), first and extends out SDRAM (13) and be connected with A/D modular converter (9) with first respectively, simultaneously said dsp chip (10) also with two-way connection of FPGA module (3); Said FPGA module (3) is through interface module (5) and host computer (4) and two-way connection of antenna driver element (1), and FPGA module (3) also is connected with A/D modular converter (9) simultaneously.

2. the antenna digital control device based on DSP according to claim 1 is characterized in that: said FPGA module (3) comprises that fpga chip (2), configuring chip (16), second extend out Flash storer (14) and second and extend out SDRAM (15); Said fpga chip (2) extends out Flash storer (14) and second with configuring chip (16), second respectively and extends out SDRAM (15) and be connected, simultaneously and two-way connection of dsp chip (10).

3. the antenna digital control device based on DSP according to claim 1 is characterized in that: said interface module (5) is made up of PCI bridging chip (6).

4. the antenna digital control device based on DSP according to claim 1 is characterized in that: said A/D modular converter (9) comprises A/D conversion chip (7) and multichannel selection chip (8) composition; A/D conversion chip (7) is connected with dsp chip (10) with FPGA module (3) respectively, and multichannel selects chip (8) to be connected with dsp chip (10).

5. the antenna digital control device based on DSP according to claim 1 is characterized in that: said dsp chip (10) is the floating type dsp chip.

6. the antenna digital control device based on DSP according to claim 2 is characterized in that: the embedded NIOS II of said fpga chip (2) microprocessor, be convenient to the function expansion and the upgrading of system.

7. according to claim 1 or 5 described antenna digital control device based on DSP, it is characterized in that: said dsp chip (10) adopts the DSP TMS320C6000 series of American TI Company.

8. the antenna digital control device based on DSP according to claim 2 is characterized in that: said fpga chip (2) adopts the Stratix family chip of U.S. altera corp.

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