CN103195407B - Signal processing device for range finding radar for drilling detecting layers of horizontal wells - Google Patents
Signal processing device for range finding radar for drilling detecting layers of horizontal wells Download PDFInfo
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Abstract
The invention discloses a signal processing device for range finding radar for drilling detecting layers of horizontal wells. The signal processing device can acquire and process high-frequency electromagnetic signals in real time in an underground drilling procedure, time-domain and frequency-domain feature information of echo signals which are acquired after the high-frequency electromagnetic signals are processed can be subjected to correlation solving, distances from a tool face to the top and the bottom of a reservoir can be computed, and data of the computed distances further can be transmitted to the ground via a wireless electromagnetic signal channel by the aid of an insulating dipole transmitting unit. The signal processing device is mainly applicable to detecting thicknesses of oil layers, coal beds and other reservoirs in drilling procedures, the received high-frequency electromagnetic signals are sampled and processed in real time in the drilling procedure, and accordingly the signal processing device implements one of core technologies of the range finding radar for the drilling detecting layers of the horizontal wells.
Description
Technical field
The invention belongs to geological exploration field, be specifically related to a kind of for the signal processing apparatus of horizontal well with probing layer range radar.
Background technology
Along with the development of petroleum industry and the continuous increase of oil-gas exploration and development difficulty, petroleum exploration and development industry turns to the oil-gas reservoir that exploitation scale is little, oil-gas Layer is thin, poor properties, non-homogeneity are strong gradually, and the application of the special well such as directional well, horizontal well increases year by year.In the work progress of these special wells, the formation characteristics needing grasp drill bit in time to drill, quick and precisely find reservoir, thus guiding construction personnel control drill bit runs in the guide in reservoir all the time, to improve recovery ratio to greatest extent.
For ensureing that drill bit creeps into all the time in reservoir, just needing the up-and-down boundary face of measurement while drilling reservoir, ensureing that drill bit is in the optimum position in reservoir.But, in actual creeping into, due to the limitation of existing testing tool, often occur that drill bit drills reservoir, or the optimum position in reservoir can not be remained on, have impact on the recovery ratio of the resource such as Drilling ratio and oil gas of reservoir.
For ensureing that visiting layer range radar has enough certainties of measurement, requires that the wavelength of the electromagnetic wave signal launched is short as far as possible.If precision is decided to be 10cm, then wavelength X≤the 40cm transmitted, then by electromagnetic wave spread speed v ≈ 1 × 10 in the earth formation
8m/s, according to
the broadband narrow pulse signal centre frequency f launched can be obtained
c>=250MHz.For ensureing that energy major part can be launched by broadband narrow pulse signal, then ultra-wideband antenna should be adopted, namely
wherein f
h, f
lbe respectively power compared with corresponding high frequency points during peak power decline 10dB and low frequency.If setting f
h=300MHz, f
l=200MHz, according to nyquist sampling law, sample frequency should be not less than 2 times that are sampled frequency, thus sample frequency f
s>=2f
h=600MHz.So, visit layer range radar system very high to hardware requirement, sufficiently high sample frequency be had, meanwhile, more will have enough data processing speeds.
U.S. Patent application 7013991 discloses a kind of mode solved the problem, the echo-signal that radar system receives by this patent is directly sent to ground host machine in real time by the mode of wire transmission, and ground host machine carries out Digital Signal Processing in real time to high-frequency signal.
But consider the factor such as economy, practicality, the underground survey data transfer mode adopted both at home and abroad is at present commonly wireless transmission method, relies on mud-pulse and low-frequency electromagnetic wave etc., the speed of transmission data is comparatively slow, is only a few Hz ~ tens Hz.In system, the data volume of radar transmissions is very large, and system is very high to requirement of real-time, and so low transfer rate cannot meet sampling and the processing requirements of radar system, data can not be sent to ground, at the enterprising row relax of ground host machine.Therefore, necessarily require to process the data collected in real time in down-hole, the data handled well are passed to ground again.
Summary of the invention
For the problems referred to above, the object of the present invention is to provide a kind of horizontal well with the signal processing apparatus of probing layer range radar.In downhole drill process, this signal processing apparatus can realize carrying out Real-time Collection to high frequency electromagnetic wave signal and processing, the time domain of echo-signal obtain process and the characteristic information of frequency domain carry out relevant resolving, calculate the end face of tool-face and reservoir and the distance of bottom surface, then by insulation dipole emission unit, the range data calculated can be passed through wireless electromagnetic transmission to ground.
To achieve these goals, the invention provides following technical scheme:
Horizontal well is with a signal processing apparatus for probing layer range radar, and the main body of described device comprises: high-speed a/d sampling unit, digital signal processing unit DSP and FPGA, and high speed synchronous memory SDRAM; Described high-speed a/d sampling unit, the echo reception unit formed with reception antenna and preamplifier is connected, and samples to high frequency echo signal, the sample frequency f of A/D sampling unit
s>=600MHz.
Described device characteristic carries out real-time sampling and process in down-hole to echo-signal, the upper and lower interface of reservoir is calculated in down-hole, without the need to data wired or alternate manner are passed to the laggard row relax in ground, only need by the range data after handling well with the speed of a few Hz by being wirelessly transmitted to ground host machine.
Wherein, described digital signal processing unit FPGA is connected with high-speed a/d sampling unit, and carry out pretreatment to the signal after sampling, carry out simple algorithm process, described algorithm process comprises Fourier transformation; Described digital signal processing unit FPGA internal logic control unit is connected with host computer ARM, and wait for the open and close of ARM instruction control A/D sampling unit, described logic control element is connected with DSP, for interrupting DSP signal, to DSP feedback information simultaneously; Address bus, data/address bus are connected with DSP with control bus, carry out parallel communications, by pretreated data stored in RAM, call for DSP.
Wherein, described digital signal processing unit DSP is connected with digital signal processing unit FPGA, data/address bus is connected with the RAM of address bus with digital signal processing unit FPGA, carry out parallel communications, control bus control FPGA, carries out collaborative work, calls the pretreated data of FPGA, extract the characteristic information on the time domain of echo-signal and frequency domain further by series of algorithms, eventually pass the up-and-down boundary face that algorithm calculates antenna place plane and reservoir and obtain range information; Described digital signal processing unit DSP is connected with high speed synchronous memory SDRAM, wherein between DSP and SDRAM, transmission means is Ping_pong Double buffer mode, realize carrying out not affecting the process of CPU to data in the process that EDMA moves data, described digital signal processing unit DSP is connected with host computer ARM, transmits the reservoir upper and lower interface range data processing and obtain to host computer.
Wherein, described high speed synchronous memory SDRAM and DSP is connected, and in order to store the buffered data of DSP in calculating process, and stores the result after computing.
Beneficial effect
Beneficial effect of the present invention is: adopt DSP can make full use of DSP and FPGA feature separately in conjunction with FPGA framework, be applicable to the real-time process of downhole data, need not adopt the modes such as wire transmission that a large amount of initial data is passed to the enterprising row relax in ground.
Accompanying drawing explanation
A kind of horizontal well that Fig. 1 provides for the embodiment of the present invention is with the structured flowchart of the signal processing apparatus of probing layer range radar;
A kind of horizontal well that Fig. 2 provides for the embodiment of the present invention is with the overall soft flow chart of the signal processing apparatus of probing layer range radar.
Wherein, 1 is reception antenna, and 2 is preamplifiers, and 3 is high-speed a/d sampling units, 4 is digital signal processing unit FPGA, and 5 is host computer ARM, and 6 is rotational angle detection unit, 7 is insulation dipole emission unit, and 8 is digital signal processing unit DSP, and 9 is storage unit in high speed SDRAM.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
As shown in Figure 1, reception antenna 1 receives the faint electromagnetic wave echo-signal that reservoir and cap interface produce, and carries out enlarge leadingly with small signal amplifier 2 to the weak electromagnetic ripple signal received; Rotational angle detection unit detect antenna place plane be directly over or immediately below, namely antenna horizontal plane place angle and ground line place angle be 0 ° or 180 ° time, host computer ARM control unit 5 controls high-speed a/d chip 3 to start to sample to echo, converts the analog signal after amplifying to data signal; Signal after conversion passes to FPGA4, FPGA4 is as the SECO center of whole device and exchanges data bridge, Quick Pretreatment is carried out to bottom data, and pretreated signal is deposited in internal RAM, be connected with DSP8 by data/address bus, address bus and control bus, adopt parallel communications; DSP8 reads through the pretreated data of FPGA4, extracts the characteristic information on the time domain of echo-signal and frequency domain further by series of algorithms, eventually passes the up-and-down boundary face that algorithm calculates antenna place plane and reservoir and obtains range information; In above-mentioned processing procedure, SDRAM9 be used for buffer memory initial data and process after information data, wherein between DSP8 and SDRAM9, transmission means is Ping_pong Double buffer mode, realizes carrying out not affecting the process of CPU to data in the process that EDMA moves data; The range data processed is passed to host computer ARM control unit 5; ARM control unit 5 is encoded to these data, sets up the 2-D data bag of tool face azimuth and distance value, and this signal is entered stratum with electromagnetic mode radiation and is sent to ground by finally control insulation dipole emission unit 7.
As shown in Figure 2, step S201, initializes DSP8 and FPGA4; Step S202, waits for that FPGA4 triggers, and namely waits for the instruction of ARM host computer 5, if receive instruction, then enters next step, otherwise continues to wait for; Step S203, starts high-speed a/d sampling unit 3, starts analog signal sampling; Step S204, FPGA4 and DSP8 process signal simultaneously, comprise the process such as bandpass filtering, background denoising, signal enhancing, the result after process are further resolved again; Step S205, has resolved and has sent out interruption to host computer ARM5; Step S206, if host computer ARM5 receives interrupt signal, then enters next step, otherwise continues to wait for; Step S207, reads the signal after DSP8 process; Step S208, ARM5, to the data encoding received, are sent to ground.
In sum, useful achievement of the present invention is: the present invention proposes the signal processing apparatus of a kind of horizontal well with probing layer range radar.By this device, can realize can completing data processing to signal in down-hole, the up-and-down boundary face of reservoir can be obtained, thus realize visiting layer, range finding effect, drill bit can be controlled in real time and creep in reservoir, ensure that good reservoir Drilling ratio.
Last it is noted that obviously, above-described embodiment is only for the application's example is clearly described, and the restriction not to embodiment.For those of ordinary skill in the field, can also make other changes in different forms on the basis of the above description.Here exhaustive without the need to also giving all embodiments.And thus the apparent change of amplifying out or variation be still among the protection domain of the application's type.
Claims (3)
1. horizontal well is with a signal processing apparatus for probing layer range radar, it is characterized in that: the main body of described device comprises: high-speed a/d sampling unit, digital signal processing unit DSP and FPGA, and high speed synchronous memory SDRAM; Described high-speed a/d sampling unit, the echo reception unit formed with reception antenna and preamplifier is connected, and samples to high frequency echo signal, the sample frequency f of A/D sampling unit
s>=600MHz; Described digital signal processing unit FPGA is connected with high-speed a/d sampling unit, and carry out pretreatment to the signal after sampling, carry out simple algorithm process, described algorithm process comprises Fourier transformation; Described digital signal processing unit FPGA internal logic control unit is connected with host computer ARM, and wait for the open and close of ARM instruction control A/D sampling unit, described logic control element is connected with DSP, for interrupting DSP signal, to DSP feedback information simultaneously; Address bus, data/address bus are connected with DSP with control bus, carry out parallel communications, by pretreated data stored in RAM, call for DSP.
2. signal processing apparatus according to claim 1, it is characterized in that: described digital signal processing unit DSP is connected with digital signal processing unit FPGA, data/address bus is connected with the RAM of address bus with digital signal processing unit FPGA, carry out parallel communications, control bus control FPGA, carry out collaborative work, call the pretreated data of FPGA, extract the characteristic information on the time domain of echo-signal and frequency domain further by series of algorithms, eventually pass the up-and-down boundary face that algorithm calculates antenna place plane and reservoir and obtain range information; Described digital signal processing unit DSP is connected with high speed synchronous memory SDRAM, wherein between DSP and SDRAM, transmission means is Ping_pong Double buffer mode, realize carrying out not affecting the process of CPU to data in the process that EDMA moves data, described digital signal processing unit DSP is connected with host computer ARM, transmits the reservoir upper and lower interface range data processing and obtain to host computer.
3. signal processing apparatus according to claim 1, is characterized in that: described high speed synchronous memory SDRAM and DSP is connected, and in order to store the buffered data of DSP in calculating process, and stores the result after computing.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4814768A (en) * | 1987-09-28 | 1989-03-21 | The United States Of America As Represented By The United States Department Of Energy | Downhole pulse radar |
| EP1436638A2 (en) * | 2001-10-16 | 2004-07-14 | Abraham Jossef | Method and apparatus for signal detection and jamming |
| CN201464643U (en) * | 2009-09-07 | 2010-05-12 | 哈尔滨工程大学科技园发展有限公司 | Radar image acquisition card based on DSP and FPGA |
| CN202217051U (en) * | 2011-06-30 | 2012-05-09 | 桂林电子科技大学 | LFMCW radar system |
| CN202548579U (en) * | 2011-12-29 | 2012-11-21 | 北京遥测技术研究所 | Antenna digital control device based on DSP (digital signal processor) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7013991B2 (en) * | 2003-09-24 | 2006-03-21 | Gas Technology Institute | Obstacle detection system for underground operations |
-
2013
- 2013-04-12 CN CN201310128107.XA patent/CN103195407B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4814768A (en) * | 1987-09-28 | 1989-03-21 | The United States Of America As Represented By The United States Department Of Energy | Downhole pulse radar |
| EP1436638A2 (en) * | 2001-10-16 | 2004-07-14 | Abraham Jossef | Method and apparatus for signal detection and jamming |
| CN201464643U (en) * | 2009-09-07 | 2010-05-12 | 哈尔滨工程大学科技园发展有限公司 | Radar image acquisition card based on DSP and FPGA |
| CN202217051U (en) * | 2011-06-30 | 2012-05-09 | 桂林电子科技大学 | LFMCW radar system |
| CN202548579U (en) * | 2011-12-29 | 2012-11-21 | 北京遥测技术研究所 | Antenna digital control device based on DSP (digital signal processor) |
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