CN202548495U - Array substrate and display device - Google Patents
Array substrate and display device Download PDFInfo
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- CN202548495U CN202548495U CN 201220019092 CN201220019092U CN202548495U CN 202548495 U CN202548495 U CN 202548495U CN 201220019092 CN201220019092 CN 201220019092 CN 201220019092 U CN201220019092 U CN 201220019092U CN 202548495 U CN202548495 U CN 202548495U
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- public electrode
- extension line
- electrode extension
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Abstract
The utility model discloses an array substrate and a display device, and relates to the technical field of LCD (liquid crystal display). The array substrate comprises a common electrode outgoing line, a common electrode routing line and one or multiple repairing lines, wherein the common electrode outgoing line is connected with the common electrode routing line. The array substrate is characterized in that the repairing lines are arranged by surrounding the wiring area of the array substrate, and the repairing lines are connected with the common electrode outgoing line and the common electrode routing line. The array substrate and the display device which are disclosed by the utility model fully utilize idle repairing lines, homogenization of in-plane common voltage signals can be realized, and a line defect repairing function also can be realized.
Description
Technical field
The utility model relates to LCD, and (Liquid Crystal Display, LCD) technical field relates in particular to a kind of array base palte and display device.
Background technology
LCD is a kind of flat-panel screens that is widely used most at present, has characteristics such as low-power consumption, slim body, in light weight and low driving voltage.Generally speaking, comprise a plurality of subpixel area in the viewing area on the LCD array base palte, each subpixel area is generally two grid lines and two data lines and intersects defined rectangular area, is provided with a thin film field-effect pipe (TFT) and a pixel electrode in it.Grid line and data line mainly are to be used to provide signal with the driving pixels electrode.In addition, all need MM CAP to keep the voltage of its pixel electrode in each subpixel area, this MM CAP is usually because public (Common) electrode completion of pixel electrode on same substrate; Therefore; Indispensable, on this substrate, there is a large amount of Common cablings.No matter be that grid line, data line or Common cabling are had in the end and drawn or cause the corresponding drive IC of wiring region from the wiring region of panel; Usually the grid line unification leads to the gate driving IC of panel one side, and the data line unification leads to the not source drive IC of homonymy of gate driving IC.As shown in Figure 1, the Common cabling is dispersed throughout whole viewing area, comprises Common cabling 1-1 parallel with data line and the two Common cabling 1-2 parallel with grid line.The one Common cabling 1-1 is connected with the 2nd Common cabling 1-2; The 2nd Common cabling 1-2 is drawn by panel left side Common extension line 2-1 and/or right side Common extension line 2-2, and left side Common extension line 2-1 is connected with bottom side Common extension line 2-3 with right side Common extension line 2-2.Through the Common extension line each Common cabling in the panel is introduced in the unification of Vcommon signal.Usually, Common cabling and grid line are with layer, and for avoiding crosstalking with grid line and data line generation, the Common extension line should form with corresponding grid line and data line staggered floor.As shown in fig. 1, left side Common extension line 2-1 and data line are with layer, and right side Common extension line 2-2 and grid line are with layer, and bottom Common extension line 2-3 and grid line are with layer.But; There is bigger problem in the power supply mode of this Common cabling: produce voltage drop because the voltage drop that the resistance of Common extension line and cabling self causes makes the Common extension line 2-2 of the inner vertical direction of panel go up, the voltage on same article the one Common cabling 1-1 is not Vcommon entirely.Array base palte bottom is different with the electric current that overhead stream is crossed pixel, and along with the increasing of panel size, Common extension line and cabling on the array base palte elongate gradually, and himself resistance is also obvious day by day accordingly, thereby causes the inhomogeneous of demonstration.
In addition, during owing to making, influences such as just fluctuating of substrate surface, thermal treatment, etching technics, grid line and data line are easy to break, and then cause appearing the generation of defective.And along with the area of panel increases, the raising of resolution needs more grid line of production quantity and data line, makes live width become narrower, causes the raising of technology difficulty, and line defct takes place more easily.In order to improve the product yield, therefore the technology of various reparation circuits just proposes.But in traditional array base palte design shown in Figure 1; The first reparation line R1 and second repairs line R2 (being located in the wiring region of array base palte) and only when panel generation line defct, just can be utilized; Because it is less relatively that the chance of line defct appears in panel; As far as most of panels, repair line and be in idle state, can not be effectively used.
The utility model content
The technical matters that (one) will solve
The technical matters that the utility model will solve is: provide a kind of reparation line capable of using to realize in the face voltage on the Common cabling array base palte and the display device of homogenization more.
(2) technical scheme
For addressing the above problem; The utility model provides a kind of array base palte; Comprise public electrode extension line, public electrode cabling and one or more reparation line, said public electrode extension line links to each other with said public electrode cabling, it is characterized in that; Said reparation line is located in the wiring region of array base palte, and said reparation line links to each other with said public electrode extension line and said public electrode cabling.
Preferably; Said array base palte comprises the first public electrode extension line, the second public electrode extension line and the 3rd public electrode extension line; The first public electrode extension line and the second public electrode extension line are arranged at both sides relative on the said array base palte respectively; Said the 3rd public electrode extension line is arranged at and the first public electrode extension line and the adjacent side of the second public electrode extension line, and the said first public electrode extension line and the second public electrode extension line link to each other with said the 3rd public electrode extension line respectively.
Preferably; Said array base palte comprises many first public electrode cablings that laterally arrange with the said first public electrode extension line; And many second public electrode cablings that laterally arrange with said the 3rd public electrode extension line, the said second public electrode cabling links to each other with the said first public electrode extension line and/or the second public electrode extension line respectively.
Preferably, said array base palte comprises that is repaired a line, and said reparation line links to each other with the said first public electrode extension line and/or the second public electrode extension line.
Preferably, said reparation line links to each other with the said first public electrode cabling.
Preferably, said array base palte comprises that first repairs the line and the second reparation line, and said first repairs line links to each other with the said first public electrode extension line and/or the second public electrode extension line; Said second repairs line links to each other with the said first public electrode extension line and/or the second public electrode extension line.
Preferably, said first reparation line and the said second reparation line link to each other with the said first public electrode cabling respectively.
Preferably, said first reparation line and the said second reparation line are identical with layer and material with grid line.
Preferably; The said first public electrode extension line is identical with layer and material with data line/grid line; The said second public electrode extension line is identical with layer and material with grid line/data line; Said the 3rd public electrode extension line is identical with layer and material with grid line/data line, and the said first public electrode cabling and the second public electrode cabling are all identical with layer and material with grid line.
The utility model also provides a kind of display device, and this device comprises above-mentioned array base palte.
(3) beneficial effect
Array base palte of the utility model and display device make full use of idle reparation line; When line defct takes place when; Reparation radical according to number that line defct takes place and the design of reparation line carries out cut or laser dotting; Both can realize the homogenization of Common voltage signal in the face, can realize the line defct repair function again simultaneously; If more need to utilize of line defct all repaired lines, then repair the function that the line full recovery is repaired line on the traditional sense.
Description of drawings
Fig. 1 is for accordinging to public electrode wire and reparation line synoptic diagram on the traditional array substrate;
Fig. 2 is for accordinging to public electrode wire and reparation line synoptic diagram on the array base palte of a kind of embodiment of the utility model.
Embodiment
Array base palte and display device that the utility model proposes specify as follows in conjunction with accompanying drawing and embodiment.
In this embodiment to comprise that two array base paltes of repairing lines are example.As shown in Figure 2, in this embodiment, be horizontal direction with the direction X parallel with the grid line (not shown), the direction Y parallel with the data line (not shown) is vertical direction.Array base palte according to a kind of embodiment of the utility model comprises: many first public electrodes (Common) the cabling 1-1 of vertical direction, many articles the 2nd Common cabling 1-2, a Common extension line 2-1, the 2nd Common extension line 2-2 and the 3rd Common extension line 2-3 of horizontal direction, at least two reparation lines (in the present embodiment mode are two; Be respectively first and repair the line R1 and the second reparation line R2, but be not limited thereto).Wherein:
The one Common extension line 2-1 is arranged on the left side of substrate; The 2nd Common extension line 2-2 is arranged on a relative side, the i.e. right side of substrate with a Common extension line 2-1; The 3rd Common extension line 2-3 is arranged on substrate bottom side (with a Common extension line 2-1 and the adjacent side of the 2nd Common extension line 2-2), and all links to each other with a Common extension line 2-1 and the 2nd Common extension line 2-2.All the 2nd Common cabling 1-2 all link to each other with the 2nd Common extension line 2-2, and the 2nd Common extension line 2-2 links to each other with the Vcommon signal, thereby the Vcommon signal is introduced in the panel.
First repairs line R1 and second repairs the wiring region that line R2 is located in array base palte; And the first reparation line R1 and second repairs line R2 and links to each other with the 2nd Common extension line 2-2 respectively; The first reparation line R1 and second repairs line R2 and also all links to each other (in this embodiment with a Common cabling 1-1; The first reparation line R1 and second repairs line R2 and realizes being connected through a Common cabling extension line 1-3 and a Common cabling 1-1, and a Common cabling extension line 1-3 all links to each other with every the one Common cabling 1-1, and is arranged at the panel bottom side; Laterally arrange with the 2nd Common cabling 1-2); Like this, the Vcommon signal not only can be introduced by horizontal direction from the 2nd Common cabling 1-2, is also bottom-uply simultaneously introduced from the panel bottom side by a Common cabling extension line 1-3; The Vcommon signal of introducing in the panel does not receive the influence of Common extension line and the pressure drop of Common cabling, thereby makes the Common voltage homogenization more that panel is interior.
In the array base palte of this embodiment, for the convenience for preparing, the first reparation line R1 and second repairs line R2 can be preferably identical with layer and material with grid line.The one Common extension line 2-1 can be identical with layer and material with data line or grid line; The 2nd Common extension line 2-2 can be identical with layer and material with grid line or data line; The 3rd Common extension line 2-3 can be identical with layer and material with grid line, not conflict and be advisable with the position that is provided with of gate driving IC and source drive IC.In this embodiment; The one Common extension line 2-1 is identical with layer and material with data line; The 2nd Common extension line 2-2 is identical with layer and material with grid line; The 3rd Common extension line 2-3 is identical with layer and material with grid line, and a Common cabling extension line 1-3 is identical with layer and material with grid line.
In addition; In the array base palte of this embodiment; The one Common extension line 2-1 and the 2nd Common extension line 2-2 all are connected to the Vcommon signal wire through linkage unit, and linkage unit is made up of tin indium oxide ITO material or other metal material and via hole 3.The 2nd Common extension line 2-2 and the connection completion of repairing between the line through the first linkage unit 4-1; First repairs line R1 directly is connected with the 2nd Common extension line 2-2; Second repairs line R2 accomplished with being connected through the second linkage unit 4-2 (shown in the dotted line circle) of the 2nd Common extension line 2-2; First repairs line R1 directly links to each other with a Common cabling extension line 1-3; Second repairs the completion through the 3rd linkage unit 4-3 (shown in the dotted line circle) that is connected between line R2 and the Common cabling extension line 1-3; Thereby realize the commentaries on classics layer of data line layer and grid line layer; The second linkage unit 4-2 and the 3rd linkage unit 4-3 all on the first reparation line R1, repair between the line R2 reparation line R1 and second that wins and are not connected.
In most of the cases, if there is not line fault, first repairs line R1 and second repairs line R2 respectively directly and pass through the second linkage unit 4-2 and the 2nd Common extension line 2-2 conducting; The first reparation line R1 and second repairs line R2 and directly and through the 3rd linkage unit 4-3 is connected with a Common cabling extension line 1-3 respectively; Then the Vcommon signal can directly be sent into panel inside from the bottom to top through a Common cabling extension line 1-3; Promptly repairing line can use as the Common extension line, increases Vcommon signal internal homogeneity with this.
When line fault takes place: if a line fault is arranged; Can repair line R1 to first and carry out cut laser cutting, or the second linkage unit 4-2 and the 3rd linkage unit 4-3 are carried out laser cutting with being connected of a Common cabling extension line 1-3; If 2 line faults are arranged; Then repair line R1 and carry out aser cutting being connected of a Common cabling extension line 1-3 and the second linkage unit 4-2 and the 3rd linkage unit 4-3 are carried out laser cutting, even first repairs line R1 and the second reparation line R2 returns to traditional reparation line purposes first.
Except that the cut position of above explanation, other need laser dotting could realize that the position of circuit reparation no longer narrates.
The utility model also provides a kind of display device, and this device comprises above-mentioned array base palte.This display device can be any liquid crystal indicators such as LCD, mobile phone and TV, at this not as to the restriction of the utility model.
Above embodiment only is used to explain the utility model; And be not the restriction to the utility model; The those of ordinary skill in relevant technologies field under the situation of spirit that does not break away from the utility model and scope, can also be made various variations and modification; Therefore all technical schemes that are equal to also belong to the category of the utility model, and the scope of patent protection of the utility model should be defined by the claims.
Claims (10)
1. array base palte; Comprise public electrode extension line, public electrode cabling and one or more reparation line; Said public electrode extension line links to each other with said public electrode cabling; It is characterized in that said reparation line is located in the wiring region of array base palte, and said reparation line links to each other with said public electrode extension line and said public electrode cabling.
2. array base palte as claimed in claim 1; It is characterized in that; Said array base palte comprises the first public electrode extension line, the second public electrode extension line and the 3rd public electrode extension line; The first public electrode extension line and the second public electrode extension line are arranged at both sides relative on the said array base palte respectively; Said the 3rd public electrode extension line is arranged at and the first public electrode extension line and the adjacent side of the second public electrode extension line, and the said first public electrode extension line and the second public electrode extension line link to each other with said the 3rd public electrode extension line respectively.
3. array base palte as claimed in claim 2; It is characterized in that; Said array base palte comprises many first public electrode cablings that laterally arrange with the said first public electrode extension line; And many second public electrode cablings that laterally arrange with said the 3rd public electrode extension line, the said second public electrode cabling links to each other with the said first public electrode extension line and/or the second public electrode extension line respectively.
4. array base palte as claimed in claim 3 is characterized in that, said array base palte comprises that is repaired a line, and said reparation line links to each other with the said first public electrode extension line and/or the second public electrode extension line.
5. array base palte as claimed in claim 4 is characterized in that, said reparation line links to each other with the said first public electrode cabling.
6. array base palte as claimed in claim 3 is characterized in that, said array base palte comprises that first repairs the line and the second reparation line, and said first repairs line links to each other with the said first public electrode extension line and/or the second public electrode extension line; Said second repairs line links to each other with the said first public electrode extension line and/or the second public electrode extension line.
7. array base palte as claimed in claim 6 is characterized in that, the said first reparation line and said second is repaired line and linked to each other with the said first public electrode cabling respectively.
8. array base palte as claimed in claim 7 is characterized in that, it is identical with layer and material with grid line that the said first reparation line and said second is repaired line.
9. like each described array base palte of claim 3-8; It is characterized in that; The said first public electrode extension line is identical with layer and material with data line/grid line; The said second public electrode extension line is identical with layer and material with grid line/data line, and said the 3rd public electrode extension line is identical with layer and material with grid line/data line, and the said first public electrode cabling and the second public electrode cabling are all identical with layer and material with grid line.
10. a display device is characterized in that, this device comprises each described array base palte of claim 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220019092 CN202548495U (en) | 2012-01-16 | 2012-01-16 | Array substrate and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220019092 CN202548495U (en) | 2012-01-16 | 2012-01-16 | Array substrate and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202548495U true CN202548495U (en) | 2012-11-21 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220019092 Expired - Lifetime CN202548495U (en) | 2012-01-16 | 2012-01-16 | Array substrate and display device |
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| Country | Link |
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| CN (1) | CN202548495U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109584833A (en) * | 2019-01-21 | 2019-04-05 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
-
2012
- 2012-01-16 CN CN 201220019092 patent/CN202548495U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109584833A (en) * | 2019-01-21 | 2019-04-05 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
| CN109584833B (en) * | 2019-01-21 | 2021-06-01 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
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| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20121121 |