CN202495916U - Digital circuit capable of eliminating key jittering - Google Patents

Abstract

The utility model relates to a digital circuit capable of eliminating key jittering. A key signal X and an output end Q1 of a trigger DFF1 are connected with an and gate AND1, the key signal Z and an output end Q0 of a trigger DFF0 are connected with an and gate AND2, the output ends Q0 and Q1 are connected with an and gate AND3; output ends of the and gate AND1, the and gate AND2 and the and gate AND3 are connected with an or gate OR. A sampling clock CLK is connected with clock input ends of the trigger DFF0 and DFF1, the key signal X is connected with an input end D0 of the trigger DFFO, or an output end of the or gate OR is connected with an input end D1 of the trigger DFF1, an output Q1 of the trigger DFF1 is an output of the key signal after jittering prevention process. The circuit can be used in household appliances, telephones and teaching experiment boxes or the like.

Description

A Digital Circuit for Eliminating Key Shake

technical field

The utility model relates to a digital circuit design for eliminating vibration of mechanical keys, which is applied to keys with poor anti-shake effect and can effectively eliminate vibration. the

Background technique

Ordinary buttons do not have anti-shake, and one hand press can generate multiple inputs, which is often encountered in real life. For example, the buttons in the EDA experiment box used by students have very little elasticity, and the vibration is very serious when pressed once. Some solutions are to prolong the action time of the key after pressing the key, so that the vibration of the key during the extended key time is invalid. But the disadvantage of this method is that if the extended key-press time is set too long, two key-presses in a short period of time will be mistaken for one. Use buttons with good elasticity to prevent shaking in actual products, such as mobile phone buttons. the

Contents of the invention

A switch with poor mechanical properties may produce the effect of pressing multiple keys once. The utility model provides a digital circuit, which can eliminate key vibration, so that only one effective signal can be generated by pressing a key once. the

The technical solution adopted by the utility model to solve the technical problem is: a digital circuit for eliminating button jitter, including AND gate, OR gate and D flip-flop, the sampling clock CLK is connected to the clock input terminals of flip-flops DFF0 and DFF1, and the button signal X is connected to the input terminal D ₀ of the flip-flop DFF0, and the output of the OR gate OR is connected to the input terminal D ₁ of the flip-flop DFF1. The output Q ₁ of the flip-flop DFF1 is the output of the key signal after anti-shake processing.

Read button information under continuous sampling signals; if two (and above) adjacent sampled button signals are both pressed, it is determined that the button is pressed, otherwise it is determined that the button is in a shaking state; if two (and more) adjacent If the sampled key signals are all lifted, it is determined that the key is lifted, otherwise it is determined that the key is in a shaking state; the signals for determining that the key is pressed and lifted in the above two steps are respectively sent to the component that receives the key action as a valid key signal, Realize the elimination of button jitter. the

The design process is as follows: Let X be the key input, and Y be the output. CLK is the sampling clock of the button. the

The state transition diagram is shown in Figure 2. The input of S ₀ is always 0, which means that the sampling signal has been sampled 0 twice in a row. At this time, it is considered that it has released the button stably; the input of S ₁ is 1, which means that the time of pressing is not long enough. It is considered that the button is invalid; S ₂ inputs two 1s, which means that the sampling signal has been sampled twice 1 continuously, and at this time it is considered that the button has been pressed steadily; the input of S ₃ is shaking from 1 to 0, which means that the hand is shaking. In short, it is necessary to sample two consecutive 1s to output 1, and two 0s to output 0.

Coding scheme: S ₀ is 00, S ₁ is 01, S ₂ is 11, S ₃ is 10. Draw a Karnaugh map representing the next-state logic function and carry function (as shown in Table 1).

的卡诺图  Table 1 Secondary state/output

Karnaugh map

The state equation and output equation of the circuit obtained from the Karnaugh map are:

${\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="Q"\; filenames="HSA00000597000400012.png"\; state="\{\{state\}\}">Q</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}^{\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="0"\; label="Q"\; filenames="HSA00000597000400012.png"\; state="\{\{state\}\}">Q</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; x</span>}{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; x</span>}{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="Q"\; filenames="HSA00000597000400012.png"\; state="\{\{state\}\}">Q</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}$

Q ₀ ⁿ⁺¹ ＝X

Y=Q ₁

It is realized with D flip-flop, and the anti-shake circuit diagram is obtained according to the state equation and the output equation, as shown in Figure 1. The key signal X and the output terminal _Q1 of the trigger DFF1 are connected to the AND gate AND1, the key signal X and the output terminal _Q0 of the trigger DFF0 are connected to the AND gate AND2, and the output terminals _Q0 and _Q1 of the two flip-flops are connected to the AND gate AND3; The output terminals of the gates AND1, AND2 and AND3 are connected with the OR gate OR. The sampling clock CLK is connected to the clock input terminals of flip-flops DFF0 and DFF1, the key signal X is connected to the input terminal D ₀ of the flip-flop DFF0, the output of the OR gate OR is connected to the input terminal D ₁ of the flip-flop DFF1, and the output Q ₁ of the flip-flop DFF1 is the button The output of the signal after anti-shake processing.

The beneficial effect of the utility model is that one input signal will be generated once a key is pressed, and multiple inputs will not be generated, so as to ensure that the number of times a person presses a key is truly reflected. the

Description of drawings

Below in conjunction with accompanying drawing and embodiment the utility model is further described. the

Fig. 1 is the digital circuit diagram of the present utility model;

Figure 2 is a state transition diagram. the

Detailed ways

The utility model will be further described below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the utility model. the

Embodiment 1: A kind of digital circuit that eliminates key jitter, as shown in Figure 1, comprises AND gate, OR gate and D flip-flop, the sampling clock CLK connects the clock input end of flip-flop DFF0 and DFF1, and key signal X connects flip-flop The input terminal D ₀ of DFF0 and the output of the OR gate OR are connected to the input terminal D ₁ of the flip-flop DFF1 , and the output Q ₁ of the flip-flop DFF1 is the output of the key signal after anti-shake processing.

Embodiment 2: The button signal X and the output terminal _Q1 of the flip-flop DFF1 are connected to the AND gate AND1, the button signal X and the output terminal _Q0 of the flip-flop DFF0 are connected to the AND gate AND2, and the output terminals _Q0 and _Q1 of the two flip-flops are connected to the AND gate. Gate AND3; the output terminals of AND gates AND1, AND2 and AND3 are connected with OR gate OR. The frequency range of the sampling clock CLK is 64-4KHz, and the sampling clock CLK is connected to the clock input terminals of the flip-flops DFF0 and DFF1. The key signal X is connected to the input terminal D ₀ of the flip-flop DFF0, the output of the OR gate OR is connected to the input terminal D ₁ of the flip-flop DFF1, and the output Q ₁ of the flip-flop DFF1 is the output of the key signal after anti-shake processing.

The above-mentioned embodiments are only two kinds of specific implementation methods of the utility model, and the usual changes and replacements carried out by those skilled in the art within the scope of the technical solution of the utility model all should be included in the protection scope of the utility model. the

Claims (2)

1. digital circuit of eliminating key jitter; Comprise and door or door and d type flip flop; It is characterized in that: sampling clock CLK connects the input end of clock of trigger DFF0 and DFF1; Push button signalling X connects the input D0 of trigger DFF0, or the output connection trigger DFF1 input D1 of door OR, and the output Q1 of trigger DFF1 is that push button signalling is through anti-output of trembling after handling.

2. a kind of digital circuit of eliminating key jitter according to claim 1 is characterized in that: push button signalling X and trigger DFF1 output Q ₁Connect and door AND1, push button signalling X and trigger DFF0 output Q ₀Connect and door AND2, the output Q of two triggers ₀And Q ₁Connect and door AND3; Be connected or door OR with the output of door AND1, AND2 and AND3.

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