CN202076992U - D flip-flop - Google Patents
D flip-flop Download PDFInfo
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- CN202076992U CN202076992U CN2011201796551U CN201120179655U CN202076992U CN 202076992 U CN202076992 U CN 202076992U CN 2011201796551 U CN2011201796551 U CN 2011201796551U CN 201120179655 U CN201120179655 U CN 201120179655U CN 202076992 U CN202076992 U CN 202076992U
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Abstract
The utility model relates to a D flip-flop which comprises a first phase inverter U1, a second phase inverter U2 with a control end, a third phase inverter U3 with a control end, a fourth phase inverter U4 and a fifth phase inverter U5, wherein a clock signal of the D flip-flop is connected with the input end of the first phase inverter U1; when the clock signal is arranged at a first electrical level, the clock signal controls the second phase inverter U2 with the control end to lock and store inverted signals of input signals in the second phase inverter U2 with the control end; and when the clock signal is arranged at a second electric level, the clock signal controls the third phase inverter U3 with the control end to lock and store the input signals in the third phase inverter with the control end. According to different electrical levels at which the clock signal is arranged, the input signals are respectively locked and stored in the second phase inverter with the control end and the third phase inverter with the control end and then are output through the fourth phase inverter and the fifth phase inverter, so that the circuit has a simple structure, and the relay of signals is reduced.
Description
Technical field
The utility model relates to integrated circuit fields, is specifically related to a kind of d type flip flop.
Background technology
The normal employing of existing high speed d trigger circuit structure shown in Figure 1; The operation principle of this circuit is: when CK for ' 1 ' time, the D signal is sampled on the parasitic capacitance of drain node of the anti-phase M3 of being saved in pipe; At this moment the drain voltage of M4 is ' 0 '; The source voltage of M8 pipe is ' 1 '.After CK became ' 0 ', the D signal just voltage on the parasitic capacitance of the drain node by the anti-phase M3 of being saved in pipe was delivered on the drain voltage of M4, at this moment the high low reaction of the drain voltage of M4 the height of input signal D; The drain voltage of M4 is delivered to the drain electrode of M7 with the D signal inversion, and the drain voltage of M7 and input D signal are anti-phase; The anti-phase output Q that is delivered to of inverter that the drain voltage of M7 is formed through M11 and M10, output Q voltage response the height of input signal D; Output Q voltage is through the anti-phase output NQ that is delivered to of inverter of M12 and M13 composition, and output NQ voltage and input signal D are anti-phase.So just, finished the sampling output function of d type flip flop, this d type flip flop is the trigger that the clock trailing edge triggers.The circuit structure complexity of this trigger, and need pass through Pyatyi to the path of the inverse output terminal NQ of d type flip flop from input D signal, make signal delay longer.
The utility model content
The utility model is for solving the long problem of prior art d type flip flop complex structure and signal delay, thereby the d type flip flop that a kind of circuit structure is simple, signal delay is short is provided.
For solving the problems of the technologies described above, the utility model provides following technical scheme:
A kind of d type flip flop comprises: first inverter, have second inverter of control end, have the 3rd inverter, the 4th inverter and the 5th inverter of control end; The output that has second inverter of control end connects the input of the 3rd inverter that has control end, the output that has the 3rd inverter of control end connects the input of the 4th inverter, the output of the 4th inverter connects the input of the 5th inverter, described the 4th inverter is output as the reversed-phase output of d type flip flop, and the output of the 5th inverter is the in-phase output end of d type flip flop; The clock signal of d type flip flop connects the input of first inverter, described clock signal is when first level, second inverter that clock signal control has control end is latching to input signal in second inverter that has control end, described clock signal is when second level, and the 3rd inverter that clock signal control has control end is latching to input signal in the 3rd inverter that has control end.
Further, second inverter that has control end comprises first switch of series connection successively, NMOS pipe, PMOS pipe and second switch, the one NMOS pipe and PMOS pipe are formed second inverter, the input of second inverter is the input that has second inverter of control end, the output of second inverter is the output that has second inverter of control end, and described clock signal is controlled first switch and second switch while turn-on and turn-off.
Preferably, described first switch is the NMOS pipe.
Preferably, described second switch is the PMOS pipe.
Further, the 3rd inverter that has control end comprises the 3rd switch of series connection successively, the 2nd NMOS pipe, the 2nd PMOS pipe and the 4th switch, the 2nd NMOS pipe and the 2nd PMOS pipe are formed the 3rd inverter, the input of the 3rd inverter is the input that has the 3rd inverter of control end, the output of the 3rd inverter is the output that has the 3rd inverter of control end, and described clock signal is controlled the 3rd switch and the 4th switch while turn-on and turn-off.
Preferably, described the 3rd switch is the NMOS pipe.
Preferably, described the 4th switch is the PMOS pipe.
Compared with prior art, the utlity model has following beneficial effect: a kind of d type flip flop that the utility model provides, varying level according to the clock signal place, respectively input signal is latched in second inverter that has control end and has in the 3rd inverter of control end, then through the 4th inverter and the output of the 5th inverter, sort circuit is simple in structure, and the inverse output terminal from the input signal to the d type flip flop has only passed through the tertiary road footpath, and the delay of signal reduces.
Description of drawings
Fig. 1 is prior art d type flip flop circuit theory diagrams.
Fig. 2 is the utility model first embodiment d type flip flop circuit theory diagrams.
Fig. 3 is the utility model second embodiment d type flip flop circuit theory diagrams.
Fig. 4 is the utility model embodiment d type flip flop schematic symbol diagram.
Fig. 5 is that the utility model embodiment uses the two-divider schematic diagram that d type flip flop forms.
Fig. 6 is that the utility model embodiment uses the tri-frequency divider schematic diagram that d type flip flop forms.
Fig. 7 is that the utility model embodiment uses four-divider selected or the five frequency divider schematic diagram that d type flip flop forms.
Fig. 8 is the four-divider schematic diagram of having simplified among Fig. 7.
Fig. 9 is the five frequency divider schematic diagram of having simplified among Fig. 7.
Embodiment
Clearer for technical problem, technical scheme and beneficial effect that the utility model is solved, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explanation the utility model, and be not used in qualification the utility model.
Fig. 2 is the utility model first embodiment d type flip flop circuit theory diagrams; Disclose a kind of d type flip flop, having comprised: the first inverter U1, had the second inverter U2 of control end, have the 3rd inverter U3, the 4th inverter U4 and the 5th inverter U5 of control end; The output that has the second inverter U2 of control end connects the input of the 3rd inverter U3 that has control end, the output U3 that has the 3rd inverter of control end connects the input of the 4th inverter U4, the output of the 4th inverter U4 connects the input of the 5th inverter U5, described the 4th inverter U4 is output as the reversed-phase output of d type flip flop, and the output of the 5th inverter U5 is the in-phase output end of d type flip flop; The clock signal of d type flip flop connects the input of the first inverter U1, described clock signal C K is when first level, the second inverter U2 that clock signal C K control has a control end is latching to the inversion signal of input signal among the second inverter U2 that has control end, described clock signal C K is when second level, and the 3rd inverter U3 that clock signal C K control has control end is latching to input signal among the 3rd inverter U3 that has control end.Varying level according to clock signal C K place, respectively input signal is latched in the second inverter U2 that has control end and has among the 3rd inverter U3 of control end, then through the 4th inverter U4 and the 5th inverter U5 output, sort circuit is simple in structure, inverse output terminal from the input signal to the d type flip flop has only passed through the tertiary road footpath, and the delay of signal reduces.
In the present embodiment, the second inverter U2 that has control end comprises first switch S 1 of series connection successively, NMOS pipe M11, PMOS pipe M12 and second switch S2, the one NMOS pipe M11 and PMOS pipe M12 form second inverter, the input of second inverter is the input that has the second inverter U2 of control end, the output of second inverter is the output that has the second inverter U2 of control end, and clock signal C K controls first switch and second switch while turn-on and turn-off.The 3rd inverter U3 that has control end comprises the 3rd switch S 3 of series connection successively, the 2nd NMOS pipe M13, the 2nd PMOS pipe M14 and the 4th switch S 4, the 2nd NMOS pipe M13 and the 2nd PMOS pipe M14 form the 3rd inverter, the input of the 3rd inverter is the input that has the 3rd inverter U3 of control end, the output of the 3rd inverter is the output that has the 3rd inverter U3 of control end, and described clock signal is controlled the 3rd switch S 3 and the 4th switch S 4 while turn-on and turn-off.The first inverter U1 is with the anti-phase output inversion clock of clock signal C K signal NCK, and when clock signal C K was high level, first switch S 1 and second switch S2 all disconnected, the 3rd switch S 3 and the 4 equal conductings of the 4th switch S; When clock signal C K is low level, first switch S 1 and the equal conducting of second switch S2, the 3rd switch S 3 and the 4th switch S 4 all disconnect.
Fig. 3 is the utility model second embodiment d type flip flop circuit theory diagrams; On the basis of Fig. 2, wherein first switch S 1 is the NMOS pipe, and second switch S2 is the PMOS pipe, and the 3rd switch S 3 is the NMOS pipe, and the 4th switch S 4 is the PMOS pipe.The inverted signal of the clock signal of clock signal control second switch S2 and the 3rd switch S 3, the first inverter U1 output is controlled first switch S 1 and the 4th switch S 4 in the present embodiment.
The high point of present embodiment setting is flat to be expressed as ' 1 ', and low level is expressed as ' 0 '.Operation principle is: when clock signal CK for ' 0 ' time, input signal D is sampled on the parasitic capacitance of drain node that inversion signal is saved in NMOS pipe M11.When clock signal CK becomes ' 1 ', the anti-phase drain electrode that is delivered to the 2nd NMOS pipe M13 of the drain voltage of NMOS pipe M11, at this moment the drain voltage of the 2nd NMOS pipe M13 has reflected the input signal D that is sampled; The drain voltage of the 2nd NMOS pipe M13 is through the anti-phase reversed-phase output NQ that is delivered to d type flip flop of the 4th inverter U4, and the reversed-phase output NQ voltage of d type flip flop and the input signal D that is sampled are anti-phase; Reversed-phase output NQ voltage is through the anti-phase in-phase output end Q that is delivered to d type flip flop of the 5th inverter U5, and in-phase output end Q voltage is identical with the input signal D that is sampled.The symbol of this d type flip flop can represent that wherein D is an input signal with Fig. 4, and CK is a clock signal, and the in-phase output end of d type flip flop is Q, the reversed-phase output NQ of d type flip flop.
D type flip flop can also have a lot of application, and Fig. 5 is that the utility model embodiment uses the two-divider schematic diagram that d type flip flop forms.The reversed-phase output NQ of d type flip flop is linked to each other with the D input, and in-phase output end Q is output as the two divided-frequency signal of clock signal C K.Concise and to the point operation principle is: the initial state voltage of supposing initial state reversed-phase output NQ is ' 1 ', and after triggered clock signal C K first upper edge, in-phase output end Q end was output as ' 1 ', and reversed-phase output NQ end is output as ' 0 '; After clock signal C K triggered second upper edge, in-phase output end Q was output as ' 0 ', and reversed-phase output NQ end is output as ' 1 '; After clock signal C K triggered the 3rd upper edge, in-phase output end Q was output as ' 1 ', and reversed-phase output NQ is output as ' 0 ', and at this moment clock signal C K passed through for two cycles, and one-period is just experienced in in-phase output end Q output, so finished divide-by-two function.Initial state reversed-phase output NQ initial state voltage also is the same reason for ' 0 ', repeats no more herein.
Fig. 6 is that the utility model embodiment uses the tri-frequency divider schematic diagram that d type flip flop forms; The clock end of second d type flip flop 12 and 3d flip-flop 13 all is connected clock signal C K, the in-phase output end Q of second d type flip flop 12 connects the input of 3d flip-flop 13, the in-phase output end Q of second d type flip flop 12 and the in-phase output end Q of 3d flip-flop 13 all are connected two inputs of first NAND gate 14, the output of first NAND gate 14 connects the input of second d type flip flop 12, and the in-phase output end Q of second d type flip flop 12 is the two-divider output.The Q end initial state of supposing second d type flip flop 12 is output as ' 0 ', and the Q end of 3d flip-flop 13 is output as ' 0 ', and like this, the input of the D of second d type flip flop 12 end is exactly ' 1 '.
After first clock signal C K upper edge was come, the Q of second d type flip flop 12 end was output as ' 1 ', and the Q end of 3d flip-flop 13 is output as ' 0 ', and like this, the input of the D of second d type flip flop 12 end is exactly ' 1 '.
After second clock CK upper edge come, the Q of second d type flip flop 12 end was output as ' 1 ', and the Q end of 3d flip-flop 13 is output as ' 1 ', and like this, the input of the D of second d type flip flop 12 end is exactly ' 0 '.
After the 3rd clock CK upper edge come, the Q of second d type flip flop 12 end was output as ' 0 ', and the Q end of 3d flip-flop 13 is output as ' 1 ', and like this, the input of the D of second d type flip flop 12 end is exactly ' 1 '.
After the 4th clock CK upper edge come, the Q of second d type flip flop 12 end was output as ' 1 ', and the Q end of 3d flip-flop 13 is output as ' 0 ', and like this, the input of the D of second d type flip flop 12 end is exactly ' 1 '.
At this moment as can be seen, behind three clocks, the Q of second d type flip flop 12 end is output as ' 1 ', and the Q end of 3d flip-flop 13 is output as ' 0 ', the D end input of second d type flip flop 12 ' 1 ' state has exactly reappeared, and that is to say that this circuit is the circuit of three frequency division.When initial state was worth for other, operation principle was identical, repeats no more herein.
Fig. 7 is that the utility model embodiment uses four-divider selected or the five frequency divider schematic diagram that d type flip flop forms; Four d flip-flop 14, the clock end of the 5th d type flip flop 15 and the 6th d type flip flop 16 all is connected clock signal C K, the in-phase output end Q of four d flip-flop 14 connects the input of the 5th d type flip flop 15, the reversed-phase output of the 5th d type flip flop 15 connects an input of second NAND gate 17, another input of second NAND gate 17 connects selects signal sel, the output of second NAND gate 17 connects the input of the 6th d type flip flop 16, the in-phase output end of the 6th d type flip flop 16 connects an input of the 3rd NAND gate 18, the in-phase output end of the 5th d type flip flop 15 connects another input of the 3rd NAND gate 18, the output of the 3rd NAND gate 18 connects the input of four d flip-flop 14, and the in-phase output end of four d flip-flop 14 is the output of this frequency divider.
For simplifying circuit, when sel was ' 0 ', this frequency divider was 4 frequency divisions; Simplify circuit as shown in Figure 8; The in-phase output end Q of four d flip-flop 14 connects the input of the 5th d type flip flop 15, and the reversed-phase output of the 5th d type flip flop 15 connects the input of four d flip-flop 14, and the in-phase output end of four d flip-flop 14 is the output of this frequency divider.Operation principle is as follows:
The Q end of supposing initial state four d flip-flop 14 is output as ' 0 ', and the Q end of the 5th d type flip flop 15 is output as ' 0 ', and like this, the input of the NQ of the 5th d type flip flop 15 end is exactly ' 1 '.
After first clock CK rising edge arrived, the output of the Q of four d flip-flop 14 end was ' 1 ', and the NQ end that the Q end of the 5th d type flip flop 15 is output as the ' 0 ', the 5th d type flip flop 15 is output as ' 1 '.
After second clock CK rising edge arrived, the output of the Q of four d flip-flop 14 end was ' 1 ', and the NQ end that the Q end of the 5th d type flip flop 15 is output as the ' 1 ', the 5th d type flip flop 15 is output as ' 0 '.
After the 3rd clock CK rising edge arrived, the output of the Q of four d flip-flop 14 end was ' 0 ', and the NQ end that the Q end of the 5th d type flip flop 15 is output as the ' 1 ', the 5th d type flip flop 15 is output as ' 0 '.
After the 4th clock CK rising edge arrived, the output of the Q of four d flip-flop 14 end was ' 0 ', and the NQ end that the Q end of the 5th d type flip flop 15 is output as the ' 0 ', the 5th d type flip flop 15 is output as ' 1 '.At this moment as can be seen, behind four clocks, the Q of four d flip-flop 14 end is output as ' 0 ', and the Q end of the 5th d type flip flop 15 is output as ' 0 ' state and has reappeared, and that is to say that this circuit is the circuit of four frequency divisions.When initial state was worth for other, operation principle was identical, repeats no more herein.
When sel was ' 1 ', this frequency divider was 5 frequency divisions, simplified circuit as shown in Figure 9; The in-phase output end Q of four d flip-flop 14 connects the input of the 5th d type flip flop 15, the in-phase output end of the 5th d type flip flop 15 connects an input of the 3rd NAND gate 18, the in-phase output end of the 5th d type flip flop 15 connects the input of the 6th d type flip flop 16, the in-phase output end of the 6th d type flip flop 16 connects another input of the 3rd NAND gate 18, the output of the 3rd NAND gate 18 connects the input of four d flip-flop 14, and the in-phase output end of four d flip-flop 14 is the output of this frequency divider.Operation principle is as follows:
The Q end initial state of supposing four d flip-flop 14 is output as ' 0 ', and the Q end of d type flip flop b is output as ' 0 ', and the Q end of d type flip flop E is output as ' 0 ', and like this, the input of the D of four d flip-flop 14 end is exactly ' 1 '.
After first clock CK upper edge was come, the Q of four d flip-flop 14 end was output as ' 1 ', and the Q end that the Q end of the 5th d type flip flop 15 is output as the ' 0 ', the 6th d type flip flop 16 is output as ' 0 ', and like this, the input of the D of four d flip-flop 14 end is exactly ' 1 '.
After second clock CK upper edge come, the Q of four d flip-flop 14 end was output as ' 1 ', and the Q end that the Q end of the 5th d type flip flop 15 is output as the ' 1 ', the 6th d type flip flop 16 is output as ' 0 ', and like this, the input of the D of four d flip-flop 14 end is exactly ' 1 '.
After the 3rd clock CK upper edge come, the Q of four d flip-flop 14 end was output as ' 1 ', and the Q end that the Q end of the 5th d type flip flop 15 is output as the ' 1 ', the 6th d type flip flop 16 is output as ' 1 ', and like this, the input of the D of four d flip-flop 14 end is exactly ' 0 '.
After the 4th clock CK upper edge come, the Q of four d flip-flop 14 end was output as ' 0 ', and the Q end that the Q end of the 5th d type flip flop 15 is output as the ' 1 ', the 6th d type flip flop 16 is output as ' 1 ', and like this, the input of the D of four d flip-flop 14 end is exactly ' 0 '.
After the 5th clock CK upper edge come, the Q of four d flip-flop 14 end was output as ' 0 ', and the Q end that the Q end of the 5th d type flip flop 15 is output as the ' 0 ', the 6th d type flip flop 16 is output as ' 1 ', and like this, the input of the D of four d flip-flop 14 end is exactly ' 1 '.
After the 6th clock CK upper edge come, the Q of four d flip-flop 14 end was output as ' 1 ', and the Q end that the Q end of the 5th d type flip flop 15 is output as the ' 0 ', the 6th d type flip flop 16 is output as ' 0 ', and like this, the input of the D of four d flip-flop 14 end is exactly ' 1 '.
At this moment as can be seen, behind five clocks, the Q of four d flip-flop 14 end is output as ' 1 ', and the Q end of the 5th d type flip flop 15 is output as ' 0 ', the Q of the 6th d type flip flop 16 end is output as ' 0 ' state and has reappeared, and that is to say that this circuit is the circuit of five frequency divisions.When initial state was worth for other, operation principle was identical, repeats no more herein.
The above only is preferred embodiment of the present utility model; not in order to restriction the utility model; all any modifications of within spirit of the present utility model and principle, being done, be equal to and replace and improvement etc., all should be included within the protection range of the present utility model.
Claims (7)
1. a d type flip flop is characterized in that, comprising: first inverter, have second inverter of control end, have the 3rd inverter, the 4th inverter and the 5th inverter of control end; The output that has second inverter of control end connects the input of the 3rd inverter that has control end, the output that has the 3rd inverter of control end connects the input of the 4th inverter, the output of the 4th inverter connects the input of the 5th inverter, described the 4th inverter is output as the reversed-phase output of d type flip flop, and the output of the 5th inverter is the in-phase output end of d type flip flop; The clock signal of d type flip flop connects the input of first inverter, described clock signal is when first level, second inverter that clock signal control has a control end is latching to the inversion signal of input signal in second inverter that has control end, described clock signal is when second level, and the 3rd inverter that clock signal control has control end is latching to input signal in the 3rd inverter that has control end.
2. d type flip flop according to claim 1, it is characterized in that, second inverter that has control end comprises first switch of series connection successively, NMOS pipe, PMOS pipe and second switch, the one NMOS pipe and PMOS pipe are formed second inverter, the input of second inverter is the input that has second inverter of control end, the output of second inverter is the output that has second inverter of control end, and described clock signal is controlled first switch and second switch while turn-on and turn-off.
3. d type flip flop according to claim 2 is characterized in that, described first switch is the NMOS pipe.
4. d type flip flop according to claim 2 is characterized in that, described second switch is the PMOS pipe.
5. d type flip flop according to claim 1, it is characterized in that, the 3rd inverter that has control end comprises the 3rd switch of series connection successively, the 2nd NMOS pipe, the 2nd PMOS pipe and the 4th switch, the 2nd NMOS pipe and the 2nd PMOS pipe are formed the 3rd inverter, the input of the 3rd inverter is the input that has the 3rd inverter of control end, the output of the 3rd inverter is the output that has the 3rd inverter of control end, and described clock signal is controlled the 3rd switch and the 4th switch while turn-on and turn-off.
6. d type flip flop according to claim 5 is characterized in that, described the 3rd switch is the NMOS pipe.
7. d type flip flop according to claim 5 is characterized in that, described the 4th switch is the PMOS pipe.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011201796551U CN202076992U (en) | 2011-05-31 | 2011-05-31 | D flip-flop |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011201796551U CN202076992U (en) | 2011-05-31 | 2011-05-31 | D flip-flop |
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| CN202076992U true CN202076992U (en) | 2011-12-14 |
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| CN2011201796551U Expired - Fee Related CN202076992U (en) | 2011-05-31 | 2011-05-31 | D flip-flop |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102497201A (en) * | 2011-12-21 | 2012-06-13 | 东南大学 | True Single-Phase Clock (TSPC) 2/3 dual-mode prescaler with high speed and low power consumption |
-
2011
- 2011-05-31 CN CN2011201796551U patent/CN202076992U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102497201A (en) * | 2011-12-21 | 2012-06-13 | 东南大学 | True Single-Phase Clock (TSPC) 2/3 dual-mode prescaler with high speed and low power consumption |
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