CN202473903U - Loading frame for semiconductor devices - Google Patents
Loading frame for semiconductor devices Download PDFInfo
- Publication number
- CN202473903U CN202473903U CN 201120565322 CN201120565322U CN202473903U CN 202473903 U CN202473903 U CN 202473903U CN 201120565322 CN201120565322 CN 201120565322 CN 201120565322 U CN201120565322 U CN 201120565322U CN 202473903 U CN202473903 U CN 202473903U
- Authority
- CN
- China
- Prior art keywords
- pin
- loading
- semiconductor device
- semiconductor devices
- loading stage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
The utility model provides a loading frame for semiconductor devices. The loading frame comprises a plurality of loading units connected in parallel, wherein each loading unit consists of loading platforms, a first pin, a second pin and a third pin. The loading platforms comprises the left loading platform and the right loading platform, wherein the left loading platform is electrically connected with the first pin and the right loading platform is electrically connected with the third pin; the first pin and the third pin can separately used as a negative electrode for the respective semiconductor devices loaded on the left loading platform and the right loading platform ; and the second pin can be used as a common positive electrode for the two semiconductor devices. A pin reinforcement is disposed among the three pins and the plurality of loading units, and the three pins and the plurality of loading units are connected by the pin reinforcement. The plane where the loading platforms are positioned is 1 mm to 5 mm lower than the plane where the pins and the pin reinforcement are positioned. With the loading frame for semiconductor devices, two semiconductor devices using a common positive electrode can be realized; such a loading mode is different from that of conventional common negative electrodes; and thus special loading requirements of different semiconductor devices can be satisfied, and further, mutual interference between main bodies of packages of the two semiconductor devices seldom occurs.
Description
Technical field
The utility model relates to the semiconductor device Load frame.
Background technology
Lead frame (Load frame) is as the carrier of semiconductor chip, is a kind ofly to realize being electrically connected of chip internal circuit exit and outer lead by means of bonding wire, and the key structure spare of formation electric loop, it has played the function served as bridge that is connected with outer lead.All need use lead frame in the semiconductor integrated package of the overwhelming majority, supply follow-up technical processs such as semiconductor packages to use, lead frame is a basic material important in the electronics and information industry.Common lead frame; Be formed in parallel by a plurality of load units; Each load units is made up of pins such as loading stage, first pin, second pin, the 3rd pins, is connected with the pin muscle between three pins and between a plurality of load units, combines to constitute the semiconductor device Load frame.
The number of applying for a patent is to have introduced a kind of " semiconductor packages and lead frame thereof " in 200420006462.6 the specification, and this lead frame comprises the platform that is used for installing semiconductor chip above that, is arranged in a plurality of leads of platform periphery and a plurality of pin interconnection parts of those lead-in wires that are used to interconnect.Through lead frame is enclosed in the moulded resin member, produced the QFN semiconductor package, wherein lead portion comes out from moulded resin member, forms through cutting at the line of cut place subsequently.This patent provides that a kind of traditional loading stage is as a whole, second pin of shared centre is as the lead frame of negative electrode.
The utility model content
Utility model purpose: overcome traditional single defective of semiconductor chip lead frame structure, a kind of Load frame that can supply two semiconductor device common anode is provided.
Technical scheme: a kind of semiconductor device Load frame that the utility model provides; Be formed in parallel by a plurality of load units; Each load units is made up of loading stage, first pin, second pin, the 3rd pin; Be connected with the pin muscle between three pins and between a plurality of load units, constitute the semiconductor device Load frame together.Loading stage is divided into two of left loading stage and right loading stages, can load a semiconductor device respectively; The left side loading stage and first pin are electrically connected, and right loading stage connects with the 3rd pin is electric, and first pin, the 3rd pin respectively can be as the negative electrodes of the semiconductor device that loads separately, and second pin can be as the public anode of two semiconductor device.
The utility model supplies semiconductor device to load and supplies follow-up semiconductor packages technical process to use, and after the loading semiconductor device encapsulation, the pin muscle is fallen in punching, can become independently to encapsulate the load units finished product one by one.
Described semiconductor device is meant semiconductor chips such as diode chip for backlight unit, triode chip, integrated package.
The plane at described loading stage place can be lower than the plane 1mm-5mm at pin and pin muscle place.
Between two of described left loading stage and the right loading stages the wide loading stage gap of 0.5mm-2mm can be arranged.
Described loading stage, pin or both can be coated with one deck gold or silver-colored, with the bonding wire that strengthens semiconductor device and the conductive capability between the pin.
Beneficial effect: the utility model can be realized two semiconductor device common anode, and this load mode with traditional common cathode is different, satisfies the special stowage requirement of different semiconductor device.In addition, the main part of two semiconductor device packages is separated, and interferes with each other and lacks, and can change separately during a damage, reduces the maintenance cost in using.
Description of drawings
Fig. 1 is the structural representation of facing of the utility model;
Fig. 2 is the left TV structure sketch map of Fig. 1 of the utility model;
Among the figure: 1, load units; 2, left loading stage; 3, loading stage gap; 4, right loading stage; 5, first pin; 6, second pin; 7, the 3rd pin; 8, pin muscle.
Embodiment
Below in conjunction with accompanying drawing the utility model is done description more specifically.
Like accompanying drawing 1, shown in 2, load units 1 is made up of left loading stage 2, right loading stage 4, first pin 5, second pin 6, the 3rd pin 7, is connected with pin muscle 8 between three pins.The left side loading stage 2 and first pin 5 are electrically connected right loading stage 4 and 7 electric connections of the 3rd pin; Two loading stages can load a diode chip for backlight unit respectively, and first pin 5, the 3rd pin 7 respectively can be as the negative electrodes of the diode chip for backlight unit that loads separately, and second pin 6 can be as the public anode of two diode chip for backlight unit.
Between 4 two of described left loading stage 2 and the right loading stages the wide loading stage gap 3 of 1mm is arranged, the plane at described two loading stages place is lower than the plane 2mm at pin 5,6,7 and pin muscle 8 places.
Be formed in parallel by a plurality of load units 1; Be connected with the utility model of pin muscle 8 between a plurality of load units 1; After loading diode chip for backlight unit, can use for follow-up diode chip for backlight unit potting process, again after the diode chip for backlight unit encapsulation; Pin muscle 8 is fallen in punching, can become independently to encapsulate the diode finished product one by one.
Claims (4)
1. semiconductor device Load frame; Be formed in parallel by a plurality of load units (1); Each load units (1) is made up of loading stage, first pin (5), second pin (6), the 3rd pin (7); Be connected with pin muscle (8) between three pins and between a plurality of load units (1), it is characterized in that: loading stage is divided into (4) two of left loading stage (2) and right loading stages, can load a semiconductor device respectively; Left side loading stage (2) is electrically connected with first pin (5); Right loading stage (4) and electric connection of the 3rd pin (7); First pin (5), the 3rd pin (7) respectively can be as the negative electrodes of the semiconductor device that loads separately, and second pin (6) can be as the public anode of two semiconductor device.
2. semiconductor device Load frame according to claim 1 is characterized in that: the plane at described loading stage place is lower than the plane 1mm-5mm at pin and pin muscle (8) place.
3. semiconductor device Load frame according to claim 1 is characterized in that: between (4) two of described left loading stage (2) and the right loading stages the wide loading stage gap (3) of 0.5mm-2mm is arranged.
4. according to claim 1,2 or 3 described semiconductor device Load frame, it is characterized in that: described loading stage, pin or both are coated with one deck gold or silver-colored, with the bonding wire that strengthens semiconductor device and the conductive capability between the pin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120565322 CN202473903U (en) | 2011-12-30 | 2011-12-30 | Loading frame for semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201120565322 CN202473903U (en) | 2011-12-30 | 2011-12-30 | Loading frame for semiconductor devices |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202473903U true CN202473903U (en) | 2012-10-03 |
Family
ID=46922046
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201120565322 Expired - Lifetime CN202473903U (en) | 2011-12-30 | 2011-12-30 | Loading frame for semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202473903U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106409805A (en) * | 2016-12-06 | 2017-02-15 | 四川富美达微电子有限公司 | Five-pin IC structure |
-
2011
- 2011-12-30 CN CN 201120565322 patent/CN202473903U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106409805A (en) * | 2016-12-06 | 2017-02-15 | 四川富美达微电子有限公司 | Five-pin IC structure |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20121003 |
|
| CX01 | Expiry of patent term |