CN202443814U - Residual voltage optimization type surge protection device - Google Patents
Residual voltage optimization type surge protection device Download PDFInfo
- Publication number
- CN202443814U CN202443814U CN201120176496XU CN201120176496U CN202443814U CN 202443814 U CN202443814 U CN 202443814U CN 201120176496X U CN201120176496X U CN 201120176496XU CN 201120176496 U CN201120176496 U CN 201120176496U CN 202443814 U CN202443814 U CN 202443814U
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- residual voltage
- type surge
- optimization type
- voltage
- voltage optimization
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Abstract
A residual voltage optimization type surge protection device is characterized in that input conductors are separated from output conductors at pins of piezoresistor chips, double-elastic-arm linkage forms are adopted at high-voltage ends, and linkage rods are welded with the pins of the high-voltage ends of the piezoresistor chips by low-temperature soldering tin. Connecting terminals are disposed at two ends of each ground wire end connecting plate. After the residual voltage optimization type surge protection device is assembled, each connecting position is provided with an input terminal and an output terminal, residual voltage of piezoresistors is thoroughly separated from connection wire inductance voltage drop of connecting wires, so that outputted residual voltage is reduced as compared with a conventional product, peak positions are postponed, residual voltage outputted to the ground from the four wires L1, L2, L3 and L4 is unaffected by connection wire inductance of ground wires, each wire keeps balanced, waveforms of the residual voltage reflect the true level of the piezoresistor chips without any interferences.
Description
Affiliated technical field
The utility model belongs to one type of residual voltage optimization type surge protector, is to use L1, L2, L3, the N four line-to-grounds protection power surge protector of piezo-resistance assembling.
Background technology
At first, use L1, L2, L3, the N four line-to-grounds protection power surge protector of piezo-resistance assembling at present, big with its through-current capacity, the characteristics that residual voltage is low are unique products of power supply secondary thunder and lightning and surge protection always.But, cause four lines to export the uneven problem of residual voltage over the ground because the chosen position of ground terminal is different.Common surge protector product is exported the equipotential ground terminal under the L3-PE module; Make that the residual voltage output of one road L1-PE is exported with the residual voltage of nearest one road L3-PE farthest; Under 60kA, differ up to 300V; High like this pressure reduction is that the surge pulse of transition produces under the induction reactance effect of different length ground wire connecting line, and this will influence this phase line connect greatly by the protection effect of protection equipment, so that thunder and lightning or overcurrent to damage accident often take place.Simple change PE electrical grounding position or 4 equal ground connection all can't change this problem.
Secondly; Because the package design of the surge protector of present stage, piezo-resistance are after passing through electrode and terminal is connected, in the pressure drop of the inner lead-in inductance formation of protector; Can when its output residual voltage, be superimposed upon on the true residual voltage of piezo-resistance; Cause output residual voltage protection level to be elevated, the residual voltage wave distortion, the wave head uplift rate improves.These problems can cause the forfeiture of the true protective capability of chip, and product competitiveness is low.
Summary of the invention
The utility model provides a kind of surge protector that the output residual voltage is had optimization function; Can make the residual voltage of L1, L2, L3, N four line-to-grounds export the influence that does not receive the sense of ground wire connecting line; Can eliminate the line pressure-sensitive of surge protector enclosure output lead falls; The output residual voltage that reaches protector reduces, and the residual voltage waveform does not distort, the advantage that the wave head uplift rate reduces.
The utility model solves the technical scheme that its technical problem adopted: in insulation crust; With piezoresistive wafer, connecting line, binding post is critical piece; It is characterized in that: the pin place of piezoresistive wafer isolates input and output lead, and high-pressure side adopts two elastic arm interlock forms, and two ends of ground terminal brace are provided with binding post; Residual voltage optimization type surge protector after the assembling, each road wiring position all have two terminals of input and output.
Be divided into two parts in the inner connection design of residual voltage optimization type surge protector: (1) high-pressure side connects design: pair elastic arms interlock forms are adopted in the change of high-pressure side dropout elastic arm, high-pressure side, and gangbar and piezo-resistance high-pressure side pin are done the eutectic welding soldering and connect.The other end at two elastic arms independently welds binding post separately.(2) design of Grounding Connections mode: the ground electrode equipotential of every circuit voltage dependent resistor chip is connected; This ground terminal brace can be directly, turn, prolong the back at two binding posts of its two ends welding, guarantees that these two terminals are arranged on the two ends of all chip pins in equivalent electric circuit.
The beneficial effect of the utility model is, do the time spent when protector plays earial drainage to thunder and lightning or surge pulse, the output residual voltage that equipment obtains eliminated wired pressure-sensitive stack of falling; Descend 40%; Residual voltage peak value time of occurrence is postponed, and residual voltage climbing speed du/dt descends 70%, and the residual voltage value is impartial over the ground to have realized four circuit L1, L2, L3, N; Output residual voltage waveform does not distort, and ideally embodies the residual voltage performance of piezo-resistance.
Description of drawings
Fig. 1 is the inside front view of the utility model.
Fig. 2 is the A-A section left view of Fig. 1.
Fig. 3 is the upward view of Fig. 1.
1. high-voltage terminals among the figure (into and out of a pair of), the 2. two elastic arms of high-pressure side, 3. piezo-resistance, 4. two elastic arm gangbar, 5. ground terminal pin, 6. ground terminal brace, 7. bending place, 8. ground wire terminals (into and out of a pair of), 9. protector insulation crusts of high-pressure side
Embodiment
In Fig. 1; In the end welding of the downside of high-voltage terminal 1 with the two elastic arms 2 of high-pressure side; And piezo-resistance 3 is arranged in the below of high-voltage terminal 1; Use of high-pressure side pin and high-pressure side two elastic arm gangbar 4 welding of low temperature scolding tin, be positioned at the ground terminal pin 5 and ground terminal brace 6 reliable soldering of piezo-resistance below piezo-resistance the place ahead.Ground terminal brace 6 in the bending place 7 bend backward 90 the degree, two ground wire terminals 8 are welded at two terminals of the brace after the bending respectively.Four circuits are connected to finish be fixed in the protector insulation crust 9.
In Fig. 2, in the A-A section left view, the two elastic arms 2 of high-pressure side are connected to piezo-resistance high-pressure side pin with certain flexibility, when guaranteeing the low temperature melts soldering tin disengaging at two elastic arm gangbar 4 places of high-pressure side, have necessary elastic force.
In Fig. 3, the ground terminal brace is one-body molded, after 7 bendings of bending place, forms the vertical relation of piezo-resistance pin joint face and terminal joint face at ground terminal brace 6.
Claims (3)
1. residual voltage optimization type surge protector; In insulation crust, be critical piece with piezoresistive wafer, connecting line, binding post, it is characterized in that: the pin place of piezoresistive wafer isolates input and output lead; High-pressure side adopts two elastic arm interlock forms; Two ends of ground terminal brace are provided with binding post, and the residual voltage optimization type surge protector after the assembling, each road wiring position all have two terminals of input and output.
2. residual voltage optimization type surge protector according to claim 1 is characterized in that: the ground terminal brace can be directly, turn, prolong the back at two binding posts of its two ends welding.
3. residual voltage optimization type surge protector according to claim 1 is characterized in that: high-pressure side adopts two elastic arm interlock forms, and gangbar and piezo-resistance high-pressure side pin are done the eutectic welding soldering and connect.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201120176496XU CN202443814U (en) | 2011-05-30 | 2011-05-30 | Residual voltage optimization type surge protection device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201120176496XU CN202443814U (en) | 2011-05-30 | 2011-05-30 | Residual voltage optimization type surge protection device |
Publications (1)
Publication Number | Publication Date |
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CN202443814U true CN202443814U (en) | 2012-09-19 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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CN201120176496XU Expired - Fee Related CN202443814U (en) | 2011-05-30 | 2011-05-30 | Residual voltage optimization type surge protection device |
Country Status (1)
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CN (1) | CN202443814U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104269834A (en) * | 2014-08-18 | 2015-01-07 | 山东华普信息科技有限公司 | Low-pulse surge protection device |
-
2011
- 2011-05-30 CN CN201120176496XU patent/CN202443814U/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104269834A (en) * | 2014-08-18 | 2015-01-07 | 山东华普信息科技有限公司 | Low-pulse surge protection device |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
DD01 | Delivery of document by public notice |
Addressee: Jia Chaochao Document name: Notification to Make Rectification |
|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
DD01 | Delivery of document by public notice |
Addressee: Jia Chaochao Document name: Notification to Pay the Fees |
|
C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120919 Termination date: 20140530 |