CN202435329U - Rotary transformer decoding processing device based on single FPGA (Field Programmable Gate Array) - Google Patents
Rotary transformer decoding processing device based on single FPGA (Field Programmable Gate Array) Download PDFInfo
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- CN202435329U CN202435329U CN2011205231305U CN201120523130U CN202435329U CN 202435329 U CN202435329 U CN 202435329U CN 2011205231305 U CN2011205231305 U CN 2011205231305U CN 201120523130 U CN201120523130 U CN 201120523130U CN 202435329 U CN202435329 U CN 202435329U
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Abstract
The utility model discloses a rotary transformer decoding processing device based on a single FPGA (Field Programmable Gate Array). The rotary transformer decoding processing device comprise a DSP (Digital Signal Processor) control circuit, an FPGA circuit, an analog-to-digital conversion circuit, an input signal conditioning circuit, an output excitation signal buffer circuit and a rotary transformer, wherein the FPGA circuit is connected with the analog-to-digital conversion circuit electrically; the input end of the output excitation signal buffer circuit is connected on the analog-to-digital conversion circuit electrically; the output end of the output excitation signal buffer circuit is connected with the rotary transformer; the output end of the rotary transformer is connected with the input signal conditioning circuit electrically; the output end of the input signal conditioning circuit is connected with the analog-to-digital conversion circuit electrically; and the DSP control circuit is connected with the FPGA circuit electrically. The purposes of simple communication between external circuits and the modules and a flexible system structure are realized.
Description
Technical field
The utility model relates to the resolver field, particularly, relates to a kind of resolver decoding processing device based on single FPGA.
Background technology
In the power Loading Control System, need carry out closed-loop control, thereby the power that realizes high fidelity loads, so whether position, angle, tachometric survey be accurately very crucial as far as system to position, angle, the speed of motor.It is main with photoelectric encoder mainly that traditional position, angle, speed detect; But the black and white line of demarcation of each code channel of photoelectric encoder always has half to align with the black and white line of demarcation of adjacent inner coil code channel; Will cause shortcomings such as parasitic error because of black and white line of demarcation portrayal inaccuracy like this; Development along with electronics industry; The raising of the integrated degree of electronic devices and components, the signal processing circuit of resolver become simply, reliable, price also descends greatly; Therefore, the utilization resolver is realized method that position, angle, speed detect because its wide ranges that tests the speed, precision are high, good, the easy advantage such as reliable of dynamic response and obtained using widely at Aero-Space, industry, traffic and civil area.At present; Most signals of rotating transformer decoding all adopts special-purpose resolver analog to digital conversion circuit to accomplish; And utilization microprocessor and the next common completion control corresponding of CPLD, but the communication more complicated between peripheral circuit and each module, and system configuration is dumb.
The utility model content
The purpose of the utility model is, to the problems referred to above, proposes a kind of resolver decoding processing device based on single FPGA, and is simple to realize the communication between peripheral circuit and each module, and system configuration advantage flexibly.
For realizing above-mentioned purpose, the technical scheme that the utility model adopts is:
A kind of resolver decoding processing device based on single FPGA; It is characterized in that; The modulate circuit, output excitation signal buffer circuit and the resolver that comprise DSP control circuit, FPGA circuit, analog to digital conversion circuit, input signal; Said FPGA circuit is electrically connected with analog to digital conversion circuit; The input of said output excitation signal buffer circuit is connected electrically on the analog to digital conversion circuit, and its output is connected electrically on the resolver, and the output of said resolver is connected electrically on the modulate circuit of input signal; The output of the modulate circuit of input signal is connected electrically on the analog to digital conversion circuit, and said DSP control circuit and FPGA circuit are electrically connected.
According to the preferably embodiment of the utility model, the modulate circuit of above-mentioned input signal is the modulate circuit of 4 road input signals.
According to the preferably embodiment of the utility model, above-mentioned output excitation signal buffer circuit is 2 tunnel output excitation signal buffer circuits.
According to the preferably embodiment of the utility model, be connected with two-way analog to digital conversion circuit at least on the above-mentioned FPGA circuit.
The technical scheme of the utility model; Adopt the FPGA circuit to realize the detection and the decoding processing of multichannel motor Jiao Jiao position, speed and acceleration signal; Thereby realized the closed-loop control of multidimensional servo loading system; Because of adopting single FPGA circuit control multichannel resolver, make that the communication between peripheral circuit and each module is simple.The whole system structure is more flexible.
Further feature of the utility model and advantage will be set forth in specification subsequently, and, partly from specification, become obvious, perhaps understand through implementing the utility model.The purpose of the utility model can realize through the structure that in the specification of being write, claims and accompanying drawing, is particularly pointed out and obtain with other advantages.
Through accompanying drawing and embodiment, the technical scheme of the utility model is done further detailed description below.
Description of drawings
Accompanying drawing is used to provide the further understanding to the utility model, and constitutes the part of specification, is used to explain the utility model with the embodiment of the utility model, does not constitute the restriction to the utility model.In the accompanying drawings:
Fig. 1 is the work block diagram of the described dual rotary transformer decoding processing device based on single FPGA of the utility model embodiment;
Fig. 2 reads the flow chart of two-way resolver position and rate signal for the said FPGA of the utility model embodiment.
Embodiment
Describe below in conjunction with the preferred embodiment of accompanying drawing, should be appreciated that preferred embodiment described herein only is used for explanation and explains the utility model, and be not used in qualification the utility model the utility model.
A kind of resolver decoding processing device based on single FPGA; The modulate circuit, output excitation signal buffer circuit and the resolver that comprise DSP control circuit, FPGA circuit, analog to digital conversion circuit, input signal; FPGA circuit and analog to digital conversion circuit link together through lead; The input of the modulate circuit of input signal is connected on the analog to digital conversion circuit through lead; Its output is connected on the resolver through lead; The output of resolver is connected through lead on the modulate circuit of input signal, and the output of the modulate circuit of input signal is connected on the analog to digital conversion circuit through lead, and DSP control circuit and FPGA circuit link together.
Wherein the modulate circuit of input signal is the modulate circuit of 4 road input signals.Output excitation signal buffer circuit is 2 tunnel output excitation signal buffer circuits.Be connected with two-way analog to digital conversion circuit at least on the FPGA circuit.
DSP control circuit: be the master controller of whole device, read position, angle, speed, the acceleration signal of the motor of FPGA circuit collection;
FPGA circuit: send chip selection signal and give analog to digital conversion circuit; Set the threshold values of this analog to digital conversion circuit; And gating one road analog to digital conversion circuit; Close other analog to digital conversion circuit, read the position, corresponding angle and the speed digital signal of resolver and calculate the relevant acceleration signal, be stored in them in the appropriate address of FPGA circuit;
Analog to digital conversion circuit: the signal from the modulate circuit of above-mentioned FPGA circuit and input signal that will accept carries out digital-to-analogue conversion;
Output excitation signal buffer circuit: the excitation signal of above-mentioned analog to digital conversion circuit conversion is exported to resolver afterwards through the power amplification processing;
The modulate circuit of input signal: export to institute's analog to digital conversion circuit after the cosine and sine signal of the position, representative motor angle of resolver output and speed passed through filtering and processing and amplifying.
A kind of resolver decoding processing method based on single FPGA may further comprise the steps:
Send chip selection signal by the FPGA circuit, gating analog to digital conversion circuit simultaneously, and according to the actual needs of system carries out the given of threshold value by the FPGA circuit to the register of analog to digital conversion circuit;
The FPGA circuit sends chip selection signal, and gating one road analog to digital conversion circuit is closed other road analog to digital conversion circuits;
The analog to digital conversion circuit of gating is exported corresponding excitation signal according to prior preset threshold;
Output excitation signal buffer circuit carries out above-mentioned excitation signal to export to resolver after power amplification is handled;
The excitation signal that resolver receives after the above-mentioned processing and amplifying is rotated;
The modulate circuit of input signal is exported to institute's analog to digital conversion circuit after the cosine and sine signal of the position, representative motor angle of resolver output and rotary speed is passed through filtering and processing and amplifying;
The analog signal conversion of analog to digital conversion circuit after with above-mentioned processing is digital signal, and exports to the FPGA circuit;
The FPGA circuit reads position, corresponding motor angle and speed digital signal according to corresponding sequential, and calculates the relevant acceleration signal, and the signal message of position, motor angle, speed and acceleration is stored in the appropriate address of FPGA circuit.
Be illustrated in figure 1 as dual rotary transformer signal decoding processing unit and method, its peripheral circuit comprises the modulate circuit of two 4 road input signals, the buffer circuit of two 2 tunnel output excitation signals, 2 road analog to digital conversion circuits, FPGA circuit; At first send chip selection signal by the FPGA module, the simultaneously said A of gating, B two-way analog to digital conversion circuit, and according to the actual needs of system carry out the given of threshold value by the FPGA circuit to the register of A, B two-way analog to digital conversion circuit simultaneously; And then send chip selection signal by the FPGA circuit; Gating A road analog to digital conversion circuit; Close B road analog to digital conversion circuit, and, read corresponding position and speed digital signal by the FPGA circuit according to corresponding sequential; And calculate the relevant acceleration signal, be stored in them in the appropriate address of FPGA circuit; Send chip selection signal by the FPGA circuit more at last; Gating B road analog to digital conversion circuit; Close A road analog to digital conversion circuit, and, read position, corresponding motor angle and speed digital signal by the FPGA circuit according to corresponding sequential; And calculate the relevant acceleration signal, be stored in them in the appropriate address of FPGA circuit.
The modulate circuit of input signal will be advanced filtering by the simulation cosine and sine signal of the position, representative motor angle of resolver output and speed and obtain analog to digital conversion circuit acceptable signal with processing and amplifying and also import.
Each road output excitation signal buffer circuit, the excitation signal of accepting analog to digital conversion circuit output is through obtaining excitation signal and the input that resolver needs after the power amplification circuit processing.
The FPGA circuit adopts cyclone II series circuit; Be that altera corp is fundamentally to the low-cost high-performance that designs and the FPGA of low-power consumption; Free Quartus II network edition design software, multiple intellectual property (IP) by easy to use provide support, and can realize low-cost FPGA solution development rapidly.
The resolver analog to digital conversion circuit adopts the AD2S1210 chip; Be a 10 to the 16 bit resolution digital converter of rotary transformer of Analog Devices company; Go up sine-wave oscillator able to programme for integrated,, realized ratio tracking conversion, system failure detection for resolver provides sinusoidal wave excitation; Improve application flexibility greatly, can well realize position, rate signal accurate transformation.
What should explain at last is: the above is merely the preferred embodiment of the utility model; Be not limited to the utility model; Although the utility model has been carried out detailed explanation with reference to previous embodiment; For a person skilled in the art, it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement.All within the spirit and principle of the utility model, any modification of being done, be equal to replacement, improvement etc., all should be included within the protection range of the utility model.
Claims (4)
1. resolver decoding processing device based on single FPGA; It is characterized in that; The modulate circuit, output excitation signal buffer circuit and the resolver that comprise DSP control circuit, FPGA circuit, analog to digital conversion circuit, input signal; Said FPGA circuit is electrically connected with analog to digital conversion circuit; The input of said output excitation signal buffer circuit is connected electrically on the analog to digital conversion circuit, and its output is connected electrically on the resolver, and the output of said resolver is connected electrically on the modulate circuit of input signal; The output of the modulate circuit of input signal is connected electrically on the analog to digital conversion circuit, and said DSP control circuit and FPGA circuit are electrically connected.
2. the resolver decoding processing device based on single FPGA according to claim 1 is characterized in that: the modulate circuit of above-mentioned input signal is the modulate circuit of 4 road input signals.
3. the resolver decoding processing device based on single FPGA according to claim 1 is characterized in that: above-mentioned output excitation signal buffer circuit is 2 tunnel output excitation signal buffer circuits.
4. the resolver decoding processing device based on single FPGA according to claim 1 is characterized in that: be connected with two-way analog to digital conversion circuit at least on the above-mentioned FPGA circuit.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011205231305U CN202435329U (en) | 2011-12-14 | 2011-12-14 | Rotary transformer decoding processing device based on single FPGA (Field Programmable Gate Array) |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011205231305U CN202435329U (en) | 2011-12-14 | 2011-12-14 | Rotary transformer decoding processing device based on single FPGA (Field Programmable Gate Array) |
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| CN202435329U true CN202435329U (en) | 2012-09-12 |
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| CN2011205231305U Expired - Fee Related CN202435329U (en) | 2011-12-14 | 2011-12-14 | Rotary transformer decoding processing device based on single FPGA (Field Programmable Gate Array) |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102403938A (en) * | 2011-12-14 | 2012-04-04 | 兰州交通大学 | Decoding device and method for rotary transformer based on single FPGA (Field Programmable Gate Array) |
| CN103078571A (en) * | 2013-01-04 | 2013-05-01 | 天津清源电动车辆有限责任公司 | Rotary transformer system and control method thereof |
| CN105180974A (en) * | 2015-08-31 | 2015-12-23 | 奇瑞汽车股份有限公司 | Rotary transformer decoding interface circuit |
| CN106357172A (en) * | 2016-08-29 | 2017-01-25 | 西安秦川数控系统工程有限公司 | Sine-cosine signal processing circuit for speed and positon feedback |
| CN107991919A (en) * | 2017-10-31 | 2018-05-04 | 河北汉光重工有限责任公司 | One kind rotation becomes excitatory and signal acquisition integrated circuit |
-
2011
- 2011-12-14 CN CN2011205231305U patent/CN202435329U/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102403938A (en) * | 2011-12-14 | 2012-04-04 | 兰州交通大学 | Decoding device and method for rotary transformer based on single FPGA (Field Programmable Gate Array) |
| CN102403938B (en) * | 2011-12-14 | 2013-07-17 | 兰州交通大学 | Decoding device and method for rotary transformer based on single FPGA (Field Programmable Gate Array) |
| CN103078571A (en) * | 2013-01-04 | 2013-05-01 | 天津清源电动车辆有限责任公司 | Rotary transformer system and control method thereof |
| CN105180974A (en) * | 2015-08-31 | 2015-12-23 | 奇瑞汽车股份有限公司 | Rotary transformer decoding interface circuit |
| CN106357172A (en) * | 2016-08-29 | 2017-01-25 | 西安秦川数控系统工程有限公司 | Sine-cosine signal processing circuit for speed and positon feedback |
| CN107991919A (en) * | 2017-10-31 | 2018-05-04 | 河北汉光重工有限责任公司 | One kind rotation becomes excitatory and signal acquisition integrated circuit |
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Granted publication date: 20120912 Termination date: 20121214 |