CN202334463U - High-accuracy voltage comparator - Google Patents

High-accuracy voltage comparator Download PDF

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Publication number
CN202334463U
CN202334463U CN2011204704655U CN201120470465U CN202334463U CN 202334463 U CN202334463 U CN 202334463U CN 2011204704655 U CN2011204704655 U CN 2011204704655U CN 201120470465 U CN201120470465 U CN 201120470465U CN 202334463 U CN202334463 U CN 202334463U
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CN
China
Prior art keywords
preamplifier
circuit
latch
clock control
comparator
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Expired - Fee Related
Application number
CN2011204704655U
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Chinese (zh)
Inventor
胡炜
何明华
王法翔
张志晓
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Fuzhou University
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Fuzhou University
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Priority to CN2011204704655U priority Critical patent/CN202334463U/en
Application granted granted Critical
Publication of CN202334463U publication Critical patent/CN202334463U/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

The utility model relates to a high-accuracy voltage comparator. The high-accuracy voltage comparator is characterized by comprising an analogue buffer, a bias circuit, a clock control circuit, a first preamplifier, a second preamplifier, a third preamplifier, a fourth preamplifier and a rear-stage latch regenerating circuit, wherein the first preamplifier, the second preamplifier, the third preamplifier, the fourth preamplifier and the rear-stage latch regenerating circuit are in sequential cascaded connection; coupled capacitors are connected among the first preamplifier, the second preamplifier, the third preamplifier, the fourth preamplifier and the rear-stage latch regenerating circuit, and the bias circuit is used for supplying bias voltage for the four preamplifiers, the clock control circuit and the analogue buffer; and analogue buffer is used for the inputting buffering of reference voltage; and the clock control circuit is used for generating a clock control signal of each circuit. According to the utility model, a novel dynamic latch comparator with preamplifiers is adopted, the advantages of the traditional comparator are combined, the circuit structure is simple, the speed is fast, and the accuracy is high.

Description

A kind of high-accuracy voltage comparator
Technical field
The utility model relates to a kind of high-accuracy voltage comparator and method for designing thereof.
Background technology
Comparator is the core circuit module of analog to digital converter.The performance quality of comparator has directly influenced conversion accuracy, conversion speed of analog to digital converter etc.The open loop comparator precision of traditional amplifier structure is high, but speed is slow; The conventional dynamic latched comparator is owing to used positive feedback, and speed is fast, but precision is low.
Summary of the invention
The purpose of the utility model provides a kind of high-accuracy voltage comparator.
The device of the utility model adopts following scheme to realize: a kind of high-accuracy voltage comparator is characterized in that: first preamplifier, second preamplifier, the 3rd preamplifier, the 4th preamplifier and the back level Latch that comprise analogue buffer, biasing circuit, clock control circuit and cascade successively latch regenerative circuit; Described first preamplifier, second preamplifier, the 3rd preamplifier, the 4th preamplifier and back level Latch latch and all are connected with coupling capacitance between the regenerative circuit, and described biasing circuit is that level Four preamplifier, clock control circuit and analogue buffer provide bias voltage; Described analogue buffer is used for the buffering of input reference voltage; Described clock control circuit produces the clock control signal of each circuit.
In the utility model one embodiment, described back level Latch latchs regenerative circuit and comprises that the waveform of a pair of output carries out the clock SR latch of shaping.
The utlity model has following advantage:
1, precision is high: be level Four amplifier open loop structure during the comparator operate as normal, gain is big, and precision is high.Preamplifier has adopted the operational amplifier structure of the weak positive feedback of band.The Latch level has also comprised clock SR latch except latching regenerative circuit, output waveform is carried out shaping.This paper has adopted input to lack of proper care and has stored and exported the offset voltage technology for eliminating that imbalance stores cascade, and the equivalent remaining input offset voltage that disappearance is mediated after the reason is lower.
2, speed is fast: whole late-class circuit has adopted Latch to latch revived structure, because it has used positive feedback, than very fast, output voltage becomes the positive exponent relation with the time, can export comparison signal fast to late-class circuit to the large-signal response speed.
Description of drawings
Fig. 1 is the circuit theory sketch map of the utility model embodiment.
Fig. 2 is the circuit diagram of the first order preamplifier of the utility model embodiment.
Fig. 3 is second and third level of the utility model embodiment, the circuit diagram of level Four preamplifier.
Fig. 4 is that the Latch of the utility model embodiment latchs the regenerative circuit sketch map.
Fig. 5 is that the Latch of the utility model embodiment latchs the clock SR latch circuit sketch map in the regenerative circuit.
Embodiment
Below in conjunction with accompanying drawing and embodiment the utility model is further specified.
As shown in Figure 1; The nucleus module of the comparator of present embodiment is that level Four preamplifier and latch latch regenerative circuit; In addition also have analogue buffer, biasing circuit, clock control circuit etc.; Please continue with reference to Fig. 1; Described first preamplifier, second preamplifier, the 3rd preamplifier, the 4th preamplifier and back level Latch latch and all are connected with coupling capacitance between the regenerative circuit, and described biasing circuit is that level Four preamplifier, clock control circuit and analogue buffer provide bias voltage; Described analogue buffer is used for the input buffering of reference voltage; Described clock control circuit produces the clock control signal of each circuit.
The utility model adopts preposition amplifier; The prime input signal is carried out processing and amplifying; Quaternary structure can arrive each amplifier with gain allocation simultaneously, and the gain of each amplifier does not need too big, the influence of adopting input to lack of proper care storage and export the way elimination input offset voltage of imbalance storage cascade simultaneously; Be embodied in input offset voltage is stored on the input and output coupling capacitance, and be less input offset voltage through the high-gain different working state equivalence of the preposition amplifier of level Four.After reason is mediated in disappearance; The remaining equivalent input noise voltage of comparator mainly receives the offset voltage of fourth stage amplifier, latch and the influence that switch is injected into the offset charge on the electric capacity; For third level amplifier, existing input imbalance storage has output imbalance storage again; After cascade was handled, the input offset voltage of third level amplifier was eliminated totally.And the gain that the offset voltage of fourth stage amplifier and latch level is put before divided by level Four, actual equivalence becomes very little to the input offset voltage.First order amplifier structure is as shown in Figure 2, second,, three grades, level Four amplifier structure is as shown in Figure 3.
Please with reference to Fig. 4 and Fig. 5, present embodiment Latch latchs regenerative circuit and through positive feedback signal is amplified to the amplitude that digital circuit can effectively be discerned rapidly again.In addition, comparator input terminal and latch regenerative circuit are isolated through preposition amplifier, effectively reduce latch regenerative circuit backhaul The noise.
In addition, biasing circuit is that modules such as preamplifier, clock processing circuit, analogue buffer provide bias voltage.The analogue buffer circuit is used for the input buffering of reference voltage.Clock control circuit produces the clock control signal of each module.
What deserves to be mentioned is; The comparator of the utility model is the core circuit of digital to analog converter; And analog to digital converter is widely used in movable equipment, battery supply set, the acquisition system of Industry Control and data and signal; In medical treatment and the safety check imaging system equipment, have bigger using value and economic benefit.
The above is merely the preferred embodiment of the utility model, and all equalizations of being done according to the utility model claim change and modify, and all should belong to the covering scope of the utility model.

Claims (2)

1. high-accuracy voltage comparator is characterized in that: first preamplifier, second preamplifier, the 3rd preamplifier, the 4th preamplifier and the back level Latch that comprise analogue buffer, biasing circuit, clock control circuit and cascade successively latch regenerative circuit; Described first preamplifier, second preamplifier, the 3rd preamplifier, the 4th preamplifier and back level Latch latch and all are connected with coupling capacitance between the regenerative circuit, and described biasing circuit is that level Four preamplifier, clock control circuit and analogue buffer provide bias voltage; Described analogue buffer is used for the input buffering of reference voltage; Described clock control circuit produces the clock control signal of each circuit.
2. a kind of high-accuracy voltage comparator according to claim 1 is characterized in that: described back level Latch latchs regenerative circuit and comprises that the waveform of a pair of output carries out the clock SR latch of shaping.
CN2011204704655U 2011-11-24 2011-11-24 High-accuracy voltage comparator Expired - Fee Related CN202334463U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2011204704655U CN202334463U (en) 2011-11-24 2011-11-24 High-accuracy voltage comparator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2011204704655U CN202334463U (en) 2011-11-24 2011-11-24 High-accuracy voltage comparator

Publications (1)

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CN202334463U true CN202334463U (en) 2012-07-11

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102394610A (en) * 2011-11-24 2012-03-28 福州大学 High-precision voltage comparator and design method thereof
CN103036508A (en) * 2012-12-20 2013-04-10 清华大学深圳研究生院 High-speed low-crosstalk pre-amplifier, dynamic comparator and circuit
CN103066966A (en) * 2012-12-27 2013-04-24 成都锐成芯微科技有限责任公司 High-speed comparator variable in common-mode wide power supply range
CN106771518A (en) * 2016-12-09 2017-05-31 圣邦微电子(北京)股份有限公司 A kind of cascaded triggering formula current comparison circuit for reducing power consumption
US11528016B2 (en) 2021-01-21 2022-12-13 Apple Inc. Low latency comparator with local clock circuit
CN118017985A (en) * 2024-04-10 2024-05-10 深圳市赛元微电子股份有限公司 Dynamic latching comparator

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102394610A (en) * 2011-11-24 2012-03-28 福州大学 High-precision voltage comparator and design method thereof
CN103036508A (en) * 2012-12-20 2013-04-10 清华大学深圳研究生院 High-speed low-crosstalk pre-amplifier, dynamic comparator and circuit
CN103036508B (en) * 2012-12-20 2016-01-20 清华大学深圳研究生院 The prime amplifier of the low crosstalk of high speed, dynamic comparer and circuit
CN103066966A (en) * 2012-12-27 2013-04-24 成都锐成芯微科技有限责任公司 High-speed comparator variable in common-mode wide power supply range
CN103066966B (en) * 2012-12-27 2015-06-17 成都锐成芯微科技有限责任公司 High-speed comparator variable in common-mode wide power supply range
CN106771518A (en) * 2016-12-09 2017-05-31 圣邦微电子(北京)股份有限公司 A kind of cascaded triggering formula current comparison circuit for reducing power consumption
US11528016B2 (en) 2021-01-21 2022-12-13 Apple Inc. Low latency comparator with local clock circuit
CN118017985A (en) * 2024-04-10 2024-05-10 深圳市赛元微电子股份有限公司 Dynamic latching comparator

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C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20120711

Termination date: 20141124

EXPY Termination of patent right or utility model