CN102394610A - High-precision voltage comparator and design method thereof - Google Patents
High-precision voltage comparator and design method thereof Download PDFInfo
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- CN102394610A CN102394610A CN2011103762268A CN201110376226A CN102394610A CN 102394610 A CN102394610 A CN 102394610A CN 2011103762268 A CN2011103762268 A CN 2011103762268A CN 201110376226 A CN201110376226 A CN 201110376226A CN 102394610 A CN102394610 A CN 102394610A
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Abstract
The invention relates to a high-precision voltage comparator and a design method thereof. The amplification treatment is carried out on a preceding stage input signal by a four-level preamplifier, and then the signal is amplified to amplitude which can be identified by a backward stage circuit by positive feedback through a backward stage latch regenerating circuit; and simultaneously a cascade connection technology of input imbalance storage and output imbalance storage is adopted to eliminate the influence of input imbalance voltage. The invention adopts a novel dynamic latch comparator with the preamplifier so as to be fully combined with the advantages of the traditional comparators, and is simple in circuit structure, fast in speed and high in accuracy.
Description
Technical field
The present invention relates to a kind of high-accuracy voltage comparator and method for designing thereof.
Background technology
Comparator is the core circuit module of analog to digital converter.The performance quality of comparator has directly influenced conversion accuracy, conversion speed of analog to digital converter etc.The open loop comparator precision of traditional amplifier structure is high, but speed is slow; The conventional dynamic latched comparator is owing to used positive feedback, and speed is fast, but precision is low.
Summary of the invention
The purpose of this invention is to provide a kind of high-accuracy voltage comparator and method for designing thereof.
Method of the present invention adopts following scheme to realize: a kind of method for designing of high-accuracy voltage comparator; It is characterized in that: adopt the level Four preamplifier; After the prime input signal carried out processing and amplifying, latch regenerative circuit by a back level Latch and signal is amplified to the amplitude that late-class circuit can be discerned through positive feedback; Each inter-stage adopts input imbalance storage and output imbalance storage cascade to eliminate the influence of input offset voltage simultaneously.
Device of the present invention adopts following scheme to realize: a kind of high-accuracy voltage comparator is characterized in that: first preamplifier, second preamplifier, the 3rd preamplifier, the 4th preamplifier and the back level Latch that comprise analogue buffer, biasing circuit, clock control circuit and cascade successively latch regenerative circuit; Described first preamplifier, second preamplifier, the 3rd preamplifier, the 4th preamplifier and back level Latch latch and all are connected with coupling capacitance between the regenerative circuit, and described biasing circuit is that level Four preamplifier, clock control circuit and analogue buffer provide bias voltage; Described analogue buffer is used for the input buffering of reference voltage; Described clock control circuit produces the clock control signal of each circuit.
The present invention has the following advantages:
1, precision is high: be level Four amplifier open loop structure during the comparator operate as normal, gain is big, and precision is high.Preamplifier has adopted the operational amplifier structure of the weak positive feedback of band.The Latch level has also comprised clock SR latch except latching regenerative circuit, output waveform is carried out shaping.This paper has adopted input to lack of proper care and has stored and exported the offset voltage technology for eliminating that imbalance stores cascade, and the equivalent remaining input offset voltage that disappearance is mediated after the reason is lower.
2, speed is fast: whole late-class circuit has adopted Latch to latch revived structure, because it has used positive feedback, than very fast, output voltage becomes the positive exponent relation with the time, can export comparison signal fast to late-class circuit to the large-signal response speed.
Description of drawings
Fig. 1 is the circuit theory sketch map of the embodiment of the invention.
Fig. 2 is the circuit diagram of the first order preamplifier of the embodiment of the invention.
Fig. 3 be the embodiment of the invention second and third, the circuit diagram of level Four preamplifier.
Fig. 4 is that the Latch of the embodiment of the invention latchs the regenerative circuit sketch map.
Fig. 5 is that the Latch of the embodiment of the invention latchs the clock SR latch circuit sketch map in the regenerative circuit.
Embodiment
The present invention provides a kind of method for designing of high-accuracy voltage comparator; This method adopts the level Four preamplifier; After the prime input signal carried out processing and amplifying, latch regenerative circuit by a back level Latch and signal is amplified to the amplitude that late-class circuit can be discerned through positive feedback; Each inter-stage adopts input imbalance storage and output imbalance storage cascade to eliminate the influence of input offset voltage simultaneously.Described input imbalance storage and output imbalance storage cascade are that input offset voltage is stored on the coupling capacitance that each inter-stage is connected, and the high gain characteristics of passing through the preposition amplifier of level Four is less input offset voltage with its equivalence.
In order to let those skilled in the art better understand the present invention, below we combine accompanying drawing that hardware of the present invention is constituted and principle further specifies.
As shown in Figure 1; The nucleus module of the comparator of present embodiment is that level Four preamplifier and latch latch regenerative circuit; In addition also have analogue buffer, biasing circuit, clock control circuit etc.; Please continue with reference to Fig. 1; Described first preamplifier, second preamplifier, the 3rd preamplifier, the 4th preamplifier and back level Latch latch and all are connected with coupling capacitance between the regenerative circuit, and described biasing circuit is that level Four preamplifier, clock control circuit and analogue buffer provide bias voltage; Described analogue buffer is used for the input buffering of reference voltage; Described clock control circuit produces the clock control signal of each circuit.
The present invention adopts preposition amplifier; The prime input signal is carried out processing and amplifying; Quaternary structure can arrive each amplifier with gain allocation simultaneously, and the gain of each amplifier does not need too big, the influence of adopting input to lack of proper care storage and export the way elimination input offset voltage of imbalance storage cascade simultaneously; Be embodied in input offset voltage is stored on the input and output coupling capacitance, and be less input offset voltage with its equivalence through the high gain characteristics of the preposition amplifier of level Four.After reason is mediated in disappearance; The remaining equivalent input noise voltage of comparator mainly receives the offset voltage of fourth stage amplifier, latch and the influence that switch is injected into the offset charge on the electric capacity, for the second, three grade of amplifier; Existing input imbalance storage; Output imbalance storage is arranged again, and after cascade was handled, the input offset voltage of third level amplifier was eliminated totally.And the offset voltage of fourth stage amplifier and latch level is divided by the gain of putting before three grades, and actual equivalence becomes very little to the input offset voltage.First order amplifier structure is as shown in Figure 2, second and third, level Four amplifier structure is as shown in Figure 3.
Please with reference to Fig. 4 and Fig. 5, present embodiment Latch latchs regenerative circuit and through positive feedback signal is amplified to the amplitude that digital circuit can effectively be discerned rapidly again.In addition, comparator input terminal and latch regenerative circuit are isolated through preposition amplifier, effectively reduce latch regenerative circuit backhaul The noise.
In addition, biasing circuit is that modules such as preamplifier, clock processing circuit, analogue buffer provide bias voltage.The analogue buffer circuit is used for the input buffering of reference voltage.Clock control circuit produces the clock control signal of each module.
What deserves to be mentioned is that comparator of the present invention is the core circuit of digital to analog converter, and analog to digital converter is widely used in movable equipment, battery supply set, the acquisition system of Industry Control and data and signal is in medical treatment and the safety check imaging system equipment.Can be widely used in Cadence, ADS, Hspice, multiple IC design platform such as Pspice.Can draw through emulation: but this comparator has under 10% the variation all operate as normal at supply voltage, lower to the requirement of foundries technology simultaneously, do not adopt high special process, can effectively reduce cost.Should the comparator applying flexible, promptly can handle as independent IP, also can be integrated in the middle of other integrated circuits, have bigger using value and economic benefit.
The above is merely preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (5)
1. the method for designing of a high-accuracy voltage comparator; It is characterized in that: adopt the level Four preamplifier; After the prime input signal carried out processing and amplifying, latch regenerative circuit by a back level Latch and signal is amplified to the amplitude that late-class circuit can be discerned through positive feedback; Each inter-stage adopts input imbalance storage and output imbalance storage concatenation technology to eliminate the influence of input offset voltage simultaneously.
2. the method for designing of high-accuracy voltage comparator according to claim 1; It is characterized in that: described input imbalance storage and output imbalance storage concatenation technology are that input offset voltage is stored on the coupling capacitance that each inter-stage is connected, and the high gain characteristics of passing through the preposition amplifier of level Four is less input offset voltage with its equivalence.
3. the method for designing of high-accuracy voltage comparator according to claim 1 is characterized in that: described back level Latch latchs regenerative circuit and also should comprise clock SR latch, to realize that the waveform of this circuit output is carried out shaping.
4. high-accuracy voltage comparator; It is characterized in that: comprise first preamplifier, second preamplifier, the 3rd preamplifier of analogue buffer, biasing circuit, clock control circuit and cascade successively, the 4th preamplifier latchs regenerative circuit with back level Latch; Described first preamplifier, second preamplifier, the 3rd preamplifier, the 4th preamplifier and back level Latch latch and all are connected with coupling capacitance between the regenerative circuit, and described biasing circuit is that level Four preamplifier, clock control circuit and analogue buffer provide bias voltage; Described analogue buffer is used for the input buffering of reference voltage; Described clock control circuit produces the clock control signal of each circuit.
5. high-accuracy voltage comparator according to claim 4 is characterized in that: described back level Latch latchs regenerative circuit and through positive feedback signal is amplified to the amplitude that late-class circuit can be discerned; And the waveform of this regenerative circuit being exported through a clock SR latch carries out shaping.
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| CN2011103762268A CN102394610A (en) | 2011-11-24 | 2011-11-24 | High-precision voltage comparator and design method thereof |
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| CN2011103762268A CN102394610A (en) | 2011-11-24 | 2011-11-24 | High-precision voltage comparator and design method thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102647189A (en) * | 2012-05-22 | 2012-08-22 | 成都启臣微电子有限公司 | Dynamic comparator |
| CN104868886A (en) * | 2015-04-27 | 2015-08-26 | 西安电子科技大学 | Latch comparator |
| CN115033047A (en) * | 2022-06-22 | 2022-09-09 | 福州大学 | Band-gap reference voltage source with single-point calibration |
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| CN202334463U (en) * | 2011-11-24 | 2012-07-11 | 福州大学 | High-accuracy voltage comparator |
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| JPH0722937A (en) * | 1993-07-02 | 1995-01-24 | Nec Ic Microcomput Syst Ltd | Semiconductor integrated circuit |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102647189A (en) * | 2012-05-22 | 2012-08-22 | 成都启臣微电子有限公司 | Dynamic comparator |
| CN102647189B (en) * | 2012-05-22 | 2014-12-10 | 成都启臣微电子有限公司 | Dynamic comparator |
| CN104868886A (en) * | 2015-04-27 | 2015-08-26 | 西安电子科技大学 | Latch comparator |
| CN115033047A (en) * | 2022-06-22 | 2022-09-09 | 福州大学 | Band-gap reference voltage source with single-point calibration |
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Application publication date: 20120328 |