CN103825568B - Automatic gain control system and method thereof - Google Patents
Automatic gain control system and method thereof Download PDFInfo
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Abstract
The invention discloses an automatic gain control system and a method thereof. The gain control unit amplifies an input signal and generates an output signal; the zero crossing monitoring circuit monitors an output signal or an input signal and sends a zero crossing signal when the alternating current of the signal crosses zero; the peak value monitoring circuit outputs an overrun signal when the output signal exceeds a preset value; the logic circuit receives the overrun signal and outputs a digital control signal; and the register writes the digital control signal into the register under the action of the zero crossing signal and outputs the gain control signal.
Description
(the application is the divisional application of 201010254427.6 applications, the filing date of original application on August 16th, 2010,
Entitled " a kind of gain across zero control system and gain across zero control method ")
Technical field
The present invention relates to gain control system and the gain control method of amplifier, particularly relate to the automatic of audio frequency amplifier
Gain control system and auto gain control method.
Background technology
In information processing system, sound is to store with the form of voltage signal and process, due to the loudness of sound mostly
Changing greatly, the voltage audio signal (hereinafter referred to as audio signal) of reflection sound intensity also changes greatly.Fix through gain
Amplifier process after, the part that audio frequency signal amplitude is bigger is exaggerated the power supply of device or amplifier itself limits, output sound
Frequently signal is cut top or cuts the end.Cut top or cut the audio signal distortion factor at the end very greatly, and external equipment may be damaged, for
Solving problems, gain control is during especially automatic gain control is widely used in audio amplifier system.
System shown in Fig. 1 is a kind of single ended input Single-end output gain controller 10.VINIt is the defeated of gain controller 10
Enter signal, VOIt it is the output signal of gain controller 10；Amplifier U1 anode couples bias voltage, bias voltage usual power taking source
Half (hereinafter referred to as VDD/ 2), suppose that bias voltage is entirely V in the following analysisDD/ 2 current potentials；The negative terminal of amplifier U1 passes through
Switch S1, S2, S3 and S4 are couple to resistor network；The outfan of amplifier is the output V of gain controller 10O。
Additional 2 byte digital controlled signal (not shown) so that switch S1, S2, S3 and S4 are in different conductings
(Guan Bi) or cut-off (opening) state, can obtain different gains (referring to table 1), it is achieved that Digital Signals gain becomes
Change.This gain control mode is simple and practical, but there is the problem that abrupt gain causes output signal to be suddenlyd change.
As in figure 2 it is shown, the X-axis of Fig. 2 A (transverse axis) is time signal, Y-axis (longitudinal axis) is input voltage signal, and signal 201 is anti-
Reflect be input voltage signal over time；X-axis (transverse axis) time signal of Fig. 2 B, Y-axis (longitudinal axis) is output voltage letter
Number, signal 202 be output voltage signal over time, dotted line 203 represents output voltage when gain does not change
Waveform.Assuming that in the T1 moment, digital controlled signal changes and reduces the gain of gain controller, and output signal will be disengaged from void
Track shown in line 203, produces a sudden change so that output signal produces the biggest distortion, and causes loading current break,
Cause the damage of external devices.
On off state and gain values under the different control signal of table 1
| Control signal | S1 | S2 | S3 | S4 | Amplifier gain |
| 00 | Cut-off | Cut-off | Cut-off | Conducting | AV=R4/(R0+ R1+ R2+ R3) |
| 01 | Cut-off | Cut-off | Conducting | Cut-off | AV=(R4+ R3)/(R0+ R1+ R2) |
| 10 | Cut-off | Conducting | Cut-off | Cut-off | AV=(R4+ R2+ R3)/(R0+ R1) |
| 11 | Conducting | Cut-off | Cut-off | Cut-off | AV=(R4+ R1+ R2+ R3)/R0 |
Summary of the invention
The purpose of the present invention mainly solves the output signal mutation problems that in gain control unit, change in gain causes, and carries
For a kind of gain across zero control system.
A kind of gain given by the present invention across zero control system, including input, receives input signal；Outfan, produces
Raw output signal；Gain control unit, is coupled to described input and outfan；Across zero observation circuit, it is coupled to described input
End or outfan, monitor described input signal or described output signal, when described input signal or described output signal exchange across
Send across zero-signal when zero；Digital controlled signal end, receives digital controlled signal；And depositor, it is coupled to described numeral control
Signal end processed and described gain control unit, writing depositor, output gain under zero-signal effect by digital controlled signal
Control signal.
A kind of gain of the present invention, across zero control system, farther includes most to capitalize set of time circuit, is coupled to described
Digital controlled signal end, receives described digital controlled signal；Described capitalization set of time circuit is further coupled to described across zero prison
Slowdown monitoring circuit, if described capitalization set of time circuit receives described across zero-signal, then sends write signal, described when capitalizing most
It is not received by described across zero-signal, then in the circuit capitalization time after digital controlled signal changes is set between if
Write signal is sent at the end of the described capitalization time；Described depositor is coupled to described digital controlled signal end, described gain
Control unit and capitalization set of time circuit, write depositor by write signal by digital controlled signal across zero-signal, output
Gain control signal.
The present invention gives and a kind of applies gain across the AGC system of zero control system, also includes monitoring of peak
Circuit, is coupled to described outfan, monitors the size of described output signal, and when output signal exceedes preset value, output is transfinited
Signal；And logic circuit, transfinite described in reception signal, exports described digital controlled signal.
The present invention gives a kind of gain across zero control method simultaneously: receives input signal, uses gain control unit pair
Input signal is amplified, and sends output signal；Input or output signal are exchanged across zero monitoring；Receive digital control
Signal, in input or output signal exchange across zero time, uses the Digital Signals gain control unit being latched.
The gain that the present invention is given also includes across zero control method, the change of monitoring digital controlled signal, digital control letter
In number capitalization time changed, without monitoring input or output signal exchanges across zero, then when capitalizing most
At the end of between, digital signal is latched.
The gain that the present invention is given also includes across zero control method, monitoring of transfiniting output signal, works as output signal
When exceeding preset value, assert the event that transfinites, send the signal that transfinites；And the result according to monitoring of transfiniting, carry out at logic
Reason, reduces or recovers digital controlled signal.
Described voltage jump both can be that voltage signal increases suddenly can also be that voltage signal reduces suddenly.
Described control signal is set of number logical signal, such as: 2 bit digital logical signals 00,01,10 and 11；3
Digital logic signal 000,001,---, 110 and 111.
It is an advantage of the current invention that: each change of gain all occurs at signal near zero, for zero-signal, no matter
Amplifying how many times is all zero, thus eliminates voltage jump.
Accompanying drawing explanation
Fig. 1 illustrates a single ended input Single-end output gain control unit 10.
The output voltage sudden change that Fig. 2 causes when illustrating change in gain when using existing gain control.
Fig. 3 illustrates that gain according to one embodiment of present invention is across zero control system 30.
Fig. 4 illustrates AGC system 40 according to one embodiment of present invention.
Fig. 5 illustrates that gain according to one embodiment of present invention is across zero control system 50.
Fig. 6 illustrates AGC system 60 according to one embodiment of present invention.
Fig. 7 A illustrates Differential Input Single-end output gain control unit 71.
Fig. 7 B illustrates differential-input differential output gain control unit 72.
Fig. 8 A illustrates a single-ended signal 801.
Fig. 8 B illustrates that a kind of embodiment across zero monitoring is across zero observation circuit 81.
Fig. 8 C illustrates a differential signal 804 and 805.
Fig. 8 D illustrates that a kind of embodiment across zero monitoring is across zero observation circuit 82.
Fig. 9 illustrates that a kind of embodiment of capitalization set of time circuit most capitalizes set of time circuit 90.
Figure 10 A illustrates that a kind of spike produces circuit embodiments spike and produces circuit 100.
Figure 10 B illustrates that a kind of spike produces circuit and implements each each node waveform.
Figure 11 illustrates the embodiment register circuit 110 of a kind of register circuit.
Figure 12 A illustrates a single-ended signal 1201.
Figure 12 B illustrates the embodiment monitoring of peak circuit 121 of a kind of monitoring of peak circuit.
Figure 12 C illustrates a differential signal 1204 and 1205.
Figure 12 D illustrates the embodiment monitoring of peak circuit 122 of a kind of monitoring of peak circuit.
Figure 13 illustrates sequential Figure 130 that a kind of logic circuit works.
Detailed description of the invention
Specific embodiment described in the literature represents the exemplary embodiment of the present invention, and be substantially only demonstration and
Unrestricted.In description, " embodiment " or " embodiment " quotes the specific spy meaning to combine described by this embodiment
Levying, structure or characteristic are included at least one embodiment of the present invention.Phrase " in one embodiment " is in the description
Each position occurs not all referring to identical embodiment, is not other embodiments mutually exclusive or various embodiments.
Fig. 3 is across zero control system 30 according to one embodiment of the present of invention gain, including:
Input, receives input signal；Outfan, sends output signal；Digital controlled signal end, receives digital control letter
Numbers 301；Gain control unit 302, is coupled to described input and outfan, determines input letter according to gain control signal 309
Number to the gain of output signal；Across zero observation circuit 303, being coupled to described outfan, monitoring output signal, when output signal is handed over
Stream sends across zero-signal 304 across zero time；Capitalization set of time circuit 305, is coupled to digital controlled signal end, receives numeral control
Signal 301 processed and across zero-signal 304, sends write signal 307.If receive across zero-signal (i.e. output signal occur exchange across
Zero), capitalization set of time circuit 305 sends write signal 307；If when one section of setting of digital controlled signal 301 change
Between in T2, capitalization set of time circuit 305 never receive across zero-signal (i.e. output signal do not occur to exchange across
Zero), then at the end of the T2 time, capitalization set of time circuit 305 sends write signal 307；Depositor 308, couples and numeral
Control signal end and gain control unit, receive digital controlled signal 301, and outputing gain control signal 309, at write signal 307
During effect, digital controlled signal 301 being write depositor and latch, the data being written into and latching are exactly the output of depositor, i.e.
Gain control signal 309.
Capitalization set of time circuit 305, the change of monitoring digital controlled signal 301, and digital controlled signal 301
Trigger after changing.Within time delay, sending out across zero time in output signal across zero observation circuit 303 of monitoring input signal
Go out across zero-signal 304；Capitalization set of time circuit 305 is receiving generation write signal 307 after zero-signal 304.If
In time delay, capitalization set of time circuit 305 is not received by across zero-signal 304, then capitalization set of time circuit
305 send write signal 307 at the end of time delay.Time delay is exactly the described capitalization time.Depositor 308 is receiving
During to write signal 307, latched digital control signal 301 also produces gain control signal 309.Wherein, gain control signal 309 is controlled
Gain control unit 302 processed.When the exchange of signal output signal is across zero time, even if digital controlled signal 301 does not change,
Capitalization set of time circuit 305 can also produce write signal.Now it is not changed in due to digital controlled signal 301, depositor 308
Write signal will not on gain produce impact.
The capitalization time can be zero, it is also possible to endless, it is also possible to outside regulation.When the described capitalization time it is
Zero, digital signal is write depositor by each digital controlled signal moment that changes immediately；When the described capitalization time it is
Endless, each digital controlled signal needs output signal by the time just can digital signal write be deposited across zero after changing
Device.
Such as Fig. 4, a kind of according to the 40 of embodiments of the invention AGC system, including:
Gain is across zero control system 30；Monitoring of peak circuit 401, is coupled to the outfan of 30, monitors described output signal
Size, when output signal exceedes preset value, assert and transfinite event, output is transfinited signal 402；Logic circuit 403, connects
Transfinite described in receipts signal 402, exports digital controlled signal 301, determines reduction according to the signal 402 that transfinites received or recovers
Digital controlled signal 301.
Fig. 5 is across zero control system 50, the system 50 and Fig. 3 institute shown in Fig. 5 according to one embodiment of the present of invention gain
Showing that system 30 is similar, its difference is in system 50, across zero observation circuit 303, is coupled to described input, monitors input signal,
When input signal exchange sends across zero-signal 304 across zero time.
Such as Fig. 6, one is according to embodiments of the invention AGC system 60, the system 60 and Fig. 4 institute shown in Fig. 6
Showing that system 40 is similar, its difference is that system 60 employs embodiment gain across zero control system 50.
The difference of the embodiment 50 shown in embodiment 30 and Fig. 5 shown in Fig. 3 is to couple and outfan across zero monitoring side
Or input, its common ground is all to include gain control unit, capitalization set of time circuit, across zero observation circuit with deposit
Device, hereafter will describe the detailed description of the invention of each functional unit successively.
Gain control unit
The present invention can be for various gain control units, except the gain control unit of single ended input Single-end output shown in Fig. 1 10
Outward, also include but not limited to following several:
Fig. 7 A is an embodiment 71 of Differential Input Single-end output gain controller.In figure, V1+, V1-are Differential Input
Signal, V1 is output signal, and offset signal VB is coupled to VDD/2 current potential.Variable resistance 701 and 702 is respectively coupled to V1+, puts
The anode of big device U2 and VB；Variable resistance 703,704 is respectively coupled to V1-, the negative terminal of amplifier U2 and output V1；Use switch
The method controlling resistance, changes ratio and the ratio of variable resistance 703,704 of variable resistance 701,702, it is achieved digital signal
Control change in gain.
Fig. 7 B is an embodiment 72 of differential-input differential output gain controller.In figure, V2+, V2-are Differential Input
Signal, V3+, V3-are differential output signals, and difference amplifier U3 also has a common mode electrical level (not shown), can take VDD/2 electricity
Position.Variable resistance 705 is coupled between the input anode of V2+ and difference amplifier U3, and variable resistance 706 is coupled to differential amplification
Between input anode and the V3-of device U3；Variable resistance 707 is coupled between the input negative terminal of V2-and difference amplifier U3, variable
Resistance 708 is coupled between input negative terminal and the V3+ of difference amplifier U3；The method using on-off control resistance, changes variable
The ratio of resistance 705,706 and the ratio of variable resistance 707,708, it is achieved Digital Signals change in gain.
For multiterminal (more than or equal to 3) input or output gain control unit, change resistance ratio way all can be used
Change gain.
More multibyte digital signal string can be realized by the way of increasing number of switches and resistor network number control
Gain.
Across zero observation circuit
Across zero, described refers to that output (input) single-ended signal, across zero, is therefore meaned by output (input) signal communication across zero
And just reach to export (input) common mode electrical level.Output (input) differential signal is meaned two differential signal size phases across zero
Deng.
Owing to the delay of amplifier is the least, therefore input across zero moment and output the least, across zero monitoring across zero moment difference
Circuit can monitor input signal or monitoring output signal.For requiring that strict system or the biggest system of delay should
Select monitoring side as required.The present invention both can select to monitor input signal, it is also possible to selects monitoring output signal.
Fig. 8 A illustrates a single-ended signal, X-axis (transverse axis) time, and Y-axis (longitudinal axis) is voltage, and 801 both can be output letter
Number can also be input signal, 802 be that (if i.e. 801 is input signal, 802 is input common mode electricity to corresponding common mode electrical level
Flat；If 801 is output signal, then 802 is output common mode level).Fig. 8 B is corresponding a kind of observation circuit embodiment 81,
S801, S802 represent and couple (sampling) 801 signal, 802 signals, when output (input) signal 801 passes through 802 from the top down, or
Time person passes through 802 from bottom to top, the output signal 815 of comparator 809 all can occur once inside out.
Fig. 8 C is a differential signal, 804,805 both can be input signal can also be output signal, 806 is corresponding
Output (input) common mode electrical level.For differential signal, can appoint and take a signal 804 or 805 in the way of using shown in Fig. 8 B
Compare with common mode electrical level 806.Can also use a kind of observation circuit embodiment 82 shown in Fig. 8 D, S804, S805 represent connection
(sampling) 804 signal, 805 signals, when exporting (input) differential signal 804 and 805 and mutually passing through, the output of comparator 813
Signal 816 all can occur once inside out.
Can represent with the upset of 815,816 in one embodiment and monitor zero state.
For preventing concussion, can monitor across zero state with hysteresis comparator in one embodiment.Due to sluggish existence,
Restriction plus comparator precision, it is impossible to monitor and be entirely zero, generally within tens millivolts.So-called is letter across zero
Number close to zero, owing to signal is the least, suddenly change and the least can ignore.
Capitalization set of time circuit
If monitored signal be zero or the least (within comparator monitoring accuracy, usually tens millis
Volt), across zero monitoring due to sluggish and precision problem, it will locking output state, it is impossible to send across zero-signal.And due to sound
Frequency range distribution very wide, especially under low frequency state, can delay to monitor zero state across zero observation circuit.For solving
Certainly problem above, adds maximum latency circuit, sets maximum latency T2.
Digital controlled signal can change by turn, such as becomes 01 from 10, or 10 become 11, it is also possible to change of jumping,
Such as become 11 from 00.The most preferably monitoring digital signal change is not emphasis of the present invention.It is assumed here that digital control letter
Number only one, each change is all 0 to become 1, or 1 becomes 0.
System 90 shown in Fig. 9 is the embodiment that the capitalization time controls, and 901 and 902 is that two spikes produce
Circuit, its function is to would indicate that the change of zero cross signal or digital controlled signal is converted into spike signal.
Figure 10 A is the embodiment 100 of spike signal generating circuit.1001 is input signal, and 1001 through delay circuit
It is output as 1002,1001 after 1004 and is input to XOR gate 1005, XOR gate 1005 output signal 1003 together with 1002.
XOR gate is conventional numeric door, it is characterized in that the output 0 when two inputs are identical, output when two inputs are different
1, truth table see table 2.
Table 2 XOR truth table
| Input 1 | Input 2 | Output |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 0 | 0 | 1 |
As shown in Figure 10 B, due to the effect of delay circuit 1004, when each 1001 occur upset, signal 1002 is all
Postpone for some time, thus all create a high level pulse at XOR gate 1005 outfan.The time of high level is depended on
In the time delay size of 1004, typically take for tens to hundreds of nanosecond.
System 90 also includes, the D of the delay unit 903 or door 904, band set (reset) that arrange T2 time delay triggers
Device 905.Its function of d type flip flop 905 is as follows: when R end is high level, and outfan Q is 0；When R end is zero, rise at C signal
Edge, transmits D end signal to Q end, and latches.D end (909) is connected to high potential always.
Digital controlled signal changes every time, and spike produces circuit 902 all can produce the first spike at 907 ends, and first
Spike is by set d type flip flop 905, and transmits to 911 ends after the T2 moment.In the process, if spike produces circuit
901 receive across zero-signal, will produce the second spike at 906 ends, spike through or after door 904 arrives 908 ends, trigger
Q end changes, and 910 will produce a rising edge, and this rising edge is exactly write signal；If not monitoring within the T2 time period
To across zero-signal, process or door 904 are passed to the C end of trigger by the first spike signal of 907 so that 910 will produce one
Rising edge, this rising edge is exactly write signal.
In one embodiment, can be set by the way that the signal of 907 end points is set to write signal and most capitalize the time
(the most above-mentioned delay time T2) is zero.In another embodiment, can be by being set to write letter by the signal of 906 end points
Number way set the capitalization time as endless.In another embodiment, can prolonging by regulation delay unit 903
Time time T2 way regulation most capitalize the time.
In one embodiment, capitalization set of time circuit is not used.Can will be coupled directly to post across zero-signal 304
The write signal input of storage.Every time digital controlled signal needs after changing by the time to export or input signal just may be used across zero
So that digital signal is write depositor, capitalization time endless.
Depositor
The function that depositor is to be completed is under write signal effect, by the digital control letter in input signal i.e. native system
Number, it is transferred to outfan (i.e. gain control signal) and latches.D type flip flop, T trigger, latch etc. can serve as depositing
Device uses.In Figure 11, system 110 is exactly a depositor with d type flip flop composition.
1101,1102,1103 is conventional d type flip flop, and its function is: the conduction of D signal is caused Q by the rising edge at C signal
End, and latch.
1104,1105,1106 is register input signal, and 1107,1108,909 is the outfan of depositor, and 1110 are
Write signal.At the rising edge of 1110,1104,1105,1106 signals are conducted cause 1107,1108,1109, and are latched.
Present invention could apply to various occasion, one of them main application is exactly in AGC system.Logical
Crossing above analysis, it will be seen that gain is finally by Digital Signals, automatic growth control is exactly according to output size certainly
The size of dynamic regulation digital controlled signal.Fig. 5 and Fig. 6 is the embodiment of AGC system of the present invention.It mainly adds
Enter monitoring of peak circuit and logic circuit.Monitoring of peak circuit, monitors the size of described output audio signal, when output audio frequency letter
When number exceeding preset value, assert that the event that transfinites, output transfinite signal；Logic circuit determines according to the signal that transfinites received
Progressively reduce or recover digital controlled signal.
Monitoring of peak circuit
Owing to audio signal is AC signal, signal too high too low be all to exceed restriction, optimized monitoring is to signal
Too high too low all it is monitored, it is also possible to only monitoring signal is too high or too low.
Figure 12 A is the waveform of a Single-end output, and transverse axis (X-axis) is the time, and the longitudinal axis (Y-axis) is voltage waveform.1201 are
Output voltage waveforms, 1202 is upper restriction voltage, and 1203 is lower restriction voltage, and in general 1202 and 1203 is about common mode electricity
Pressure VDD/2 symmetry.Output voltage 1201 exceedes (being more than) upper voltage limit 1202 or is less than (being less than) lower voltage limit 1203 all
Mean that output AC voltage exceedes restriction.
System 121 shown in Figure 12 B is a kind of in observation circuit corresponding for 12A, and wherein S1201, S1202, S1203 represent
It is coupled to (sampling) 1201,1202,1203；1209,1210 is comparator；1211 is that commonly use or door, i.e. any one input
Be 1 output 1, two input be simultaneously 0 just export 0 level；When output signal 1201 exceedes the upper limit 1202, comparator 1209
Output switching activity is high level, or the output 1212 of door 1211 also overturns as high level, and the system identification event that transfinites occurs.Work as output
When signal 1201 is less than lower limit 1203, comparator 1210 output switching activity is high level, or the output 1212 of door 1211 also overturns and is
High level, system identification transfinite event occur.
Figure 12 C is the waveform of difference output, and transverse axis (x-axis) is the time, and the longitudinal axis (Y-axis) is voltage waveform.1204,1205 points
Not being corresponding positive and negative terminal output voltage waveforms, 1206,1207 is upper voltage limit and lower voltage limit, 1206,1207 be about
VDD/2 symmetry.For difference output, both can use the monitoring method of Single-end output, appoint and take a signal in 1204,1205
Compare with upper limit lower limit.Can also adopt with the following method: (1) sampling 1204,1205 is compared with upper voltage limit 1206；(2)
Sampling 1204,1205 is compared with lower voltage limit 1207.The system 122 that Figure 12 D is shown samples signal and the upper limit in 1204,1205
It is compared to determine that the event that transfinites occurs.Wherein S1204, S1205, S1206 represent be coupled to (sampling) 1204,1205,
1206；1213,1214 is comparator；1215 is that commonly use or gate logic；When 1204 exceed the upper limit 1206, comparator 1213 is defeated
For high level yes going out upset, or door 1215 exports 1216 also upset is for high level, the system identification event that transfinites occurs.Work as output
1205 less than lower limit 1203 time, comparator 1214 output switching activity be high level yes, or door 1215 export 1216 also upset for height
Level, system identification transfinite event occur.
Comparator 1209,1210,1213,1214 typically uses hysteresis comparator.
In this specification, " (sampling) " expression can be the sampled signal of coherent signal, is not the most coupled directly to relevant letter
Number, and it is coupled to sampling or the sampled signal of coherent signal.
Logic circuit
The signal that transfinites that logic circuit sends according to monitoring of peak circuit, changes the size of digital controlled signal.
Digital controlled signal has initial value, when the event that never transfinites occurs, and the now number of the output of logic circuit
Word control signal initial number control signal.
As shown in figure 13, it is assumed that it is 1100 that digital controlled signal is set in 1100(i.e. initial gain), such as 1301 registrations
The size of word control signal is 1100, i.e. gain is 1100.
Then logic circuit is started working, and performs step 1302 and starts reception and transfinite signal, transfinites without receiving
Signal, then be always maintained at gain 1100, continue to the signal that transfinites；If receiving the signal that transfinites, then perform step 1303, increase
Benefit becomes 1011.
Being absorbed in concussion state for anti-locking system, the gain values after each change in gain should at least keep a time period
T3, can be through but not limited to following two mode: do not receive, in (1) T3 time, the signal that transfinites；(2) logic circuit in the T3 time
The signal that transfinites received is not responding to.Do not receive, in following analysis supposes employing mode (1) the T3 time, the signal that transfinites
Way keeps gain.
After gain 1011 keeps the T3 period, perform step 1304, receive the signal that transfinites: (1) is fixing period period
In T4, being not received by the signal that transfinites, perform step 1301, gain recovery is 1100, after this gain keeps the T3 period, performs step
Rapid 1302, perform subsequent step；(2) receiving the signal that transfinites, then perform step 1305, gain becomes 1010.
After gain 1010 keeps the T3 period, perform step 1306, receive the signal that transfinites: (1) is fixing period period
In T4, being not received by the signal that transfinites, perform step 1303, gain recovery is 1011, after this gain keeps the T3 period, performs step
Rapid 1304, perform subsequent step；(2) receive the signal that transfinites, then perform next step, gain is reduced one.
After performing step 1307, gain becomes 0001.After gain keeps the T3 period, perform step 1308 and receive the letter that transfinites
Number, if the T4 stage thereafter is not received by the signal that transfinites, gain recovery is that 0010(is not shown), if connect in the T4 stage
Receiving the signal that transfinites, gain becomes 0000.
After gain becomes 0000, this gain will keep the T3 period, then perform step 1310, receive the signal that transfinites.If
Being not received by, in the T4 period thereafter, the signal that transfinites, then perform step 1307, gain becomes 0001.If monitoring reception
To the signal that transfinites, gain remains in that to be 0000.
The maximum of gain is exactly initial gain, and under this gain, even if never monitoring the event of transfiniting, gain also will
Remain initial gain, and gain can not be increased.
Gain minimum is 0000, even if monitoring the event of transfiniting under this gain, gain also will keep 0000.
Foregoing invention content and detailed description of the invention are intended to prove the actual application of technical scheme provided by the present invention, should not
It is construed to limiting the scope of the present invention.Those skilled in the art are in spirit and principles of the present invention, various when making
Amendment, equivalent or improvement.Protection scope of the present invention is as the criterion with appended claims.
Claims (13)
1. an AGC system, including:
Input, receives input signal；
Outfan, it is provided that output signal；
Gain control unit, is coupled to described input and outfan, controls gain based on gain control signal；
Across zero observation circuit, it is coupled to described input or outfan, monitors described input signal or described output signal, work as institute
State input signal or the exchange of described output signal sends across zero-signal across zero time；
Monitoring of peak circuit, is coupled to described outfan, monitors the size of described output signal, when described output signal exceedes pre-
If during value, export the signal that transfinites；
Logic circuit, transfinite described in reception signal, exports digital controlled signal, if described logic circuit receives described super
Limited signal, then reduce described digital controlled signal, if being not received by institute in described logic circuit section at a fixed time
State the signal that transfinites, then recover described digital controlled signal；
Digital controlled signal end, receives digital controlled signal；
Capitalization set of time circuit, is coupled to described across zero observation circuit and described digital controlled signal end, based on described number
Word control signal and described produce write signal across zero-signal, if described capitalization set of time circuit receives described across zero letter
Number, then send described write signal；If described capitalization set of time circuit is after described digital controlled signal changes
It is not received by described across zero-signal in the capitalization time, then at the end of the described capitalization time, sends described write signal；With
And
Depositor, is coupled to described digital controlled signal end, described gain control unit and capitalization set of time circuit, in institute
State, under zero-signal effect, described digital controlled signal is write depositor, export described gain control signal.
2. a kind of AGC system, it is characterised in that described gain control unit includes amplifying
Device and resistor network.
3. a kind of AGC system, it is characterised in that the described capitalization time is fixing
Value.
4. a kind of AGC system, it is characterised in that the described capitalization time is adjustable, takes
Value scope is 0 to infinity.
5. a kind of AGC system, it is characterised in that described digital controlled signal is changing
At least keep a set time after change.
6. as claimed in claim 1 a kind of AGC system, it is characterised in that the reduction of described digital controlled signal and
Recover to carry out by turn.
7. a kind of AGC system, it is characterised in that at the beginning of described digital controlled signal is to the maximum
Beginning digital controlled signal；Described digital controlled signal minimum N number of 0, N is positive integer.
8. an auto gain control method, including:
Receive input signal, and described input signal is amplified, send output signal；
Described input signal or described output signal are exchanged across zero monitoring；
Receive digital controlled signal, exchange across zero time in described input signal or described output signal, use described numeral control
Signal processed controls gain control unit；
Described output signal is transfinited monitoring, when described output signal exceedes preset value, send the signal that transfinites；
Monitor the change of described digital controlled signal, within the capitalization time that described digital controlled signal changes, if
Do not monitor described input signal or described output signal exchanges across zero, then by described at the end of the described capitalization time
Digital controlled signal latches；And
According to the result of described monitoring of transfiniting, carry out logical process, reduce or recover described digital controlled signal, wherein said
Logical process include: if monitoring the event of transfiniting, then reduce described digital controlled signal, if at a fixed time in section
Transfinite described in not monitoring event, then recover described digital controlled signal.
9. auto gain control method as claimed in claim 8, it is characterised in that described digital controlled signal is after changing
At least keep a period of time.
10. auto gain control method as claimed in claim 8, it is characterised in that the reduction of described digital controlled signal
Carry out by turn with recovery.
11. a kind of auto gain control methods, it is characterised in that described digital controlled signal is maximum
For initial number control signal；Described digital controlled signal minimum N number of 0, N is positive integer.
12. a kind of auto gain control methods, it is characterised in that the described capitalization time is fixed value.
13. a kind of auto gain control methods, it is characterised in that the described capitalization time is adjustable, value
Scope is 0 to infinity.
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| CN201410066747.7A CN103825568B (en) | 2010-08-16 | 2010-08-16 | Automatic gain control system and method thereof |
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| CN201010254427.6A CN102377398B (en) | 2010-08-16 | 2010-08-16 | Gain zero-crossing control system and gain control method |
| CN201410066747.7A CN103825568B (en) | 2010-08-16 | 2010-08-16 | Automatic gain control system and method thereof |
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| CN106656085B (en) * | 2017-01-20 | 2018-09-25 | 深圳市中移联半导体科技有限公司 | A kind of gain control |
| CN109948786B (en) * | 2019-02-21 | 2021-05-11 | 山东师范大学 | Brain-imitating digital-analog mixed neuron circuit and method |
| CN111225437A (en) * | 2019-11-29 | 2020-06-02 | 博微宇空(重庆)科技有限公司 | Gain control method for receiving signal of ground base station |
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| US6687068B2 (en) * | 2001-03-27 | 2004-02-03 | International Business Machines Corporation | Data reproduction apparatus and method |
| CN1725634A (en) * | 2004-07-23 | 2006-01-25 | 三洋电机株式会社 | Automatic level control circuit with improved attack action |
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| JP4390653B2 (en) * | 2004-07-23 | 2009-12-24 | 三洋電機株式会社 | Automatic level adjustment circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6687068B2 (en) * | 2001-03-27 | 2004-02-03 | International Business Machines Corporation | Data reproduction apparatus and method |
| CN1725634A (en) * | 2004-07-23 | 2006-01-25 | 三洋电机株式会社 | Automatic level control circuit with improved attack action |
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