CN103825568A - Automatic gain control system and method thereof - Google Patents
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Abstract
The invention discloses an automatic gain control system and a method thereof. The gain control unit amplifies an input signal and generates an output signal; the zero crossing monitoring circuit monitors an output signal or an input signal and sends a zero crossing signal when the alternating current of the signal crosses zero; the peak value monitoring circuit outputs an overrun signal when the output signal exceeds a preset value; the logic circuit receives the overrun signal and outputs a digital control signal; and the register writes the digital control signal into the register under the action of the zero crossing signal and outputs the gain control signal.
Description
(the application is the divisional application of 201010254427.6 applications, and the applying date of original application is on August 16th, 2010, and name is called " one gains across zero control system and gains across zero control method ")
Technical field
The present invention relates to gain control system and the gain control method of amplifier, relate in particular to AGC (automatic gain control) system and the auto gain control method of audio frequency amplifier.
Background technology
In information processing system, sound is to store and process with the form of voltage signal mostly, and because the loudness of sound changes greatly, the voltage audio signal (hereinafter to be referred as audio signal) of reflection sound intensity also changes larger.After the amplifier that gains fixing is processed, the part that audio frequency signal amplitude is larger is exaggerated power supply or the amplifier restriction itself of device, and output audio signal is cut top or cut at the end.Cutting top or cut the audio signal distortion factor at the end very large, and may damage external equipment, is to solve problems, and gain control especially automatic gain control is widely used in audio amplifier system.
System shown in Fig. 1 is a kind of single-ended input Single-end output gain controller 10.V
iNthe input signal of gain controller 10, V
oit is the output signal of gain controller 10; Amplifier U1 anode couples bias voltage, and the half in the common power taking of bias voltage source is (hereinafter referred to as V
dD/ 2), suppose that in the following analysis bias voltage is all V
dD/ 2 current potentials; The negative terminal of amplifier U1 is couple to resistor network by switch S 1, S2, S3 and S4; The output of amplifier is the output V of gain controller 10
o.
Additional 2 byte digital controlled signal (not shown), make switch S 1, S2, S3 and S4 in different conducting (closure) or cut-off (opening) state, can obtain different gains (referring to table 1), have realized Digital Signals change in gain.This gain control mode is simple and practical, but exists gain sudden change to cause the problem of output signal sudden change.
As shown in Figure 2, the X-axis of Fig. 2 A (transverse axis) is time signal, and Y-axis (longitudinal axis) is input voltage signal, and what signal 201 reflected is input voltage signal over time; X-axis (transverse axis) time signal of Fig. 2 B, Y-axis (longitudinal axis) is output voltage signal, signal 202 be output voltage signal over time, the waveform of output voltage when dotted line 203 represents that gain does not change.Suppose the moment at T1, digital controlled signal changes and has reduced the gain of gain controller, and output signal will depart from the track shown in dotted line 203, produce a sudden change, make output signal produce very large distortion, and cause current break in load, cause the damage of external devices.
On off state and gain values under the different control signals of table 1
| Control signal | S1 | S2 | S3 | S4 | Amplifier gain |
| 00 | Cut-off | Cut-off | Cut-off | Conducting | A V=R4/（R0+ R1+ R2+ R3） |
| 01 | Cut-off | Cut-off | Conducting | Cut-off | A V=(R4+ R3)/（R0+ R1+ R2） |
| 10 | Cut-off | Conducting | Cut-off | Cut-off | A V=(R4+ R2+ R3)/（R0+ R1） |
| 11 | Conducting | Cut-off | Cut-off | Cut-off | A V=（R4+ R1+ R2+ R3）/ R0 |
Summary of the invention
Object of the present invention is mainly to solve the output signal sudden change problem that in gain control unit, change in gain causes, and provides a kind of gain across zero control system.
The given one of the present invention gains across zero control system, comprising: input, receives input signal; Output, produces output signal; Gain control unit, is coupled to described input and output; Across zero observation circuit, be coupled to described input or output, monitor described input signal or described output signal, when exchanging, described input signal or described output signal send across zero-signal across zero time; Digital controlled signal end, receives digital controlled signal; And register, be coupled to described digital controlled signal end and described gain control unit, under across zero-signal effect, digital controlled signal is write to register, outputing gain control signal.
A kind of gain of the present invention, across zero control system, further comprises and capitalizes set of time circuit most, is coupled to described digital controlled signal end, receives described digital controlled signal; The described set of time circuit of capitalizing most is also coupled to described across zero observation circuit, if capitalizing most set of time circuit described receives described across zero-signal, send write signal, capitalize most if described and in the capitalization time of set of time circuit after digital controlled signal changes, do not receive describedly across zero-signal, in the time that the described capitalization time finishes, send write signal; Described register is coupled to described digital controlled signal end, described gain control unit and capitalizes set of time circuit most, by write signal, digital controlled signal is write to register, outputing gain control signal across zero-signal.
The present invention gives the AGC (automatic gain control) system of a kind of using gain across zero control system, also comprises and is coupled to described output by monitoring of peak circuit, monitors the size of described output signal, in the time that output signal exceedes preset value, exports the signal that transfinites; And logical circuit, the signal that transfinites described in reception, exports described digital controlled signal.
The present invention has provided a kind of gain across zero control method simultaneously: receive input signal, use gain control unit to amplify input signal, send output signal; Input or output signal are exchanged across zero monitoring; Receive digital controlled signal, exchange across 1 o'clock in input or output signal, use the Digital Signals gain control unit being latched.
The gain that the present invention provides also comprises across zero control method, the variation of monitoring digital controlled signal, in the capitalization time that digital controlled signal changes, if do not monitor input or output signal exchanges across zero, in the time that the capitalization time finishes by digital signal latch.
The gain that the present invention provides also comprises across zero control method, to the output signal monitoring of transfiniting, in the time that output signal exceedes preset value, assert the event that transfinites, and sends the signal that transfinites; And according to the result of the monitoring of transfiniting, carry out logical process, reduce or recover digital controlled signal.
Described voltage jump can be both that the unexpected increase of voltage signal can be also that voltage signal reduces suddenly.
Described control signal is set of number logical signal, such as: 2 bit digital logical signals 00,01,10 and 11; 3 bit digital logical signals 000,001,---, 110 and 111.
The invention has the advantages that: each variation of gain all occurs in signal across near zero, and for zero-signal, amplifying how many times is all zero, thereby has removed voltage jump.
Accompanying drawing explanation
Fig. 1 illustrates a single-ended input Single-end output gain control unit 10.
Fig. 2 illustrates the output voltage sudden change causing while adopting change in gain when existing gain control.
Fig. 3 illustrates and gains according to one embodiment of present invention across zero control system 30.
Fig. 4 illustrates AGC (automatic gain control) system 40 according to one embodiment of present invention.
Fig. 5 illustrates and gains according to one embodiment of present invention across zero control system 50.
Fig. 6 illustrates AGC (automatic gain control) system 60 according to one embodiment of present invention.
Fig. 7 A illustrates difference input Single-end output gain control unit 71.
Fig. 7 B illustrates differential-input differential output gain control unit 72.
Fig. 8 A illustrates a single-ended signal 801.
Fig. 8 B illustrates that a kind of embodiment across zero monitoring is across zero observation circuit 81.
Fig. 8 C illustrates a differential signal 804 and 805.
Fig. 8 D illustrates that a kind of embodiment across zero monitoring is across zero observation circuit 82.
Fig. 9 illustrates that a kind of embodiment that capitalizes set of time circuit most capitalizes most set of time circuit 90.
Figure 10 A illustrates that a kind of spike produces circuit embodiments spike and produces circuit 100.
Figure 10 B illustrates that a kind of spike produces circuit and implements each each node waveform.
Figure 11 illustrates a kind of embodiment register circuit 110 of register circuit.
Figure 12 A illustrates a single-ended signal 1201.
Figure 12 B illustrates a kind of embodiment monitoring of peak circuit 121 of monitoring of peak circuit.
Figure 12 C illustrates a differential signal 1204 and 1205.
Figure 12 D illustrates a kind of embodiment monitoring of peak circuit 122 of monitoring of peak circuit.
Figure 13 illustrates sequential Figure 130 of a kind of logical circuit work.
Embodiment
Described specific embodiment represents exemplary embodiment of the present invention in the literature, and in essence only for demonstration is unrestricted.In specification, quoting of " embodiment " or " embodiment " means the described special characteristic in conjunction with this embodiment, and structure or characteristic comprise at least one embodiment of the present invention.Phrase " in one embodiment " each position in specification occurs all not relating to identical embodiment, neither mutually get rid of other embodiment or variable embodiment.
Fig. 3 gains across zero control system 30 according to one embodiment of the present of invention, comprising:
Input, receives input signal; Output, sends output signal; Digital controlled signal end, receives digital controlled signal 301; Gain control unit 302, is coupled to described input and output, determines the gain of input signal to output signal according to gain control signal 309; Across zero observation circuit 303, be coupled to described output, monitoring output signal, sends across zero-signal 304 across zero time when output signal exchanges; Capitalize most set of time circuit 305, be coupled to digital controlled signal end, receive digital controlled signal 301 and across zero-signal 304, send write signal 307.If receive across zero-signal (being that output signal occurs to exchange across zero), capitalize set of time circuit 305 most and send write signal 307; If in the one section of setting-up time T2 changing at digital controlled signal 301, capitalizing most set of time circuit 305 never receives across zero-signal (being that output signal does not occur to exchange across zero),, in the time that the T2 time finishes, capitalize set of time circuit 305 most and send write signal 307; Register 308, couple and digital controlled signal end and gain control unit, receive digital controlled signal 301, outputing gain control signal 309, do the used time at write signal 307 digital controlled signal 301 is write to register latch, the data that are written into also latch are exactly the output of register, i.e. gain control signal 309.
Capitalize most set of time circuit 305, monitoring digital controlled signal 301 variation, and after digital controlled signal 301 changes trigger.Within time of delay, monitor sending across zero-signal 304 across 1 o'clock in output signal across zero observation circuit 303 of input signal; Capitalizing most set of time circuit 305 is receiving across the rear generation write signal 307 of zero-signal 304.If within time of delay, capitalize set of time circuit 305 most and do not receive across zero-signal 304, capitalize so set of time circuit 305 most and in the time that finish time of delay, send write signal 307.Be exactly the described capitalization time time of delay.Register 308 is in the time receiving write signal 307, and latch digital controlled signal 301 also produces gain control signal 309.Wherein, gain control signal 309 ride gain control units 302.When signal output signal exchanges across zero time, even if digital controlled signal 301 does not change, capitalize set of time circuit 305 most and also can produce write signal.Now, because digital controlled signal 301 does not change, the write signal of register 308 can not exert an influence to gain.
Capitalizing most the time can be zero, also can endless, also can outsidely regulate.Be zero when the described capitalization time, each digital controlled signal moment that changes writes register by digital signal immediately; Be endless when the described capitalization time, after each digital controlled signal changes, need output signal by the time just digital signal can be write to register across zero.
As Fig. 4, a kind of according to 40 of embodiments of the invention AGC (automatic gain control) system, comprising:
Gain is across zero control system 30; Monitoring of peak circuit 401, is coupled to 30 output, monitors the size of described output signal, in the time that output signal exceedes preset value, assert the event that transfinites, and exports the signal 402 that transfinites; Logical circuit 403, the signal 402 that transfinites described in reception, output digital controlled signal 301, determines and reduces or recover digital controlled signal 301 according to the signal 402 that transfinites receiving.
Fig. 5 gains across zero control system 50 according to one embodiment of the present of invention, system 50 shown in Fig. 5 is similar with system shown in Figure 3 30, its difference is in system 50, across zero observation circuit 303, be coupled to described input, monitoring input signal, sends across zero-signal 304 across zero time when input signal exchanges.
As Fig. 6, a kind of according to embodiments of the invention AGC (automatic gain control) system 60, the system 60 shown in Fig. 6 is similar with system shown in Figure 4 40, and its difference is that system 60 has been used embodiment to gain across zero control system 50.
The difference of embodiment 50 shown in embodiment 30 shown in Fig. 3 and Fig. 5 is to couple and output or input across zero monitoring side, its common ground be all comprise gain control unit, capitalize set of time circuit most, across zero observation circuit and register, below will narrate successively the embodiment of each functional unit.
Gain control unit
The present invention can, for various gain control units, except single-ended input Single-end output gain control unit 10 shown in Fig. 1, also include but not limited to following several:
Fig. 7 A is an embodiment 71 of difference input Single-end output gain controller.In figure, V1+, V1-are differential input signals, and V1 is output signal, and offset signal VB is coupled to VDD/2 current potential.Variable resistor 701 and 702 is respectively coupled to anode and the VB of V1+, amplifier U2; Variable resistor 703,704 is coupled to respectively negative terminal and the output V1 of V1-, amplifier U2; Adopt the method for switch controlling resistance, change the ratio of variable resistor 701,702 and the ratio of variable resistor 703,704, realize Digital Signals change in gain.
Fig. 7 B is an embodiment 72 of differential-input differential output gain controller.In figure, V2+, V2-are differential input signals, and V3+, V3-are differential output signals, and differential amplifier U3 also has a common mode electrical level (not shown), can get VDD/2 current potential.Variable resistor 705 is coupled between V2+ and the input anode of differential amplifier U3, and variable resistor 706 is coupled between the input anode and V3-of differential amplifier U3; Variable resistor 707 is coupled between V2-and the input negative terminal of differential amplifier U3, and variable resistor 708 is coupled between the input negative terminal and V3+ of differential amplifier U3; Adopt the method for switch controlling resistance, change the ratio of variable resistor 705,706 and the ratio of variable resistor 707,708, realize Digital Signals change in gain.
For multiterminal (being more than or equal to 3) input or output gain control unit, all can adopt and change resistance ratio way change gain.
Can realize the gain of more multibyte digital signal string control by increasing the mode of number of switches and resistor network number.
Across zero observation circuit
Described refers to that across zero output (input) signal communication is across zero, therefore output (input) single-ended signal is meaned and just reaches output (input) common mode electrical level across zero.Output (input) differential signal is meaned to two differential signal equal and opposite in directions across zero.
Because the delay of amplifier is very little, therefore input across zero moment and output and differ very little across zero moment, can monitor input signal or monitoring output signal across zero observation circuit.Should select as required monitoring side for requiring strict system or postponing very large system.The present invention both can select to monitor input signal, also can select monitoring output signal.
Fig. 8 A illustrates a single-ended signal, and X-axis (transverse axis) time, Y-axis (longitudinal axis) is voltage, and 801 can be both that output signal can be also input signal, the 802nd, and (if 801 be input signal, 802 is input common mode electrical level for corresponding common mode electrical level; If 801 is output signal, 802 is output common mode level).Fig. 8 B is corresponding a kind of observation circuit embodiment 81, S801, S802 represent to couple (sampling) 801 signals, 802 signals, when output (input) signal 801 passes through 802 from the top down, or when passing through 802 from bottom to top, all can there is once inside out in the output signal 815 of comparator 809.
Fig. 8 C is a differential signal, and 804,805 can be both that input signal can be also output signal, the 806th, and corresponding output (input) common mode electrical level.For differential signal, can adopt the mode shown in Fig. 8 B, appoint get a signal 804 or 805 and common mode electrical level 806 relatively.Can also adopt a kind of observation circuit embodiment 82 shown in Fig. 8 D, S804, S805 represent to connect (sampling) 804 signals, 805 signals, in the time that output (input) differential signal 804 and 805 passes through mutually, all can there is once inside out in the output signal 816 of comparator 813.
Can represent to monitor nought state with 815,816 upset in one embodiment.
For preventing concussion, can monitor across nought state with hysteresis comparator in one embodiment.Due to sluggish existence, add the restriction of comparator precision, can not monitor and be entirely zero, conventionally in tens millivolts.So-called across zero be signal close to zero, because signal is very little, the I of suddenling change is very to ignore.
Capitalize most set of time circuit
If monitored signal is zero or very little (in comparator monitoring accuracy, being generally tens millivolts), due to sluggishness and precision problem, will lock output state across zero monitoring, cannot send across zero-signal.And due to the frequency range of sound distribute very wide, especially under low frequency state, across the zero observation circuit nought state that can delay to monitor.For overcoming the above problems, add maximum latency circuit, set maximum latency T2.
Digital controlled signal can change by turn, and such as becoming 01 from 10, or 10 become 11, and the variation of also can jumping, such as becoming 11 from 00.How monitoring better digital signal change is not emphasis of the present invention.Suppose that digital controlled signal only has one here, each variation is all 0 to become 1, or 1 becomes 0.
Figure 10 A is the embodiment 100 of spike signal generating circuit.The 1001st, input signal, 1001 are output as 1002,1001 after delay circuit 1004 is input to XOR gate 1005, XOR gate 1005 output signals 1003 together with 1002.
XOR gate is conventional numeric door, it is characterized in that exporting 1 export 0, two input difference in the time that two inputs are identical time, and truth table sees the following form 2.
Table 2 XOR truth table
| Input 1 | |
Output |
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 0 | 0 | 1 |
As shown in Figure 10 B, due to the effect of delay circuit 1004, in the time that each 1001 upset occurs, signal 1002 all postpones for some time, thereby has all produced a high level pulse at XOR gate 1005 outputs.The time of high level is depended on 1004 time delay size, generally gets for tens to a hundreds of nanosecond.
Digital controlled signal changes at every turn, and spike produces circuit 902 all can produce the first spike at 907 ends, and the first spike is set d type flip flop 905, and after the T2 moment, transfers to 911 ends.In this process, if producing circuit 901, spike receives across zero-signal, will produce the second spike at 906 ends, spike through or door 904 arrive after 908 ends, trigger Q end changes, and 910 will produce a rising edge, and this rising edge is exactly write signal; If do not monitored across zero-signal within the T2 time period, the first spike signal of 907 is passed to process or door 904 at the C end of trigger, makes 910 will produce a rising edge, and this rising edge is exactly write signal.
In an embodiment, can capitalize the time (being above-mentioned delay time T2) most by the way setting that is write signal by the signal setting of 907 end points is zero.In another embodiment, can set the capitalization time by the way that is write signal by the signal setting of 906 end points is endless.In another embodiment, can regulate and capitalize the time most by the way of the delay time T2 of adjusting delay unit 903.
In one embodiment, do not use and capitalize set of time circuit most.Can the write signal input of register will be directly coupled to across zero-signal 304.After each digital controlled signal changes, need output by the time or input signal just digital signal can be write to register across zero, capitalize most time endless.
Register
The function that register will complete is under write signal effect, is the digital controlled signal in native system by input signal, is transferred to output (being gain control signal) latch.D type flip flop, T trigger, latch etc. can use as register.In Figure 11, system 110 is exactly a register with d type flip flop composition.
1101, the 1102, the 1103rd, conventional d type flip flop, its function is: the conduction of D signal is caused Q end by the rising edge at C signal, and latch.
1104,1105,1106 is register input signal, the 1107,1108, the 909th, and the output of register, 1110 is write signal.At 1110 rising edge, 1104,1105,1106 signals are caused 1107,1108,1109 by conduction, and are latched.
The present invention can be applied to various occasions, and one of them main application is exactly in AGC (automatic gain control) system.By above analysis, we can see, it is exactly the size that automatically regulates digital controlled signal according to output size that gain is finally subject to Digital Signals, automatic gain control.Fig. 5 and Fig. 6 are the embodiment of AGC (automatic gain control) system of the present invention.It is mainly to add monitoring of peak circuit and logical circuit.Monitoring of peak circuit, monitors the size of described output audio signal, in the time that output audio signal exceedes preset value, assert the event that transfinites, and exports the signal that transfinites; Logical circuit is determined and is progressively reduced or recover digital controlled signal according to the signal that transfinites receiving.
Monitoring of peak circuit
Because audio signal is AC signal, signal too high too low be all to exceed restriction, optimized monitoring is too lowly all to monitor signal is too high, also can a monitor signal too high or too low.
Figure 12 A is the waveform of a Single-end output, and transverse axis (X-axis) is the time, and the longitudinal axis (Y-axis) is voltage waveform.The 1201st, output voltage waveforms, the 1202nd, upper deboost, the 1203rd, lower deboost, in general 1202 and 1203 about common-mode voltage VDD/2 symmetry.Output voltage 1201 exceedes (being greater than) upper voltage limit 1202 or all means that lower than (being less than) lower voltage limit 1203 output AC voltage exceedes restriction.
Figure 12 C is the waveform of difference output, and transverse axis (x axle) is the time, and the longitudinal axis (Y-axis) is voltage waveform.1204,1205 is respectively corresponding positive and negative terminal output voltage waveforms, the 1206, the 1207th, and upper voltage limit and lower voltage limit, the 1206, the 1207th, about VDD/2 symmetry.For difference output, both can adopt the monitoring method of Single-end output, appoint and get in 1204,1205 a signal and upper limit lower limit compares.Also can adopt with the following method: (1) sampling 1204,1205 and upper voltage limit 1206 are relatively; (2) sampling 1204,1205 and lower voltage limit 1207 are relatively.The system 122 of Figure 12 D shown in being samples signal and the upper limit in 1204,1205 and compares to determine that the event that transfinites occurs.Wherein S1204, S1205, S1206 represent to be coupled to (sampling) 1204,1205,1206; 1213,1214 is comparator; 1215 is conventional or gate logic; In the time that 1204 exceed the upper limit 1206, comparator 1213 output switching activities be high level yes, or door 1215 outputs 1216 also upset is for high level, the system identification event that transfinites occurs.When output 1205 is during lower than lower limit 1203, comparator 1214 output switching activities be high level yes, or door 1215 outputs 1216 also upset be high level, the system identification event that transfinites occurs.
The general hysteresis comparator that adopts of comparator 1209,1210,1213,1214.
In this specification, " (sampling) " represents can be the sampled signal of coherent signal, is not directly coupled to coherent signal, and is coupled to sampling or the sampled signal of coherent signal.
Logical circuit
What logical circuit sent according to monitoring of peak circuit transfinite signal, changes the size of digital controlled signal.
Digital controlled signal has initial value, in the time that the event that never transfinites occurs, and the digital controlled signal initial number control signal of the now output of logical circuit.
As shown in figure 13, suppose that it is that initial gain is 1100 that digital controlled signal is set in 1100(), as shown in 1301, the size of digital controlled signal is 1100, gain is 1100.
Then logical circuit is started working, and execution step 1302 starts to receive the signal that transfinites, if do not receive the signal that transfinites, keeps gain 1100 always, continues to receive the signal that transfinites; If receive the signal that transfinites, perform step 1303, gain becomes 1011.
For anti-locking system is absorbed in concussion state, the gain values after each change in gain should at least keep a time period T3, can be through but not limited to following two kinds of modes: in (1) T3 time, do not receive the signal that transfinites; (2) in the T3 time, logical circuit does not respond the signal that transfinites receiving.The way that does not receive the signal that transfinites within following analysis supposition employing mode (1) the T3 time keeps gain.
Gain 1011 kept after the T3 period, and execution step 1304 receives the signal that transfinites: (1) is in a fixing period period T4, do not receive the signal that transfinites, execution step 1301, gain recovery is 1100, this gain kept after the T3 period, and execution step 1302 is carried out subsequent step; (2) receive the signal that transfinites, perform step 1305, gain becomes 1010.
Gain 1010 kept after the T3 period, and execution step 1306 receives the signal that transfinites: (1) is in a fixing period period T4, do not receive the signal that transfinites, execution step 1303, gain recovery is 1011, this gain kept after the T3 period, and execution step 1304 is carried out subsequent step; (2) receive the signal that transfinites, carry out next step, gain is reduced to one.
After execution step 1307, gain becomes 0001.Gain kept after the T3 period, and execution step 1308 receives the signal that transfinites, if do not receive in the T4 stage after this signal that transfinites, gain recovery is that 0010(is not shown), if receive in the T4 stage signal that transfinites, gain becomes 0000.
After gain becomes 0000, this gain will keep the T3 period, then perform step 1310, receive the signal that transfinites.If do not receive the signal that transfinites within the T4 period after this, perform step 1307, gain becomes 0001.Receive if monitored the signal that transfinites, gain still remains 0000.
The maximum of gain is exactly initial gain, and under this gain, even if never monitor the event of transfiniting, gain also will remain initial gain, and can not increase gain.
Gain minimum is 0000, even monitor the event of transfiniting under this gain, gain also will keep 0000.
Foregoing invention content and embodiment are intended to prove the practical application of technical scheme provided by the present invention, should not be construed as limiting the scope of the present invention.Those skilled in the art are in spirit of the present invention and principle, when doing various modifications, be equal to and replace or improve.Protection scope of the present invention is as the criterion with appended claims.
Claims (15)
1. an AGC (automatic gain control) system, comprising:
Input, receives input signal;
Output, provides output signal;
Gain control unit, is coupled to described input and output, based on gain control signal ride gain;
Across zero observation circuit, be coupled to described input or output, monitor described input signal or described output signal, when exchanging, described input signal or described output signal send across zero-signal across zero time;
Monitoring of peak circuit, is coupled to described output, monitors the size of described output signal, in the time that described output signal exceedes preset value, exports the signal that transfinites;
Logical circuit, the signal that transfinites described in reception, output digital controlled signal;
Digital controlled signal end, receives described digital controlled signal; And
Register, is coupled to described digital controlled signal end and described gain control unit, described digital controlled signal is write to register described under across zero-signal effect, exports described gain control signal.
2. a kind of AGC (automatic gain control) system as claimed in claim 1, also comprises:
Capitalize most set of time circuit, be coupled to described across zero observation circuit and described digital controlled signal end, based on described digital controlled signal with describedly produce write signal across zero-signal, capitalize set of time circuit if described most and receive describedly across zero-signal, send described write signal; Capitalize most if described and in the capitalization time of set of time circuit after described digital controlled signal changes, do not receive describedly across zero-signal, in the time that the described capitalization time finishes, send described write signal;
Described register is coupled to described digital controlled signal end, described gain control unit and capitalizes set of time circuit most, describedly by write signal, described digital controlled signal is write to register latch across zero-signal, exports described gain control signal.
3. a kind of AGC (automatic gain control) system as claimed in claim 1 or 2, is characterized in that, described gain control unit comprises amplifier and resistor network.
4. a kind of AGC (automatic gain control) system as claimed in claim 2, is characterized in that, the described capitalization time is fixed value.
5. a kind of AGC (automatic gain control) system as claimed in claim 2, is characterized in that, the described capitalization time is adjustable, and span is 0 to infinity.
6. a kind of AGC (automatic gain control) system as claimed in claim 1, it is characterized in that, if transfinite signal described in described logical circuit receives, reduce described digital controlled signal, the signal if described logical circuit transfinites described in not receiving in section at a fixed time, recovers described digital controlled signal;
Described digital controlled signal at least keeps a set time after changing.
7. a kind of AGC (automatic gain control) system as claimed in claim 6, is characterized in that, the reducing and recover of described digital controlled signal carries out by turn.
8. a kind of AGC (automatic gain control) system as claimed in claim 1, is characterized in that, described digital controlled signal is initial number control signal to the maximum; Described digital controlled signal minimum is that N 0, N is positive integer.
9. an auto gain control method, comprising:
Receive input signal, and described input signal is amplified, send output signal;
Described input signal or described output signal are exchanged across zero monitoring;
Receive digital controlled signal, exchange across 1 o'clock at described input signal or described output signal, use described digital controlled signal ride gain control unit;
To the monitoring of transfiniting of described output signal, in the time that described output signal exceedes preset value, send the signal that transfinites; And
According to the result of the described monitoring of transfiniting, carry out logical process, reduce or recover described digital controlled signal.
10. auto gain control method as claimed in claim 9, is characterized in that, also comprises:
Monitor the variation of described digital controlled signal, in the capitalization time changing at described digital controlled signal, exchange across zero if do not monitor described input signal or described output signal, in the time that the described capitalization time finishes by described digital controlled signal latch.
11. auto gain control methods as claimed in claim 9, is characterized in that, described logical process comprises:
If monitor the event of transfiniting, reduce described digital controlled signal, if transfinite at a fixed time event in section described in not monitoring, recover described digital controlled signal; And
Described digital controlled signal at least keeps a period of time after changing.
12. auto gain control methods as claimed in claim 11, is characterized in that, the reducing and recover of described digital controlled signal carries out by turn.
13. a kind of auto gain control methods as claimed in claim 9, is characterized in that, described digital controlled signal is initial number control signal to the maximum; Described digital controlled signal minimum is that N 0, N is positive integer.
14. a kind of auto gain control methods as claimed in claim 9, is characterized in that, the described capitalization time is fixed value.
15. a kind of auto gain control methods as claimed in claim 9, is characterized in that, the described capitalization time is adjustable, and span is 0 to infinity.
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| CN201410066747.7A CN103825568B (en) | 2010-08-16 | 2010-08-16 | Automatic gain control system and method thereof |
| CN201010254427.6A CN102377398B (en) | 2010-08-16 | 2010-08-16 | Gain zero-crossing control system and gain control method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106656085A (en) * | 2017-01-20 | 2017-05-10 | 深圳市中移联半导体科技有限公司 | Gain control device |
| CN109948786A (en) * | 2019-02-21 | 2019-06-28 | 山东师范大学 | A kind of the numerical model analysis neuron circuit and method of imitative brain |
| CN111225437A (en) * | 2019-11-29 | 2020-06-02 | 博微宇空(重庆)科技有限公司 | Gain control method for receiving signal of ground base station |
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| US6687068B2 (en) * | 2001-03-27 | 2004-02-03 | International Business Machines Corporation | Data reproduction apparatus and method |
| CN1725634A (en) * | 2004-07-23 | 2006-01-25 | 三洋电机株式会社 | Automatic level control circuit with improved attack action |
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| US6687068B2 (en) * | 2001-03-27 | 2004-02-03 | International Business Machines Corporation | Data reproduction apparatus and method |
| CN1725634A (en) * | 2004-07-23 | 2006-01-25 | 三洋电机株式会社 | Automatic level control circuit with improved attack action |
| JP2006041732A (en) * | 2004-07-23 | 2006-02-09 | Sanyo Electric Co Ltd | Automatic level adjusting circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106656085A (en) * | 2017-01-20 | 2017-05-10 | 深圳市中移联半导体科技有限公司 | Gain control device |
| CN109948786A (en) * | 2019-02-21 | 2019-06-28 | 山东师范大学 | A kind of the numerical model analysis neuron circuit and method of imitative brain |
| CN109948786B (en) * | 2019-02-21 | 2021-05-11 | 山东师范大学 | Brain-imitating digital-analog mixed neuron circuit and method |
| CN111225437A (en) * | 2019-11-29 | 2020-06-02 | 博微宇空(重庆)科技有限公司 | Gain control method for receiving signal of ground base station |
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| CN103825568B (en) | 2016-09-14 |
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