CN109948786A - A kind of the numerical model analysis neuron circuit and method of imitative brain - Google Patents
A kind of the numerical model analysis neuron circuit and method of imitative brain Download PDFInfo
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- CN109948786A CN109948786A CN201910129772.8A CN201910129772A CN109948786A CN 109948786 A CN109948786 A CN 109948786A CN 201910129772 A CN201910129772 A CN 201910129772A CN 109948786 A CN109948786 A CN 109948786A
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- 210000002569 neuron Anatomy 0.000 title claims abstract description 46
- 210000004556 brain Anatomy 0.000 title claims abstract description 23
- 238000004458 analytical method Methods 0.000 title claims abstract description 21
- 238000000034 method Methods 0.000 title claims abstract description 13
- 238000009825 accumulation Methods 0.000 claims description 12
- 239000003990 capacitor Substances 0.000 claims description 5
- 210000004027 cell Anatomy 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 3
- 238000005534 hematocrit Methods 0.000 claims 1
- 210000005036 nerve Anatomy 0.000 abstract description 7
- 230000005055 memory storage Effects 0.000 abstract description 4
- 230000006870 function Effects 0.000 abstract description 2
- 238000013528 artificial neural network Methods 0.000 description 3
- 210000001367 artery Anatomy 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000001537 neural effect Effects 0.000 description 1
- 230000035479 physiological effects, processes and functions Effects 0.000 description 1
- GOLXNESZZPUPJE-UHFFFAOYSA-N spiromesifen Chemical compound CC1=CC(C)=CC(C)=C1C(C(O1)=O)=C(OC(=O)CC(C)(C)C)C11CCCC1 GOLXNESZZPUPJE-UHFFFAOYSA-N 0.000 description 1
- 230000005062 synaptic transmission Effects 0.000 description 1
- 210000003462 vein Anatomy 0.000 description 1
Abstract
The invention discloses a kind of numerical model analysis neuron circuit of imitative brain and methods; it include: neuron kernel circuitry, the neuron kernel circuitry includes voltage latch module, output signal and output postpones signal XOR operation module and output pulse signal routing module compared with threshold voltage after sequentially connected input routing module, input pulse voltage integrating meter module, integral.The invention has the advantages that: the logical signals that sequential element " latch " obtains, and can carry out local memory storage；Realize the interim memory storage function of the inside neurons for input signal.Input and output nerve signal can pass through routing configuration, may be connected to upper layer, the neuron of level course or lower layer's network.
Description
Technical field
The invention belongs to the numerical model analysis neuron circuit of Fang Nao working mechanism technical field more particularly to a kind of imitative brain and
Method.
Background technique
Develop for current imitative brain science, a kind of new impulsive neural networks chip is developed and applies with system.
But inventors have found that the imitative brain neuron circuit invented at present is not able to satisfy the demand of impulsive neural networks, need to set
Count a kind of new imitative brain numerical model analysis neuron circuit.
Prior art discloses not answering circuit system for integrate artificial neuron component, forbid in unseasonable
Integral input signals can not at any time integrate input signal.
Prior art discloses the hardware circuits of the analog pulse neuron based on MOS field effect transistor, utilize MOS
Pipe die intends nerve impulse, and control process is complicated, high failure rate.
Therefore, it has been recognised by the inventors that the prior art does not provide the imitative brain numerical model analysis nerve for impulsive neural networks
First circuit, and the internal structure of corresponding imitative brain numerical model analysis neuron circuit.
Summary of the invention
The invention proposes a kind of numerical model analysis neuron circuit of imitative brain and methods, can carry out at any time to input signal
Continuous integral, can not also integrate input signal, input signal is directly compared with threshold voltage.
To achieve the goals above, the present invention adopts the following technical scheme:
A kind of numerical model analysis neuron circuit of imitative brain disclosed in one or more embodiments, comprising: neuron
Kernel circuitry, the neuron kernel circuitry include sequentially connected input routing module, input pulse voltage integrating meter module,
Voltage latch module, output signal and output postpones signal XOR operation module and output compared with threshold voltage after integral
Pulse signal routing module.
Further, further includes: control is set between the input routing module and output pulse signal routing module
Switch bypass, when the control switch bypass is connected, input signal directly passes through control switch and bypasses into output pulse signal
Routing module.
Further, input signal enters neuron kernel circuitry by input routing module；
Alternatively, input signal is directly exported by input routing module and control switch bypass.
Further, the input pulse voltage integrating meter module is switched-capacitor integrator, for realizing to input pulse
The accumulation of voltage signal.
Further, using dynamic comparison latch to input pulse voltage signal accumulation after voltage and threshold voltage into
Row compares, if voltage is greater than threshold voltage after accumulation, neuron is activated, and comparison result is latched.Otherwise, not defeated
Pulse signal out.
Further, voltage output signal of latch module compared with threshold voltage is divided into two-way after the integral, wherein
NOR gate circuit is directly fed into all the way, is in addition fed to NOR gate circuit by delay cell all the way；The NOR gate circuit
Export one section of high level pulse.
A kind of implementation method of the numerical model analysis neuron circuit of imitative brain disclosed in one or more embodiments, packet
It includes:
Pulse voltage signal is accumulated by switched-capacitor integrator, the threshold voltage of voltage and setting after accumulation
It is compared, if the voltage after accumulation is greater than the threshold voltage of setting, exports high level signal, otherwise, export low level
Signal；The signal of output carries out exclusive or calculating with the output signal after setting time postpones, and output a period of time is T's
High level pulse signal.
Further, if pulse voltage signal is without integral, input signal is directly exported.
Compared with prior art, the beneficial effects of the present invention are:
The logical signal that sequential element " latch " obtains can carry out local memory storage；It realizes and input is believed
Number inside neurons interim memory storage function.
Input and output nerve signal can pass through routing configuration, may be connected to upper layer, the nerve of level course or lower layer's network
Member.
Detailed description of the invention
The accompanying drawings constituting a part of this application is used to provide further understanding of the present application, and the application's shows
Meaning property embodiment and its explanation are not constituted an undue limitation on the present application for explaining the application.
Fig. 1 is the structural schematic diagram of imitative brain numerical model analysis neuron circuit.
Specific embodiment
It is noted that described further below be all exemplary, it is intended to provide further instruction to the application.Unless another
It indicates, all technical and scientific terms that the present invention uses have and the application person of an ordinary skill in the technical field
Normally understood identical meanings.
It should be noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
According to the illustrative embodiments of the application.As used herein, unless the context clearly indicates otherwise, otherwise singular shape
Formula be also intended to include plural form, additionally, it should be understood that, when in the present specification use term "comprising" and/or
When " comprising ", existing characteristics, step, operation, device, component and/or their combination are indicated.
Embodiment one
As background technique is introduced, the not no circuit framework about imitative brain numerical model analysis neuron in the prior art,
And the internal structure of corresponding circuits.
In one or more embodiments, it is novel to disclose one kind, as shown in Figure 1, neuron kernel circuitry, neural
First kernel circuitry includes: the input spike pulse signal router being sequentially connected in series, input Spike pulse voltage integral electricity
Road, the dynamic latch comparator being compared with threshold value, output pulse generator and output signal router.
Wherein, spike is nerve impulse signal, belongs to the physiology electric impulse signal of neurotransmission.
The product to input pulse spike voltage can be completed with access switch capacitance integrator by inputting spike pulse signal
It is tired；
Voltage after input spike pulse voltage accumulation is compared with threshold voltage, and Dynamic comparison latch can be used
Device is completed, if voltage is greater than threshold voltage after accumulation, neuron is activated, and comparison result is latched, and is obtained number and is patrolled
Collect level signal；If voltage is less than threshold voltage after cumulative, latched comparator not output pulse signal.
Dynamic latch output signal separates two paths of signals, wherein directly feeding into NOR gate circuit all the way, in addition all the way
It is fed to XOR gate (XOR) again by a series of delay cells (realizing by the cascade phase inverter of even number), by exclusive or meter
One section of high level pulse of output is calculated, as a nerve impulse signal, output is gone out.
High level pulse is output to the neuron of network below by output routing module.
In other embodiment, after inputting spike pulse signal router, before output signal router
Circuit in Parallel Control switch bypass；That is the branch in Fig. 1 where by-passing signal, when the neuron circuit breaks down,
By-passing signal is enabled.
Alternatively, control by-passing signal if input spike pulse signal does not need to be integrated and enable, input signal
The neuron of network below can be directly output to by control switch bypass, at this point, neuron kernel circuitry is bypassed.
Embodiment two
In one or more embodiments, a kind of realization side of imitative brain numerical model analysis neuron circuit structure is disclosed
Method, faint spike pulse voltage enter input routing, and spike pulse voltage signal can enter the neuron kernel circuitry,
Upper layer neuron circuit or lower layer's neuron circuit can also be directly entered.
Concrete methods of realizing is as follows:
Input spike voltage is accumulated by switched-capacitor integrator；Spike voltage into the neuron can be with
Selection (when by-passing signal is not enabled) accumulation is on dynamic comparison latch input capacitance C2；Voltage enters after accumulating on C2
Dynamic latch comparator, Vo are compared with Vth, if Vo > Vth, dynamic comparison latch output Q=1 (meanwhile Q is taken
It is anti-:~Q=0), otherwise, dynamic comparison latch output Q=0 (meanwhile Q is negated :~Q=1)；Export Q signal and delay
The Q signal of (delay time T) carries out exclusive or (XOR gate) afterwards, exports the pulse signal that one section of high level time is T；Export arteries and veins
Signal is rushed by output router, with output pulse signal.
If inputting spike voltage, after being input to input router, do not need to be integrated, then by-passing signal is enabled, defeated
Entering signal can directly export.
Above-mentioned, although the foregoing specific embodiments of the present invention is described with reference to the accompanying drawings, not protects model to the present invention
The limitation enclosed, those skilled in the art should understand that, based on the technical solutions of the present invention, those skilled in the art
The various modifications or changes that can be made are not needed to make the creative labor still within protection scope of the present invention.
Claims (8)
1. a kind of numerical model analysis neuron circuit of imitative brain characterized by comprising neuron kernel circuitry, the neuron
Kernel circuitry includes voltage and threshold voltage after sequentially connected input routing module, input pulse voltage integrating meter module, integral
Compare latch module, output signal and output postpones signal XOR operation module and output pulse signal routing module.
2. a kind of numerical model analysis neuron circuit of imitative brain as described in claim 1, which is characterized in that further include: described
It inputs setting control switch between routing module and output pulse signal routing module to bypass, the control switch bypass is connected
When, input signal directly passes through control switch and bypasses into output pulse signal routing module.
3. a kind of numerical model analysis neuron circuit of imitative brain as claimed in claim 2, which is characterized in that input signal is by defeated
Enter routing module and enters neuron kernel circuitry；
Alternatively, input signal is directly exported by input routing module and control switch bypass.
4. a kind of numerical model analysis neuron circuit of imitative brain as described in claim 1, which is characterized in that the input pulse electricity
Hematocrit sub-module is switched-capacitor integrator, for realizing the accumulation to input pulse voltage signal.
5. a kind of numerical model analysis neuron circuit of imitative brain as described in claim 1, which is characterized in that locked using Dynamic comparison
Voltage after storage accumulates input pulse voltage signal is compared with threshold voltage, if voltage is greater than threshold value electricity after accumulation
Pressure, then neuron is activated, and comparison result is latched.Otherwise, not output pulse signal.
6. a kind of numerical model analysis neuron circuit of imitative brain as described in claim 1, which is characterized in that voltage after the integral
The output signal of latch module is divided into two-way compared with threshold voltage, wherein directly feed into NOR gate circuit all the way, in addition one
Road is fed to NOR gate circuit by delay cell；The NOR gate circuit exports one section of high level pulse.
7. a kind of implementation method of the numerical model analysis neuron circuit of imitative brain characterized by comprising
Pulse voltage signal is accumulated by switched-capacitor integrator, and the threshold voltage of voltage and setting after accumulation carries out
Compare, if the voltage after accumulation is greater than the threshold voltage of setting, export high level signal, otherwise, exports low level signal；
The signal of output carries out exclusive or calculating, the high level that output a period of time is T with the output signal after setting time postpones
Pulse signal.
8. a kind of implementation method of the numerical model analysis neuron circuit of imitative brain as claimed in claim 7, which is characterized in that pulse
If voltage signal is directly exported without integral, input signal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910129772.8A CN109948786B (en) | 2019-02-21 | 2019-02-21 | Brain-imitating digital-analog mixed neuron circuit and method |
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| CN201910129772.8A CN109948786B (en) | 2019-02-21 | 2019-02-21 | Brain-imitating digital-analog mixed neuron circuit and method |
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| CN109948786B CN109948786B (en) | 2021-05-11 |
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| WO2021135502A1 (en) * | 2019-12-30 | 2021-07-08 | 清华大学 | Artificial neuron circuit with plastic threshold |
| CN113361683A (en) * | 2021-05-18 | 2021-09-07 | 山东师范大学 | Biological brain-imitation storage method and system |
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Granted publication date: 20210511 |