CN203224544U - Oscilloscope front-end processing module circuit - Google Patents
Oscilloscope front-end processing module circuit Download PDFInfo
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- CN203224544U CN203224544U CN 201320144537 CN201320144537U CN203224544U CN 203224544 U CN203224544 U CN 203224544U CN 201320144537 CN201320144537 CN 201320144537 CN 201320144537 U CN201320144537 U CN 201320144537U CN 203224544 U CN203224544 U CN 203224544U
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Abstract
The utility model discloses an oscilloscope front-end processing module circuit, comprising an X1/X2 attenuation circuit, an impedance transformation circuit, a program control variable gain amplification circuit, an AC/DC coupling switch circuit, a direct-current level offset circuit, and an output buffer circuit. The AC/DC coupling switch circuit, the X1/X2 attenuation circuit, the impedance transformation circuit, the direct-current level offset circuit, the program control variable gain amplification circuit, and the output buffer circuit are sequentially connected in series to form a loop. Firstly, an input signal passes through the AC/DC coupling switch circuit and the X1/X2 attenuation circuit, and goes through an impedance buffering process conducted by the impedance transformation circuit; then, the input signal passes through the direct-current level offset circuit and is controllably amplified by the program control variable gain amplification circuit; and finally, the input signal is outputted by the output buffer circuit to an ADC. For realizing the conditioning of the input signal by a front-end circuit in an oscilloscope and considering the noise coefficient and the direct-current offset stability after the conditioning of the signal, the optimized signal processing circuit is adopted, thereby achieving the relatively low noise and the relatively good frequency flatness when the front-end processing circuit of the oscilloscope is designed by employing a non-special chip form.
Description
Technical field
The utility model relates to a kind of oscillograph front-end processing modular circuit for the conditioning of oscillograph front end signal, can nurse one's health importing oscillographic signal preferably, to adapt to the input characteristics of ADC.
Background technology
The present age, the basic composition of digital oscilloscope mainly comprised AFE (analog front end), analog to digital converter, data acquisition/storage/signal processing, demonstration and man-machine interface.Wherein first two section has determined oscillograph overwhelming majority performance index, also is oscillographic core place.All be to be determined by the bandwidth of AFE (analog front end) under a lot of situations of oscillographic test signal bandwidth, just directly influenced oscillographic background noise and range.
The adoptable form of AFE (analog front end) has special chip and general-purpose chip to build, and adopts special chip need drop into higher cost, under the consideration of lower cost, adopts general-purpose chip to build.A certain existing oscillograph front-end processing circuit structure is shown in Figure 1, partly is made up of passive attenuation, impedance conversion, optional amplification, variable gain amplification etc.Wherein impedance inverter circuit adopts JFET operational amplifier and JFET to form as shown in Figure 2.
In the above-mentioned technology, impedance inverter circuit adopts JFET amplifier and JFET pipe to form, and the high and low frequency path is inconsistent, and the radio-frequency component of input signal provides buffering by the Q1 among the figure.This kind processing form causes low-and high-frequency to be connected component frequency amplitude-phase response unevenness easily, causes input signal is produced bigger distortion.
In the above-mentioned technology, do not do the direct current offset circuit on the hardware, then when input signal has bigger flip-flop, can't teach accurate processing waveform details under the equal sampling precision.
The utility model content
In order to address the above problem, the purpose of this utility model is, provides a kind of, to solve when adopting non-special chip form to design the oscillograph front-end processing circuit, reaches lower noise and reaches frequency-flat degree preferably.
In order to achieve the above object, the technical solution of the utility model is, a kind of oscillograph front-end processing modular circuit, comprise the X1/X2 attenuator circuit, impedance inverter circuit and Programmable and Variable gain amplifying circuit, also comprise AC/DC coupling commutation circuit, the DC level off-centre circuit, Programmable and Variable and output buffer have AC/DC coupling commutation circuit and the X1/X2 attenuator circuit of input signal process, input signal is carried out the impedance inverter circuit of impedance buffering, the DC level off-centre circuit, again the Programmable and Variable gain amplifying circuit of the controlled amplification of input signal and output buffer are connected successively and form the loop; And export input signal to ADC.
The utility model has been realized in the oscillograph front-end circuit to the conditioning of input signal, and considers and noise figure and direct current offset stability behind the signal condition adopt the signal processing circuit through optimizing.Input signal is earlier through handing over AC/DC coupling commutation circuit and X1/X20 attenuator circuit, and then after impedance inverter circuit cushions, deliver to the DC level off-centre circuit and handle, after sending the Programmable and Variable gain amplifying circuit again to and carrying out controlled amplification, export ADC to through the one-level output buffer.
Wherein, after the DC level migration processing is placed on impedance buffering in the utility model, with amplify in variable gain after carry out the DC level migration processing and compare, the direct current offset scope that can carry out is bigger.
The utility model middle impedance translation circuit adopts single broadband FET input amplifier to handle, and compares compared with using low frequency high input impedance amplifier to add the FET driving, has more flat frequency response, and is littler to the degree of distortion influence that signal is handled.
To adopt model be that the digital control variable gain amplifier of AD8370 is built to variable-gain amplification circuit in the utility model, is that D/A changes dress parallel operation, a kind of device that digital signal is converted to simulating signal compared with using DAC(.The figure place of DAC is more high, and distorted signals is just more little.Sound is also more steady and audible).Control of Voltage voltage-controlled variable gain amplifier is compared, and the amplifier gain degree of stability is higher, can not be subjected to external disturbance and causes variable gain fractionated gain shakiness, thereby can realize better squelch.
As further improvement of the utility model, impedance inverter circuit includes input end and output terminal, and being in series with resistance and model between input end and the output terminal is the hypervelocity voltage feedback-type amplifier of ADA4817-1, and has triode in parallel with resistance.
As further improvement of the utility model, the DC level off-centre circuit includes input end and output terminal, is in series with the current feedback amplifier that resistance and model are AD8009 between input end and the output terminal.
As further improvement of the utility model, the Programmable and Variable gain amplifying circuit includes input end and output terminal, and being in series with resistance and model between input end and the output terminal is the digital control variable gain amplifier of AD8370.
As further improvement of the utility model, output buffer includes input end and output terminal, and the model of connecting between input end and the output terminal is the current feedback amplifier of AD8009.
The beneficial effects of the utility model are, in order to realize in the oscillograph front-end circuit to the conditioning of input signal, and consider noise figure and direct current offset stability behind the signal condition, adopt the signal processing circuit through optimizing.Input signal is earlier through handing over AC/DC coupling commutation circuit and X1/X20 attenuator circuit, and then after impedance inverter circuit cushions, deliver to the DC level off-centre circuit and handle, after sending the Programmable and Variable gain amplifying circuit again to and carrying out controlled amplification, export ADC to through the one-level output buffer; Make when adopting non-special chip form to design the oscillograph front-end processing circuit, reach lower noise and reach frequency-flat degree preferably.
Description of drawings
Fig. 1 is prior art oscillograph front-end processing circuit structural representation.
Fig. 2 is the impedance inverter circuit schematic diagram of prior art oscillograph front-end processing circuit.
Fig. 3 is structured flowchart of the present utility model.
Fig. 4 is AC/DC coupling principle figure of the present utility model.
Fig. 5 is X1/X20 attenuation principle figure of the present utility model.
Fig. 6 is the utility model impedance inverter circuit schematic diagram.
Fig. 7 is DC level off-centre circuit schematic diagram of the present utility model.
Fig. 8 is Programmable and Variable gain amplifying circuit schematic diagram of the present utility model.
Fig. 9 is output buffer schematic diagram of the present utility model.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage are more clear, in conjunction with the following drawings, it are further described, with reference to Fig. 1～Fig. 9.
A kind of oscillograph front-end processing modular circuit, comprise X1/X2 attenuator circuit 2, impedance inverter circuit 3 and Programmable and Variable gain amplifying circuit 5, also comprise AC/DC coupling commutation circuit 1, DC level off-centre circuit 4 and output buffer 6, the AC/DC coupling commutation circuit 1 of input signal process and X1/X2 attenuator circuit 2 are arranged, input signal is carried out the impedance inverter circuit 3, DC level off-centre circuit 4 of impedance buffering, the Programmable and Variable gain amplifying circuit 5 of the controlled amplification of input signal and output buffer 6 connects successively formation loop again; And export input signal to ADC.
The utility model is realized in the oscillograph front-end circuit to the conditioning of input signal, and considers noise figure and direct current offset stability behind the signal condition, adopts the signal processing circuit through optimizing.Input signal is earlier through handing over AC/DC coupling commutation circuit 1 and X1/X20 attenuator circuit 2, and then after impedance inverter circuit 3 cushions, delivering to DC level off-centre circuit 4 handles, after sending Programmable and Variable gain amplifying circuit 5 again to and carrying out controlled amplification, export ADC to through one-level output buffer 6.
Wherein, after the DC level migration processing is placed on impedance buffering in the utility model, with amplify in variable gain after carry out the DC level migration processing and compare, the direct current offset scope that can carry out is bigger.
The utility model middle impedance translation circuit adopts single broadband FET input amplifier to handle, and compares compared with using low frequency high input impedance amplifier to add the FET driving, has more flat frequency response, and is littler to the degree of distortion influence that signal is handled.
Impedance inverter circuit includes input end and output terminal, and being in series with resistance and model between input end and the output terminal is the hypervelocity voltage feedback-type amplifier of ADA4817-1, and has triode in parallel with resistance.
The DC level off-centre circuit includes input end and output terminal, is in series with the current feedback amplifier that resistance and model are AD8009 between input end and the output terminal.
The Programmable and Variable gain amplifying circuit includes input end and output terminal, and being in series with resistance and model between input end and the output terminal is the digital control variable gain amplifier of AD8370.
To adopt models be that the digital control variable gain amplifier of AD8370 is built for variable-gain amplification circuit 5 in the utility model, is that D/A changes dress parallel operation, a kind of device that digital signal is converted to simulating signal compared with using DAC(.The figure place of DAC is more high, and distorted signals is just more little.Sound is also more steady and audible).Control of Voltage voltage-controlled variable gain amplifier is compared, and the amplifier gain degree of stability is higher, can not be subjected to external disturbance and causes variable gain fractionated gain shakiness, thereby can realize better squelch.
Output buffer 6 includes input end and output terminal, and the model of connecting between input end and the output terminal is the current feedback amplifier of AD8009.
The announcement of book and instruction according to the above description, the utility model those skilled in the art can also carry out suitable change and modification to above-mentioned embodiment.Therefore, the embodiment that discloses and describe above the utility model is not limited to also should fall in the protection domain of claim of the present utility model modifications and changes more of the present utility model.In addition, although used some specific terms in this instructions, these terms do not constitute any restriction to the utility model just for convenience of description.
Claims (5)
1. oscillograph front-end processing modular circuit, comprise X1/X2 attenuator circuit, impedance inverter circuit and Programmable and Variable gain amplifying circuit, it is characterized in that, also comprise AC/DC coupling commutation circuit, DC level off-centre circuit, Programmable and Variable and output buffer, the AC/DC coupling commutation circuit of input signal process and X1/X2 attenuator circuit are arranged, input signal is carried out the impedance inverter circuit, DC level off-centre circuit of impedance buffering, the Programmable and Variable gain amplifying circuit of the controlled amplification of input signal and output buffer are connected successively forms the loop again; And export input signal to ADC.
2. oscillograph front-end processing modular circuit according to claim 1, it is characterized in that, impedance inverter circuit includes input end and output terminal, being in series with resistance and model between input end and the output terminal is the hypervelocity voltage feedback-type amplifier of ADA4817-1, and has triode in parallel with resistance.
3. oscillograph front-end processing modular circuit according to claim 1 is characterized in that the DC level off-centre circuit includes input end and output terminal, is in series with the current feedback amplifier that resistance and model are AD8009 between input end and the output terminal.
4. oscillograph front-end processing modular circuit according to claim 1, it is characterized in that, the Programmable and Variable gain amplifying circuit includes input end and output terminal, and being in series with resistance and model between input end and the output terminal is the digital control variable gain amplifier of AD8370.
5. oscillograph front-end processing modular circuit according to claim 1 is characterized in that output buffer includes input end and output terminal, and the model of connecting between input end and the output terminal is the current feedback amplifier of AD8009.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320144537 CN203224544U (en) | 2013-03-27 | 2013-03-27 | Oscilloscope front-end processing module circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320144537 CN203224544U (en) | 2013-03-27 | 2013-03-27 | Oscilloscope front-end processing module circuit |
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| CN203224544U true CN203224544U (en) | 2013-10-02 |
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| CN 201320144537 Expired - Fee Related CN203224544U (en) | 2013-03-27 | 2013-03-27 | Oscilloscope front-end processing module circuit |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104267228A (en) * | 2014-09-30 | 2015-01-07 | 中国电子科技集团公司第四十一研究所 | Circuit allowing trigger sensitivity of digital oscilloscope to be continuously adjustable |
| CN105116362A (en) * | 2015-08-26 | 2015-12-02 | 电子科技大学 | Oscilloscope simulation front end impedance conversion circuit having program control correction function |
| CN107231140A (en) * | 2017-06-07 | 2017-10-03 | 广州致远电子有限公司 | A kind of impedance transformer network circuit structure |
| CN107561431A (en) * | 2017-09-04 | 2018-01-09 | 中国电子科技集团公司第四十研究所 | A kind of efficient modularization oscilloscope analog channel debugging circuit and method |
| CN111413527A (en) * | 2020-05-13 | 2020-07-14 | 深圳市鼎阳科技股份有限公司 | Single-ended active probe for oscilloscope and signal detection system |
| CN113252956A (en) * | 2021-04-08 | 2021-08-13 | 广州致远电子有限公司 | Oscilloscope with ADC linear calibration function |
| CN115290949A (en) * | 2022-07-29 | 2022-11-04 | 普源精电科技股份有限公司 | Analog front end chip and oscilloscope |
-
2013
- 2013-03-27 CN CN 201320144537 patent/CN203224544U/en not_active Expired - Fee Related
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104267228A (en) * | 2014-09-30 | 2015-01-07 | 中国电子科技集团公司第四十一研究所 | Circuit allowing trigger sensitivity of digital oscilloscope to be continuously adjustable |
| CN105116362A (en) * | 2015-08-26 | 2015-12-02 | 电子科技大学 | Oscilloscope simulation front end impedance conversion circuit having program control correction function |
| CN105116362B (en) * | 2015-08-26 | 2017-10-31 | 电子科技大学 | A kind of oscilloscope analog front end impedance inverter circuit with program control calibration function |
| CN107231140A (en) * | 2017-06-07 | 2017-10-03 | 广州致远电子有限公司 | A kind of impedance transformer network circuit structure |
| CN107231140B (en) * | 2017-06-07 | 2020-12-04 | 广州致远电子有限公司 | Impedance transformation network circuit structure |
| CN107561431A (en) * | 2017-09-04 | 2018-01-09 | 中国电子科技集团公司第四十研究所 | A kind of efficient modularization oscilloscope analog channel debugging circuit and method |
| CN107561431B (en) * | 2017-09-04 | 2020-02-04 | 中国电子科技集团公司第四十一研究所 | Efficient test method for debugging circuit of modularized oscilloscope simulation channel |
| CN111413527A (en) * | 2020-05-13 | 2020-07-14 | 深圳市鼎阳科技股份有限公司 | Single-ended active probe for oscilloscope and signal detection system |
| CN111413527B (en) * | 2020-05-13 | 2022-08-16 | 深圳市鼎阳科技股份有限公司 | Single-ended active probe for oscilloscope and signal detection system |
| CN113252956A (en) * | 2021-04-08 | 2021-08-13 | 广州致远电子有限公司 | Oscilloscope with ADC linear calibration function |
| CN115290949A (en) * | 2022-07-29 | 2022-11-04 | 普源精电科技股份有限公司 | Analog front end chip and oscilloscope |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20131002 Termination date: 20190327 |