CN202334447U - Front-mounted equalization amplifying circuit - Google Patents
Front-mounted equalization amplifying circuit Download PDFInfo
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- CN202334447U CN202334447U CN2011204224450U CN201120422445U CN202334447U CN 202334447 U CN202334447 U CN 202334447U CN 2011204224450 U CN2011204224450 U CN 2011204224450U CN 201120422445 U CN201120422445 U CN 201120422445U CN 202334447 U CN202334447 U CN 202334447U
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Abstract
A front-mounted equalization amplifying circuit comprises an equalization control module, an output module, a pole adjustment module and a digital control module. The equalization control module comprises a load submodule, an input submodule, a source end negative feedback submodule and a current source submodule. The load submodule comprises a first resistor and a second resistor, the input submodule comprises a first input end, a first switch element, a second input end and a second switch element, the source end negative feedback submodule comprises a third resistor and a first adjustable capacitor, and the current source submodule comprises a first current source and a second current source. The output module comprises a first output end and a second output end, and the pole adjustment module comprises a second adjustable capacitor and a third adjustable capacitor. The front-mounted equalization amplifying circuit guarantees signal regulating performance of an equalization circuit.
Description
Technical field
The utility model relates to a kind of amplifying circuit, refers to a kind of simple in structure, preposition balanced amplifying circuit that performance is higher especially.
Background technology
Preposition balanced amplifying circuit is widely used in integrated circuit and the system, and particularly the IA High Speed Channel receiving terminal is used for the spectrum component loss of compensated high-speed signal transmission on transmission medium.
In the structure of existing preposition balanced amplifying circuit; When EQ Gain increased, can move its zero point to initial point, owing to dominant pole is that variation along with zero point changes; And secondary point remains unchanged; Therefore the highest-gain frequency of balanced amplifying circuit can move to initial point, makes bigger error to occur at bigger gain Frequency point and less gain frequency point, thereby influences the effect of equalizing circuit.
See also Fig. 1 and Fig. 2, Fig. 1 is the input signal of existing balanced amplifying circuit and the comparison of wave shape figure of output signal, and Fig. 2 is the amplitude-frequency characteristic figure of existing balanced amplifying circuit.When input signal for through the transmission signals behind the short-term medium time, the gain of required equalizing circuit is less, when input signal was the transmission signals behind long line medium, the gain of required equalizing circuit was bigger.As can beappreciated from fig. 2; The highest-gain frequency of existing balanced amplifying circuit is moving to initial point, makes bigger error to occur at bigger gain Frequency point and less gain frequency, therefore can be found out by Fig. 1 and Fig. 2; When the gain of equalizing circuit hour, the output distorted signals is less; When the gain of equalizing circuit was big, the output distorted signals was bigger, thereby had influenced the performance of output signal transfer quality and equalizing circuit conditioning signal.
Summary of the invention
In view of above content, be necessary to provide a kind of simple in structure, preposition balanced amplifying circuit that performance is higher.
A kind of preposition balanced amplifying circuit; Said preposition balanced amplifying circuit comprises that the limit adjustment module and that output module, that a balanced control module, links to each other with said balanced control module is connected between said balanced control module and the said output module is connected in the digital control module between said balanced control module and the said limit adjustment module; Said balanced control module comprises the current source submodule that source end negative feedback submodule and that input submodule, that a load submodule, links to each other with said load submodule links to each other with said input submodule links to each other with said source end negative feedback submodule; Said load submodule comprises one first resistance and one second resistance; Said input submodule comprises first switch element that a first input end, links to each other with said first input end and said first resistance, the second switch element that one second input and links to each other with said second input and said second resistance; Said source end negative feedback submodule comprises that one is connected in the 3rd resistance and one and first tunable capacitor that is connected in parallel of said the 3rd resistance between said first switch element and the said second switch element; Said current source submodule comprises second current source that first current source and that links to each other with said first switch element links to each other with said second switch element; Said output module comprises one first output and one second output, and said limit adjustment module comprises the 3rd tunable capacitor that second tunable capacitor and that links to each other with said first output links to each other with said second output.
Preferably; Said first switch element is one first FET; Said second switch element is one second FET; Said first input end links to each other with the grid of said first FET, said second output of the common connection of an end of the drain electrode of said first FET, said first resistance and an end of said the 3rd tunable capacitor, and the source class of said first FET links to each other with an end of an end of said the 3rd resistance, said first tunable capacitor and an end of said first current source.
Preferably; Said second input links to each other with the grid of said second FET; Said first output of the common connection of one end of the drain electrode of said second FET, said second resistance and an end of said second tunable capacitor, the source class of said second FET links to each other with the other end of the other end of said the 3rd resistance, said first tunable capacitor and an end of said second current source.
Preferably, said first resistance is connected a power end jointly with said second resistance.
Preferably, the common earth terminal that connects of said first current source, said second current source, said second tunable capacitor and said the 3rd tunable capacitor.
Preferably, said digital control module is a coding controller, and an end of said coding controller links to each other with said first tunable capacitor, and the other end of said coding controller links to each other with said second tunable capacitor and said the 3rd tunable capacitor.
Relative prior art, the preposition balanced amplification circuit structure of the utility model is simple, has guaranteed the output signal transfer quality, has eliminated the error between bigger gain Frequency point and less gain frequency point, has guaranteed the performance of equalizing circuit conditioning signal.
Description of drawings
Fig. 1 is the input signal of balanced amplifying circuit in the prior art and the comparison of wave shape figure of output signal.
Fig. 2 is the amplitude-frequency characteristic figure of balanced amplifying circuit in the prior art.
Fig. 3 is the system architecture diagram of the preposition balanced amplifying circuit preferred embodiments of the utility model.
Fig. 4 is the circuit diagram of the preposition balanced amplifying circuit preferred embodiments of the utility model.
Fig. 5 is the input signal of the preposition balanced amplifying circuit preferred embodiments of the utility model and the comparison of wave shape figure of output signal.
Fig. 6 is the amplitude-frequency characteristic figure of the preposition balanced amplifying circuit preferred embodiments of the utility model.
Embodiment
See also Fig. 3, the preposition balanced amplifying circuit preferred embodiments of the utility model comprises that the limit adjustment module and that output module, that a balanced control module, links to each other with this equilibrium control module is connected between this equilibrium control module and this output module is connected in the digital control module between this equilibrium control module and this limit adjustment module.Wherein, this equilibrium control module comprises the current source submodule that source end negative feedback submodule and that input submodule, that a load submodule, links to each other with this load submodule links to each other with this input submodule links to each other with this source end negative feedback submodule.
This load submodule is used for providing the load of needs to this preposition balanced amplifying circuit; This input submodule is used to import a pair of differential signal; This source end negative feedback submodule is used for confirming the z1 at zero point of this preposition balanced amplifying circuit, and the dominant pole p1 of this preposition balanced amplifying circuit is along with the variation of z1 at zero point changes; This current source submodule is used for providing operate as normal needed operating current to this preposition balanced amplifying circuit; This output module is used to export the differential signal after this preposition balanced amplifying circuit of a pair of process is regulated; This limit adjustment module is used for confirming secondary some p2 of this preposition balanced amplifying circuit; This digital control module is controlled this source end negative feedback submodule and this limit adjustment module through the mode of coding simultaneously; Make the variation of secondary some p2 can offset variation, thereby eliminate the error between bigger gain Frequency point and the less gain point frequency by the dominant pole p1 that zero point, z1 caused.
Please consult Fig. 4 simultaneously, Fig. 4 is the physical circuit figure of the preposition balanced amplifying circuit preferred embodiments of the utility model.Wherein, this load submodule comprises one first resistance R 1 and one second resistance R 2; This input submodule comprises first switch element that a first input end INN, links to each other with this first input end INN, the second switch element that one second input INP and links to each other with this second input INP; This source end negative feedback submodule comprises one the 3rd resistance R 3 and one first tunable capacitor C1; This current source submodule comprises one first current source I1 and one second current source I2; This output module comprises one first output OUTN and one second output OUTP; This limit adjustment module comprises one second tunable capacitor C2 and one the 3rd tunable capacitor C3; This digital control module is a coding controller CODE.In this execution mode, this first switch element is one first FET M1, and this second switch element is one second FET M2.In other embodiments, this first switch element and this second switch element can be for having other switch elements or the switching circuit of identical function, and for example, switch element can be replaced by triode.
The physical circuit annexation of the preposition balanced amplifying circuit preferred embodiments of the utility model is following: this first input end INN links to each other with the grid of this first FET M1; The end of the drain electrode of this first FET M1, an end of this first resistance R 1 and the 3rd tunable capacitor C3 connects this second output OUTP jointly, and the source class of this first FET M1 links to each other with the end of an end of the 3rd resistance R 3, this first tunable capacitor C1 and the end of this first current source I1.This second input INP links to each other with the grid of this second FET M2; The end of the drain electrode of this second FET M2, an end of this second resistance R 2 and this second tunable capacitor C2 connects this first output OUTN jointly, and the source class of this second FET M2 links to each other with the other end of the other end of the 3rd resistance R 3, this first tunable capacitor C1 and the end of this second current source I2.The other end of this first resistance R 1 is connected a power end VDD jointly with the other end of this second resistance R 2.The common earth terminal VDD that connects of the other end of the other end of the other end of this first current source I1, this second current source I2, this second tunable capacitor C2 and the other end of the 3rd tunable capacitor C3.The end of this coding controller CODE links to each other with the control end of this first tunable capacitor C1, and the other end of this coding controller CODE links to each other with the control end of this second tunable capacitor C2 and the control end of the 3rd tunable capacitor C3.
The operation principle of the preposition balanced amplifying circuit preferred embodiments of the utility model is following: the common differential signal of importing behind a pair of process transmission line medium that receives of this first input end INN and this second input INP; Circuit structure according to this preposition balanced amplifying circuit; By the 3rd resistance R 3 in this source end negative feedback submodule and the first tunable capacitor C1 acting in conjunction, can confirm the z1 at zero point of transfer function in this preposition balanced amplifying circuit; In this preposition balanced amplifying circuit the dominant pole p1 of transfer function along with zero point z1 variation and change, and confirm jointly by first resistance R 1 and the 3rd resistance R 3 in this source end negative feedback submodule in zero point z1, this load submodule; First resistance R 1 in second tunable capacitor C2 in this limit adjustment module and the 3rd tunable capacitor C3 and this load submodule and 2 actings in conjunction of second resistance R can be confirmed secondary some p2 of transfer function in this preposition balanced amplifying circuit.
Therefore can obtain z1 at zero point, dominant pole p1 and secondary some p2 is respectively:
Wherein, gm represents the mutual conductance of FET.Owing to dominant pole p1 be along with zero point z1 variation do linear change; The gain-adjusted of this preposition balanced amplifying circuit mainly relies on adjusting z1 at zero point and changes; In the utility model; This digital control module is controlled this source end negative feedback submodule and this limit adjustment module through the mode of coding simultaneously; Can control z1 and the variation of secondary some p2 at zero point simultaneously, make the variation of secondary some p2 can offset variation, thereby eliminate the error between bigger gain Frequency point and the less gain point frequency by the dominant pole p1 that zero point, z1 caused.
After this preposition balanced amplifying circuit is regulated the differential signal of input according to the z1 at zero point that obtains, dominant pole p1 and secondary some p2, through a pair of differential signal after this first output OUTN and this second output OUTP output adjusting.
Please continue to consult Fig. 5; Fig. 5 is the input signal of the preposition balanced amplifying circuit of the utility model and the comparison of wave shape figure of output signal; As can beappreciated from fig. 5, when input signal for through the transmission signals behind the short-term medium time, the gain of required equalizing circuit is less; When input signal was the transmission signals behind long line medium, the gain of required equalizing circuit was bigger; Please consult Fig. 6 simultaneously; Fig. 6 is the amplitude-frequency characteristic figure of the preposition balanced amplifying circuit of the utility model; As can be seen from Figure 6, the highest-gain frequency of the preposition balanced amplifying circuit of the utility model remains unchanged, thereby has eliminated the error between bigger gain Frequency point and less gain frequency point; When the gain of equalizing circuit hour, the output distorted signals is less; When the gain of equalizing circuit was big, the output distorted signals was still very little, had guaranteed the performance of output signal transfer quality and equalizing circuit conditioning signal.
The preposition balanced amplification circuit structure of the utility model is simple, has guaranteed the output signal transfer quality, has eliminated the error between bigger gain Frequency point and less gain frequency point, has guaranteed the performance of equalizing circuit conditioning signal.
Claims (6)
1. preposition balanced amplifying circuit; It is characterized in that: said preposition balanced amplifying circuit comprises that the limit adjustment module and that output module, that a balanced control module, links to each other with said balanced control module is connected between said balanced control module and the said output module is connected in the digital control module between said balanced control module and the said limit adjustment module; Said balanced control module comprises the current source submodule that source end negative feedback submodule and that input submodule, that a load submodule, links to each other with said load submodule links to each other with said input submodule links to each other with said source end negative feedback submodule; Said load submodule comprises one first resistance and one second resistance; Said input submodule comprises first switch element that a first input end, links to each other with said first input end and said first resistance, the second switch element that one second input and links to each other with said second input and said second resistance; Said source end negative feedback submodule comprises that one is connected in the 3rd resistance and one and first tunable capacitor that is connected in parallel of said the 3rd resistance between said first switch element and the said second switch element; Said current source submodule comprises second current source that first current source and that links to each other with said first switch element links to each other with said second switch element; Said output module comprises one first output and one second output, and said limit adjustment module comprises the 3rd tunable capacitor that second tunable capacitor and that links to each other with said first output links to each other with said second output.
2. preposition balanced amplifying circuit as claimed in claim 1; It is characterized in that: said first switch element is one first FET; Said second switch element is one second FET; Said first input end links to each other with the grid of said first FET; Said second output of the common connection of one end of the drain electrode of said first FET, said first resistance and an end of said the 3rd tunable capacitor, the source class of said first FET links to each other with an end of an end of said the 3rd resistance, said first tunable capacitor and an end of said first current source.
3. preposition balanced amplifying circuit as claimed in claim 2; It is characterized in that: said second input links to each other with the grid of said second FET; Said first output of the common connection of one end of the drain electrode of said second FET, said second resistance and an end of said second tunable capacitor, the source class of said second FET links to each other with the other end of the other end of said the 3rd resistance, said first tunable capacitor and an end of said second current source.
4. preposition balanced amplifying circuit as claimed in claim 1 is characterized in that: said first resistance is connected a power end jointly with said second resistance.
5. preposition balanced amplifying circuit as claimed in claim 1 is characterized in that: the common earth terminal that connects of said first current source, said second current source, said second tunable capacitor and said the 3rd tunable capacitor.
6. preposition balanced amplifying circuit as claimed in claim 1; It is characterized in that: said digital control module is a coding controller; One end of said coding controller links to each other with said first tunable capacitor, and the other end of said coding controller links to each other with said second tunable capacitor and said the 3rd tunable capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011204224450U CN202334447U (en) | 2011-10-31 | 2011-10-31 | Front-mounted equalization amplifying circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011204224450U CN202334447U (en) | 2011-10-31 | 2011-10-31 | Front-mounted equalization amplifying circuit |
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| Publication Number | Publication Date |
|---|---|
| CN202334447U true CN202334447U (en) | 2012-07-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011204224450U Withdrawn - After Issue CN202334447U (en) | 2011-10-31 | 2011-10-31 | Front-mounted equalization amplifying circuit |
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| CN (1) | CN202334447U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102394584A (en) * | 2011-10-31 | 2012-03-28 | 四川和芯微电子股份有限公司 | Preposed equalization amplifying circuit and reposed equalization amplifying system |
-
2011
- 2011-10-31 CN CN2011204224450U patent/CN202334447U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102394584A (en) * | 2011-10-31 | 2012-03-28 | 四川和芯微电子股份有限公司 | Preposed equalization amplifying circuit and reposed equalization amplifying system |
| CN102394584B (en) * | 2011-10-31 | 2014-06-11 | 四川和芯微电子股份有限公司 | Preposed equalization amplifying circuit and reposed equalization amplifying system |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee | ||
| CP02 | Change in the address of a patent holder |
Address after: 610041 Sichuan city of Chengdu province high tech Zone Kyrgyzstan Road 33 block A No. 9 Patentee after: IPGoal Microelectronics (Sichuan) Co., Ltd. Address before: 402 room 7, building 610041, incubator Park, hi tech Zone, Sichuan, Chengdu Patentee before: IPGoal Microelectronics (Sichuan) Co., Ltd. |
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| AV01 | Patent right actively abandoned |
Granted publication date: 20120711 Effective date of abandoning: 20140611 |
|
| RGAV | Abandon patent right to avoid regrant |