CN104333524A - Novel high-speed serial interface transmitter - Google Patents
Novel high-speed serial interface transmitter Download PDFInfo
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- CN104333524A CN104333524A CN201410641518.3A CN201410641518A CN104333524A CN 104333524 A CN104333524 A CN 104333524A CN 201410641518 A CN201410641518 A CN 201410641518A CN 104333524 A CN104333524 A CN 104333524A
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate
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Abstract
The invention discloses a novel high-speed serial interface transmitter. The transmitter comprises a combiner, a voltage-mode driver, a feed-forward equalizer and a feedback equalizer, wherein the feed-forward equalizer is integrated in the voltage-mode driver, an input end is connected with high-speed code stream serial data output by the combiner, and output impedance and an equilibrium factor can be independently adjusted; the feedback equalizer comprises a low-pass filter and a transconductance stage circuit which are both connected with an output end of the voltage-mode driver; the low-pass filter is used for extracting a low-frequency component of the high-speed data code stream output by the voltage-mode driver; the transconductance stage is simultaneously connected with the output of the low-pass filter; output voltage of the low-pass filter is converted into current, and the current and the output current of the voltage-mode driver are summated. The feed-forward equalizer is combined with the feedback equalizer, so that the skin effect attenuation and the dielectric loss attenuation are compensated through feedback and feed-forward respectively, meanwhile equilibrium is realized, and the power consumption of the transmitter is greatly reduced.
Description
Technical field
The invention belongs to circuit design and technical field of data transmission, particularly a kind of novel HSSI High-Speed Serial Interface transmitter.
Background technology
HSSI High-Speed Serial Interface transceiver is widely used in wired data transfer.Transmitter is sent on transmission channel after multidiameter delay data are closed road.Receiver from Received signal strength transmission channel also along separate routes, continues process for circuit below.
The data transfer rate of High Speed Serial transceiver transmission in recent years constantly rises, and HSSI High-Speed Serial Interface data transfer rate commercial at present can reach 28Gbps.The design of the data bit rate promoted gradually to HSSI High-Speed Serial Interface transmitter proposes many challenges.Wherein, comparatively serious challenge is that the data flow transmission in the channel of high-transmission code check receives serious high frequency attenuation.These high frequency attenuations mainly come from two aspects, are dielectric loss and skin effect respectively.The high frequency attenuation caused by dielectric loss can use traditional equalizer to compensate, such as feed forward equalizer (FFE).But the decay caused by skin effect cannot compensate with traditional equalization methods such as FFE.This is that decay owing to being caused by skin effect has an impact usually lower frequency just, and this frequency is relevant with the concrete characteristic of channel, normally tens of megahertz.Meanwhile, the decay caused by skin effect has very slow slope at low frequency, is usually less than 4dB/dec.And FFE only can provide the attenuation compensation of steeper 20dB/dec on its zero frequency.Therefore the decay caused by skin effect needs to carry out extra equilibrium.
In addition, along with the lifting of code check, the power consumption of transmitter promotes gradually.The driver of usual transmitter can consume a large amount of power consumption.The driver of current-mode and the driver Chang Zuowei line drive of voltage-mode are used in transmitter.It is easy to control that current-mode driver has impedance, and equilibrium easily realizes, the advantages such as impedance and equalizing coefficient independent regulation, but the power consumption consumed is larger.The power consumption of the driver of voltage-mode is lower.When output voltage amplitude is consistent, the power consumption of driver of voltage-mode is well below current-mode driver.But the driver of voltage-mode has the shortcoming of impedance matching and equalizing coefficient not easily independent regulation.
Summary of the invention
In order to overcome the shortcoming of above-mentioned prior art, the object of the present invention is to provide a kind of novel HSSI High-Speed Serial Interface transmitter, this transmitter equalizer have employed feed forward equalization and is combined with feedback equalization, the structure that current-mode driver is combined with voltage-mode driver, skin-effect attenuation and dielectric loss decay can be compensated respectively by feedback and feedforward, obtain equilibrium simultaneously; Meanwhile, the structure adopting voltage-mode and current-mode driver to combine, substantially reduces the power consumption of transmitter.
To achieve these goals, the technical solution used in the present invention is:
A kind of novel HSSI High-Speed Serial Interface transmitter, comprise mixer and voltage-mode driver, also comprise feed forward equalizer and feedback equalizer simultaneously, described feed forward equalizer is integrated in voltage-mode driver, input connects the high-speeld code-flow serial data that mixer exports, and independent regulation can be carried out to output impedance and equalizing coefficient, described feedback equalizer comprises the low pass filter and transconductance stage circuit that are all connected to voltage-mode driver output end, the low-frequency component of wherein said low pass filter to the high data rate bit stream that voltage-mode driver exports extracts, described transconductance stage connects described low pass filter simultaneously and exports, the output voltage of described low pass filter is converted into electric current by it, and the output current of this electric current and described voltage-mode driver is sued for peace.
It is multipath high-speed difference bit stream MAINP/MAINN and POSTP/POSTN that the parallel data of multi-path low speed is closed road by described mixer, wherein POSTP/POSTN is obtained by MAINP/MAINN time delay data symbol width, and MAINP/MAINN and POSTP/POSTN is respectively as two inputs of two tap feed forward equalizers.
Described mixer is connected with a clock generating module for generation of clock signal required for conjunction road at different levels in mixer.
Preferably, described voltage-mode driver is made up of 22 actuator units, wherein, wherein the data input of 15 actuator units is connected to MAINP/MAINN, the data input of another 7 actuator units is connected to POSTP/POSTN, the positive connecting the actuator unit of MAINP/MAINN exports and is connected with the anti-phase output of the actuator unit being connected POSTP/POSTN, the anti-phase output connecting the actuator unit of MAINP/MAINN exports with the positive of the actuator unit being connected POSTP/POSTN and is connected, thus form the feed forward equalizer of two taps, the Input Control Word UP_RES<0:3> of each actuator unit, DN_RES<0:3> regulates pull-up and the pull down resistor of each actuator unit respectively, SLICE_EN_MAIN<0:3> and SLICE_EN_POST<0:2> controls the switch of each actuator unit and then controls the equalizing coefficient of feed forward equalization device.Have in described 22 actuator units 15 in running order, the output impedance of each actuator unit is 750 ohm, when opening a unit being connected to MAINP/MAINN and then close the unit of the POSTP/POSTN that ins succession, when keeping output impedance constant, complete the adjustment to equalizing coefficient.
Described each actuator unit is made up of two adjustable inverters of output impedance, the data input of actuator unit is the differential signal of a pair CMOS logic, the output impedance of actuator unit is regulated and is realized by configuration parallel transistor size, the size of parallel transistor is controlled by 4bit binary code UP_RES<0:3> and DN_RES<0:3>, and then distinguish pull-up and the pull-down impedance of adjusting driver unit, SLICE_EN controls the operating state of actuator unit, when SLICE_EN control and drive system unit is in off state, its output impedance is approximately infinitely great.
Described low pass filter is configurable by frequency, and its concrete numerical value, between 10MHz to 1GHz, is determined by concrete channel.Described low pass filter is active low-pass filter, the current mode logic amplifier architecture that this filter inputs based on PMOS, and by being configured switched capacitor array and then output load capacitance being configured to the adjustment realized its cut-off frequency, and utilize source degeneracy resistance R
degimprove the linearity of this low pass filter.
Described transconductance stage is based on the structure of current steer, comprise the first metal-oxide-semiconductor, the second metal-oxide-semiconductor and the 3rd metal-oxide-semiconductor, the grid of the first metal-oxide-semiconductor and the grid of the second metal-oxide-semiconductor connect the two ends of described low pass filter difference output respectively, the drain electrode of the first metal-oxide-semiconductor and the drain electrode of the second metal-oxide-semiconductor connect the two ends of the difference output of described voltage-mode driver respectively, 3rd metal-oxide-semiconductor as current source, the source electrode of its drain electrode connection first metal-oxide-semiconductor and source electrode of the second metal-oxide-semiconductor.
Compared with prior art, the transmitter that the present invention proposes have employed feed forward equalization and is combined with feedback equalization, the structure that current-mode driver is combined with voltage-mode driver, can carry out isostatic compensation simultaneously to skin-effect attenuation and dielectric loss decay and reduce transmitter power consumption.Meanwhile, utilize voltage-mode driver, independent regulation can be carried out to impedance matching and equalizing coefficient.
Accompanying drawing explanation
Fig. 1 is the transmitter architecture schematic diagram proposed.
Fig. 2 is the schematic diagram that a kind of feed forward equalization realizes.
Fig. 3 is the circuit diagram of actuator unit in Fig. 2.
Fig. 4 is that the one of low pass filter and transconductance device in Fig. 1 may circuit embodiments.
Embodiment
Below in conjunction with accompanying drawing and embodiment, preferred embodiment is elaborated.It is emphasized that following explanation is only exemplary, instead of in order to limit the scope of the invention and apply.
As shown in Figure 1, a kind of novel HSSI High-Speed Serial Interface transmitter, comprises mixer, clock generating module, voltage-mode driver, low pass filter, transconductance stage etc.Wherein mixer is responsible for the parallel data of multi-path low speed to close road is the high-speed serial data of two-pass DINSAR: MAINP/MAINN and POSTP/POSTN.Wherein POSTP/POSTN is by obtaining MAINP/MAINN time delay data symbol width.Clock generating module in charge produces the clock signal in mixer required for conjunction road at different levels.It should be noted that mixer can export the high-speeld code-flow of more multichannel in order to realize more multitap feed forward equalization here.Mixer and clock generation circuit are the common circuit in HSSI High-Speed Serial Interface transmitter, realize, do not illustrate at this by various ways.
Voltage-mode driver is integrated with a feed forward equalizer, independent regulation can be carried out to impedance matching and equalizing coefficient, MAINP/MAINN, POSTP/POSTN will be used as the input of feed forward equalizer two taps, the decay that feed forward equalizer main compensation dielectric loss causes.Transmitter contains a low pass filter for extracting the low-frequency component exporting high data rate bit stream.The cut-off frequency of low pass filter can be configured for the special letter of different channels.It is usually lower by frequency, can be configured between 10MHz to 1GHz.The low-frequency component of low pass filter to the high data rate bit stream that voltage-mode driver exports extracts, and the photovoltaic conversion that low pass filter exports by transconductance stage is electric current and sues for peace with the output current of voltage-mode driver.Due to the existence of low pass filter, the electric current that transconductance stage exports only has low-frequency component.This part low-frequency component deducts from final output stream, thus relatively improve the radio-frequency component of data flow, thus the equilibrium decay caused by skin effect.
Fig. 2 is a kind of theory diagram realizing the voltage-mode driver of two tap feed forward equalization.This driver comprises 22 actuator units, also can comprise more actuator unit.Wherein 15 actuator units are connected to MAINP/MAINN, and another 7 actuator units are connected to POSTP/POSTN.It should be noted that the number of actuator unit should change with the tap number of the precision of equilibrium and equalizer, the actuator unit number indicated in figure is just as example.
The positive connecting the actuator unit of MAINP/MAINN exports and is connected with the anti-phase output of the actuator unit being connected POSTP/POSTN, and the anti-phase output connecting the actuator unit of MAINP/MAINN exports with the positive of the actuator unit being connected POSTP/POSTN and is connected.Their feed forward equalizer connecting and composing two taps.Control word input UP_RES<0:3>, the DN_RES<0:3> of actuator unit regulate pull-up and the pull down resistor of each actuator unit respectively.SLICE_EN_MAIN<0:3> and SLICE_EN_POST<0:2> controls the switch of each actuator unit and then controls the equalizing coefficient of feed forward equalization.For Fig. 2, in specific works, one to have 15 actuator units in running order, and the output impedance of each actuator unit is 750 ohm.When opening a unit being connected to MAINP/MAINN and then close the unit of the POSTP/POSTN that ins succession, when keeping output impedance constant, complete the adjustment to equalizing coefficient.
Fig. 3 is that the one of the actuator unit shown in Fig. 2 may realize, and is made up of two adjustable inverters of output impedance.Its data input is the differential signal of a pair CMOS logic.It is realized by configuration parallel transistor size that the output impedance of actuator unit regulates.The size of parallel transistor is controlled by 4bit binary code UP_RES<0:3> and DN_RES<0:3>, and then distinguishes pull-up and the pull-down impedance of adjusting driver unit.SLICE_EN controls the operating state of actuator unit, and when SLICE_EN control and drive system unit is in off state, its output impedance is approximately infinitely great.
Fig. 4 is a kind of circuit realiration of the low pass filter shown in Fig. 1 and transconductance stage.This low pass filter is an active low-pass filter, and is the current mode logic amplifier architecture based on PMOS input.The adjustment of this low pass filter cutoff frequency is by C<0>, C<1>, ..C<5> to be configured and then output load capacitance is configured and realize, its concrete numerical value, between 10MHz to 1GHz, is determined by concrete channel.Source degeneracy resistance Rdeg is used for improving the linearity of this low pass filter.The output of transconductance stage is connected to the output of voltage-mode driver, and the output voltage of low pass filter is converted into electric current and sues for peace with the output current of voltage-mode driver by it, completes the isostatic compensation to Frequency Power Loss.On circuit realiration, this transconductance stage can based on the structure of current steer, comprise the first metal-oxide-semiconductor, the second metal-oxide-semiconductor and the 3rd metal-oxide-semiconductor, the grid of the first metal-oxide-semiconductor and the grid of the second metal-oxide-semiconductor connect the two ends of the difference output of described low pass filter respectively, the drain electrode of the first metal-oxide-semiconductor and the drain electrode of the second metal-oxide-semiconductor connect the two ends of the difference output of described voltage-mode driver respectively, 3rd metal-oxide-semiconductor as current source, the source electrode of its drain electrode connection first metal-oxide-semiconductor and source electrode of the second metal-oxide-semiconductor.
The above; be only the present invention's preferably embodiment, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; the change that can expect easily or replacement, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.
Claims (9)
1. a novel HSSI High-Speed Serial Interface transmitter, comprise mixer and voltage-mode driver, it is characterized in that, comprise feed forward equalizer and feedback equalizer simultaneously, described feed forward equalizer is integrated in voltage-mode driver, input connects the high-speeld code-flow serial data that mixer exports, and independent regulation can be carried out to output impedance and equalizing coefficient, described feedback equalizer comprises the low pass filter and transconductance stage circuit that are all connected to voltage-mode driver output end, the low-frequency component of wherein said low pass filter to the high data rate bit stream that voltage-mode driver exports extracts, described transconductance stage connects described low pass filter simultaneously and exports, the output voltage of described low pass filter is converted into electric current by it, and the output current of this electric current and described voltage-mode driver is sued for peace.
2. HSSI High-Speed Serial Interface transmitter novel according to claim 1, it is characterized in that, it is multipath high-speed difference bit stream MAINP/MAINN and POSTP/POSTN that the parallel data of multi-path low speed is closed road by described mixer, wherein POSTP/POSTN is obtained by MAINP/MAINN time delay data symbol width, and MAINP/MAINN and POSTP/POSTN is respectively as two inputs of two tap feed forward equalizers.
3. HSSI High-Speed Serial Interface transmitter novel according to claim 1 or 2, is characterized in that, described mixer is connected with a clock generating module for generation of clock signal required for conjunction road at different levels in mixer.
4. HSSI High-Speed Serial Interface transmitter novel according to claim 2, it is characterized in that, described voltage-mode driver is made up of 22 actuator units, wherein, wherein the data input of 15 actuator units is connected to MAINP/MAINN, the data input of another 7 actuator units is connected to POSTP/POSTN, the positive connecting the actuator unit of MAINP/MAINN exports and is connected with the anti-phase output of the actuator unit being connected POSTP/POSTN, the anti-phase output connecting the actuator unit of MAINP/MAINN exports with the positive of the actuator unit being connected POSTP/POSTN and is connected, thus form the feed forward equalizer of two taps, the Input Control Word UP_RES<0:3> of each actuator unit, DN_RES<0:3> regulates pull-up and the pull down resistor of each actuator unit respectively, SLICE_EN_MAIN<0:3> and SLICE_EN_POST<0:2> controls the switch of each actuator unit and then controls the equalizing coefficient of feed forward equalizer.
5. HSSI High-Speed Serial Interface transmitter novel according to claim 4, it is characterized in that, have in described 22 actuator units 15 in running order, the output impedance of each actuator unit is 750 ohm, when opening a unit being connected to MAINP/MAINN and then close the unit of the POSTP/POSTN that ins succession, when keeping output impedance constant, complete the adjustment to equalizing coefficient.
6. HSSI High-Speed Serial Interface transmitter novel according to claim 4 or 5, it is characterized in that, described each actuator unit is made up of two adjustable inverters of output impedance, the data input of actuator unit is the differential signal of a pair CMOS logic, the output impedance of actuator unit is regulated and is realized by configuration parallel transistor size, the size of parallel transistor is controlled by 4bit binary code UP_RES<0:3> and DN_RES<0:3>, and then distinguish pull-up and the pull-down impedance of adjusting driver unit, SLICE_EN controls the operating state of actuator unit, when SLICE_EN control and drive system unit is in off state, its output impedance is approximately infinitely great.
7. HSSI High-Speed Serial Interface transmitter novel according to claim 1, is characterized in that, described low pass filter is configurable by frequency, and its concrete numerical value, between 10MHz to 1GHz, is determined by concrete channel.
8. HSSI High-Speed Serial Interface transmitter novel according to claim 1 or 7, it is characterized in that, described low pass filter is active low-pass filter, the current mode logic amplifier architecture that this filter inputs based on PMOS, the adjustment of its cut-off frequency realizes by being configured switched capacitor array and then being configured output load capacitance, and utilizes source degeneracy resistance R
degimprove the linearity of this low pass filter.
9. HSSI High-Speed Serial Interface transmitter novel according to claim 8, it is characterized in that, described transconductance stage is based on the structure of current steer, comprise the first metal-oxide-semiconductor, the second metal-oxide-semiconductor and the 3rd metal-oxide-semiconductor, the grid of the first metal-oxide-semiconductor and the grid of the second metal-oxide-semiconductor connect the two ends of described low pass filter difference output respectively, the drain electrode of the first metal-oxide-semiconductor and the drain electrode of the second metal-oxide-semiconductor connect the two ends of the difference output of described voltage-mode driver respectively, 3rd metal-oxide-semiconductor as current source, the source electrode of its drain electrode connection first metal-oxide-semiconductor and source electrode of the second metal-oxide-semiconductor.
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Cited By (8)
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| CN109246037A (en) * | 2018-08-13 | 2019-01-18 | 上海奥令科电子科技有限公司 | Driver and HSSI High-Speed Serial Interface transmitter for high-speed serial data transmission |
| CN111446955A (en) * | 2020-05-07 | 2020-07-24 | 江苏集萃智能集成电路设计技术研究所有限公司 | Precoding type low-power SST driver with controllable oscillation amplitude |
| CN113014301A (en) * | 2020-09-29 | 2021-06-22 | 北京空间飞行器总体设计部 | Satellite remote-measurement multi-source multi-purpose topology interconnection and combination processing device |
| CN113243096A (en) * | 2019-08-02 | 2021-08-10 | 上海橙科微电子科技有限公司 | Method, system and apparatus for hybrid signal processing for pulse amplitude modulation |
| CN113708742A (en) * | 2020-05-20 | 2021-11-26 | 广东高云半导体科技股份有限公司 | Drive circuit and control method thereof, transmitter and serial deserializing system |
| CN114128152A (en) * | 2019-07-15 | 2022-03-01 | 华为技术有限公司 | Method and apparatus for a multi-level multimode transmitter |
| CN115544935A (en) * | 2022-10-20 | 2022-12-30 | 北京超摩科技有限公司 | Serial interface sending end driving device with multiple level outputs |
| CN115550116A (en) * | 2022-11-30 | 2022-12-30 | 高澈科技(上海)有限公司 | Combined optimization system for tap coefficients of feedforward equalizer at sending end and receiving end |
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| CN109246037B (en) * | 2018-08-13 | 2019-07-12 | 上海奥令科电子科技有限公司 | Driver and HSSI High-Speed Serial Interface transmitter for high-speed serial data transmission |
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| CN114128152B (en) * | 2019-07-15 | 2023-03-03 | 华为技术有限公司 | Method and apparatus for a multi-level multimode transmitter |
| CN114128152A (en) * | 2019-07-15 | 2022-03-01 | 华为技术有限公司 | Method and apparatus for a multi-level multimode transmitter |
| CN113243096A (en) * | 2019-08-02 | 2021-08-10 | 上海橙科微电子科技有限公司 | Method, system and apparatus for hybrid signal processing for pulse amplitude modulation |
| CN111446955A (en) * | 2020-05-07 | 2020-07-24 | 江苏集萃智能集成电路设计技术研究所有限公司 | Precoding type low-power SST driver with controllable oscillation amplitude |
| CN111446955B (en) * | 2020-05-07 | 2023-07-14 | 江苏集萃智能集成电路设计技术研究所有限公司 | Pre-coding swing controllable low-power consumption SST driver |
| CN113708742A (en) * | 2020-05-20 | 2021-11-26 | 广东高云半导体科技股份有限公司 | Drive circuit and control method thereof, transmitter and serial deserializing system |
| CN113708742B (en) * | 2020-05-20 | 2022-08-19 | 广东高云半导体科技股份有限公司 | Drive circuit, control method thereof, transmitter and serial deserializing system |
| CN113014301A (en) * | 2020-09-29 | 2021-06-22 | 北京空间飞行器总体设计部 | Satellite remote-measurement multi-source multi-purpose topology interconnection and combination processing device |
| CN115544935A (en) * | 2022-10-20 | 2022-12-30 | 北京超摩科技有限公司 | Serial interface sending end driving device with multiple level outputs |
| CN115550116A (en) * | 2022-11-30 | 2022-12-30 | 高澈科技(上海)有限公司 | Combined optimization system for tap coefficients of feedforward equalizer at sending end and receiving end |
| CN115550116B (en) * | 2022-11-30 | 2023-03-24 | 高澈科技(上海)有限公司 | Combined optimization system for tap coefficients of feedforward equalizer at sending end and receiving end |
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