CN202332304U

CN202332304U - Memory signal testing plate

Info

Publication number: CN202332304U
Application number: CN2011204729455U
Authority: CN
Inventors: 李华
Original assignee: Dawning Information Industry Co Ltd
Current assignee: Nettrix Information Industry Beijing Co Ltd
Priority date: 2011-11-24
Filing date: 2011-11-24
Publication date: 2012-07-11
Anticipated expiration: 2021-11-24

Abstract

The utility model discloses a memory signal testing plate. The memory signal testing plate comprises a memory bar interface and a memory channel interface, wherein the memory bar interface is electrically connected with a memory bar in a plugging manner; the memory channel interface is electrically connected with a memory channel of a mainboard in a plugging manner; the corresponding pins of the memory bar interface and the memory channel interface are electrically connected with each other through a connecting wire; a memory signal testing point is electrically connected on the connecting wire. In the memory signal testing plate provided by the utility model, not only are the mainboard and the memory bar not destroyed, but also a memory signal test can be conveniently carried out, thus being an effective improvement on the prior art.

Description

Internal memory signal testing plate

Technical field

The utility model relates to computer realm, particularly a kind of internal memory signal testing plate.

Background technology

Raising along with clock rate and continuous increase of data rate and performance; The performance index of necessary assurance system; Or guarantee that the interoperability of internal system storer and memory control apparatus, the simulating signal integrality of memory sub-system have become the problem that the more and more emphasis of design engineer are considered.Many performance issues, even, also can trace back to problems of Signal Integrity in the problem that protocol layer is found.Therefore, the importance of the simulating signal integrity verification of storer has become one step of key of a lot of Electronic Design checkings.Need test shake, timing and electric signal quality in the internal storage data transmission, but these tests are challenges greatly, are likely a complicacy and task consuming time because carry out these tests.In the existing server system, in order to realize test, or on memory bar, reserve test point in advance or pull down the internal memory particle the internal memory signal, very inconvenient.Still more in some cases, final product design does not allow to leave on the circuit board to visit and connects test point, and this brings more trouble with regard to the test of giving the internal memory signal.

The utility model content

To the correlation technique problem of prior art, the purpose of the utility model is to provide a kind of internal memory signal testing plate, to improve the problem of internal memory signal testing difficulty in the prior art.

For realizing above-mentioned purpose, the utility model provides a kind of internal memory signal testing plate, comprising:

The memory bar interface, but be electrically connected with memory bar with pluggable mode;

The memory slot interface, but be electrically connected with the memory slot of mainboard with pluggable mode;

Wherein, be electrically connected through connecting line between the corresponding pin of memory bar interface and memory slot interface, and on connecting line, be electrically connected with internal memory signal testing point.

Preferably, internal memory signal testing plate is a printed circuit board (PCB).

Preferably, the internal memory signal comprises: data input/output signal (DQ0-DQ63), data strobe signal (DQS), power supply signal (VDD), clock signal (CK), address signal (A0-A15), data write signal (WE#), gating signal (CS#) and/or earth signal (GND).

Preferably, internal memory signal testing probe point touches or is welded on the said internal memory signal testing point.

Preferably, the memory bar interface is positioned at a side of internal memory signal testing plate, and the memory slot interface is positioned at the opposite side of internal memory signal testing plate.

Than prior art, the beneficial effect of the utility model is: because the track lengths of printed circuit board (PCB) is shorter, very little to the influence of signal attenuation.The integrality of the test signal of the memory bar to be measured that on printed circuit board (PCB), detects is normally good, can carry out the test of electrical specification fully.But the utility model utilizes printed circuit board (PCB) to be electrically connected with pluggable mode respectively with mainboard and memory bar; And internal memory signal testing point is set on this printed circuit board (PCB); Make test probe easily touch or be welded on the internal memory signal testing point 3 in the place, thereby carry out the test of internal memory signal.This test mode is neither destroyed mainboard, does not also destroy memory bar, can carry out the internal memory signal testing easily again, is the effective improvement to prior art.

Description of drawings

Fig. 1 is the stereographic map of the utility model internal memory signal testing plate.

Embodiment

Below in conjunction with accompanying drawing the utility model embodiment is described.

With reference to figure 1, the utility model provides a kind of internal memory signal testing plate.According to the embodiment of the utility model, this internal memory signal testing plate is a printed circuit board (PCB).One side of this internal memory signal testing plate is a memory bar interface 1, and opposite side is a memory slot interface 2.Wherein, but memory bar interface 1 be electrically connected with memory bar (not shown) to be measured with pluggable mode, but memory slot interface 2 is electrically connected with the memory slot of pluggable mode with the mainboard (not shown).And according to the embodiment of the utility model, memory bar interface 1 is standard component with memory slot interface 2.

Wherein, the wiring through printed circuit board (PCB) realizes being electrically connected between the corresponding pin of memory bar interface 1 and memory slot interface 2.So, in the memory slot interface of internal memory signal testing plate 2 inserts the memory slot of mainboards, when the golden finger of memory bar inserts in the memory bar interface 1 of internal memory signal testing plate, mainboard can be read and write memory modules to be measured through internal memory signal testing plate.In the process of read-write, on printed circuit board (PCB), can produce test signal.The track lengths of printed circuit board (PCB) is shorter, and is very little to the influence of signal attenuation.The integrality of the test signal of the internal memory to be measured that on printed circuit board (PCB), detects is normally good, can carry out the test of electrical specification.

Embodiment according to the utility model; When internal memory signal testing plate connects up; Key signal to the needs test; For example data input/output signal (DQ0-DQ63), data strobe signal (DQS), power supply signal (VDD), clock signal (CK), address signal (A0-A15), data write signal (WE#), gating signal (CS#) and/or earth signal (GND) etc. are reserved internal memory signal testing point 3.This internal memory signal testing point 3 is electrically connected with the wiring of internal memory signal testing plate.Like this, just can the test probe point be touched or be welded on the internal memory signal testing point 3, carry out the test of internal memory signal.This test mode is neither destroyed mainboard, does not also destroy memory bar, can carry out the internal memory signal testing easily again.

The preferred embodiment that the above is merely the utility model is not limited to the utility model, and for a person skilled in the art, the utility model can have various changes and variation.All within the spirit and principle of the utility model, any modification of being done, be equal to replacement, improvement etc., all should be included within the protection domain of the utility model.

Claims

1. an internal memory signal testing plate is characterized in that, comprising:

Memory bar interface (1), but be electrically connected with memory bar with pluggable mode;

Memory slot interface (2), but be electrically connected with the memory slot of mainboard with pluggable mode;

Wherein, be electrically connected through connecting line between the corresponding pin of said memory bar interface (1) and memory slot interface (2), and on said connecting line, be electrically connected with internal memory signal testing point (3).

2. internal memory signal testing plate according to claim 1 is characterized in that, said internal memory signal testing plate is a printed circuit board (PCB).

3. internal memory signal testing plate according to claim 1 and 2; It is characterized in that said internal memory signal comprises: data input/output signal (DQ0-DQ63), data strobe signal (DQS), power supply signal (VDD), clock signal (CK), address signal (A0-A15), data write signal (WE#), gating signal (CS#) and/or earth signal (GND).

4. internal memory signal testing plate according to claim 3 is characterized in that, internal memory signal testing probe point touches or is welded on the said internal memory signal testing point (3).

5. according to each described internal memory signal testing plate in the claim 1,2 and 4, it is characterized in that said memory bar interface (1) is positioned at a side of said internal memory signal testing plate, said memory slot interface (2) is positioned at the opposite side of said internal memory signal testing plate.