CN202261230U - UART (Universal Asynchronous Receiver/Transmitter) voice communication signal inverting circuit based on phase inverter - Google Patents
UART (Universal Asynchronous Receiver/Transmitter) voice communication signal inverting circuit based on phase inverter Download PDFInfo
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- CN202261230U CN202261230U CN2011204192017U CN201120419201U CN202261230U CN 202261230 U CN202261230 U CN 202261230U CN 2011204192017 U CN2011204192017 U CN 2011204192017U CN 201120419201 U CN201120419201 U CN 201120419201U CN 202261230 U CN202261230 U CN 202261230U
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Abstract
The utility model discloses a UART (Universal Asynchronous Receiver/Transmitter) voice communication signal inverting circuit based on a phase inverter; and the UART voice communication signal inverting circuit is mainly composed of an inverter circuit, a normal UART signal end connected with the inverter circuit, an inverted UART signal end and a voice frequency digital power source end. The UART voice communication signal inverting circuit has the advantages of simple structure, low cost and good inverse effect.
Description
Technical field
The utility model relates to negative circuit, specifically is meant the UART voice communication signals negative circuit based on inverter.
Background technology
Inverter is can be with the anti-turnback of phase of input signals, and sort circuit is applied in analogue circuit, such as audio frequency amplifies clock oscillator etc.In electronic circuitry design, often to use inverter
The non-class inverter of TTL.Circuit is formed and operation principle: the inverter that typical TTL NAND gate circuit circuit is formed.
Input stage---transistor T 1 constitutes with resistance R b1.
Intergrade---transistor T 2 constitutes with resistance R c2, Re2.
Output stage---transistor T 3, T4, D and resistance R c4 constitute, push-pull structure, when operate as normal, T4 and T3 always one end, another is saturated.
Operation principle: when input Vi=3.6V (high level) Vb1=3.6+0.7=4.3V is enough to make T1 (bc knot) T2 (be knot) T3 (be knot) conducting simultaneously; Once conducting Vb1=0.7+0.7+0.7=2.1V (fixed value), this moment, the V1 emitter junction must end (inversion magnifying state).Vc2=Vces+Vbe2=0.2+0.7=0.9V is not enough to T3 and D conducting simultaneously, and T4 and D all end.V0=0.2V (low level).As input Vi=0.2V (low level), the Vb1=0.2+0.7=0.9V deficiency is so that the conducting of T1 (bc knot) T2 (be knot) T3 (be knot) while, and T2 T3 all ends, while Vcc---Rc2----T4---D---load formation path, the equal conducting of T4 and D.V0=Vcc-VRc2 (can omit)-Vbe4-VD=5-0.7-0.7=3.6 (high level)
Conclusion: input is high, exports low; Import low, output high (NOT logic).
The TTL inverter is characteristics separately.
The TTL advantage; 1, operating rate is fast; 2, carrying load ability is strong; 3, transmission characteristic is good.
The voltage-transfer characteristic of TTL inverter; Voltage-transfer characteristic is meant that output voltage follows the relation curve that input voltage changes, i.e. UO=f (uI) functional relation.Its curve roughly is divided into four sections: cut-off region: when UI≤0.6V, T1 is operated in dark saturation condition, and < 0.1V, < 0.7V is so T2, T3 end D, the equal conducting of T4, output high level UOH=3.6V to Vbe2 to Uces1.The voltage-transfer characteristic linear zone of TTL inverter: when 0.6V≤UI during 1.3V, 0.7V≤Vb2 1.4V, T2 begins conducting, T3 is not conducting as yet.This moment, T2 was in magnifying state, and its collector voltage Vc2 descends along with the increase of UI, and output voltage U O is also descended.CD section (break over region): 1.3V≤UI 1.4V, and when UI is slightly larger than 1.3V, the equal conducting of T2 T3, T3 gets into saturation condition, and output voltage U O descends rapidly.The saturation region: when UI >=1.4V, get into and be inverted operating state along with UI increases T1, D ends, and T4 ends, and T2, T3 are saturated, thereby output low level UOL=0.3V.
In the circuit of voice communication; According to the specific (special) requirements of speech chip, generally UART (universal asynchronous reception/dispensing device) signal of communication need be carried out anti-phase and handle, for guaranteeing the quality of voice communication; Therefore the circuit structure that needs anti-phase to handle is simple, and cost is low.
The utility model content
It is a kind of simple in structure that the purpose of the utility model is to provide, and cost is low, based on the UART voice communication signals negative circuit of inverter.
The implementation of the utility model is following: based on the UART voice communication signals negative circuit of inverter, mainly be made up of the normal UART signal end of inverter circuit and connection and inverter circuit, UART signal end, the digital audio power end after the anti-phase.
Said inverter circuit comprises inverter U13, and said inverter U13 comprises that 5 pins are respectively: IN pin 1, GND pin 2, NC pin 3, OUT pin 4, VCC pin 5; Said IN pin 1 is connected with normal UART signal end; Said GND pin 2 ground connection; OUT pin 4 connects the UART signal end after the anti-phase; Said VCC pin 5 is connected with the digital audio power end, and said VCC pin 5 also is in series with capacitor C 31 and ground wire successively.
The signal of said inverter U13 is INV_NL17SH04.
The electric capacity of said capacitor C 31 is 100nF.
The electric capacity of said capacitor C 31 is 100-105nF or 95-100nF.
Based on foregoing, the workflow of the utility model is: when normal UART signal end input signal was 1, normal UART signal 1 was through IN pin 1 input of inverter U13; Become 0 through the processing signals of inverter, the signal after its anti-phase is at last through OUT pin 4 outputs of inverter U13, is uploaded to the UART signal end after the anti-phase; In like manner; When normal UART signal end input signal was 0, normal UART signal 0 was through IN pin 1 input of inverter U13, and the processing signals of process inverter becomes 1; Signal after its anti-phase is at last through OUT pin 4 outputs of inverter U13, is uploaded to the UART signal end after the anti-phase.
The advantage of the utility model is: simple in structure, cost is low, and anti-phase is effective.
Description of drawings
Fig. 1 is the utility model overall structure sketch map.
Embodiment
Embodiment one
As shown in Figure 1.
Based on the UART voice communication signals negative circuit of inverter, mainly constitute by the normal UART signal end of inverter circuit and connection and inverter circuit, UART signal end, the digital audio power end after the anti-phase.
Said inverter circuit comprises inverter U13, and said inverter U13 comprises that 5 pins are respectively: IN pin 1, GND pin 2, NC pin 3, OUT pin 4, VCC pin 5; Said IN pin 1 is connected with normal UART signal end; Said GND pin 2 ground connection; OUT pin 4 connects the UART signal end after the anti-phase; Said VCC pin 5 is connected with the digital audio power end, and said VCC pin 5 also is in series with capacitor C 31 and ground wire successively.
The signal of said inverter U13 is INV_NL17SH04.
The electric capacity of said capacitor C 31 is 100nF.
The electric capacity of said capacitor C 31 is 100-105nF or 95-100nF.
When normal UART signal end input signal was 1, normal UART signal 1 was through IN pin 1 input of inverter U13, and the processing signals of process inverter becomes 0; Signal after its anti-phase is exported through the OUT pin 4 of inverter U13 at last; Be uploaded to the UART signal end after the anti-phase, in like manner, when normal UART signal end input signal is 0; Normal UART signal 0 is through IN pin 1 input of inverter U13; Become 1 through the processing signals of inverter, the signal after its anti-phase is at last through OUT pin 4 outputs of inverter U13, is uploaded to the UART signal end after the anti-phase.
As stated, then can well realize the utility model.
Claims (5)
1. based on the UART voice communication signals negative circuit of inverter, it is characterized in that: mainly constitute by the normal UART signal end of inverter circuit and connection and inverter circuit, UART signal end, the digital audio power end after the anti-phase.
2. the UART voice communication signals negative circuit based on inverter according to claim 1; It is characterized in that: said inverter circuit comprises inverter U13, and said inverter U13 comprises that 5 pins are respectively: IN pin 1, GND pin 2, NC pin 3, OUT pin 4, VCC pin 5; Said IN pin 1 is connected with normal UART signal end; Said GND pin 2 ground connection; OUT pin 4 connects the UART signal end after the anti-phase; Said VCC pin 5 is connected with the digital audio power end, and said VCC pin 5 also is in series with capacitor C 31 and ground wire successively.
3. the UART voice communication signals negative circuit based on inverter according to claim 2, it is characterized in that: the signal of said inverter U13 is INV_NL17SH04.
4. the UART voice communication signals negative circuit based on inverter according to claim 2, it is characterized in that: the electric capacity of said capacitor C 31 is 100nF.
5. the UART voice communication signals negative circuit based on inverter according to claim 2, it is characterized in that: the electric capacity of said capacitor C 31 is 100-105nF or 95-100nF.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011204192017U CN202261230U (en) | 2011-10-28 | 2011-10-28 | UART (Universal Asynchronous Receiver/Transmitter) voice communication signal inverting circuit based on phase inverter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011204192017U CN202261230U (en) | 2011-10-28 | 2011-10-28 | UART (Universal Asynchronous Receiver/Transmitter) voice communication signal inverting circuit based on phase inverter |
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| Publication Number | Publication Date |
|---|---|
| CN202261230U true CN202261230U (en) | 2012-05-30 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011204192017U Expired - Fee Related CN202261230U (en) | 2011-10-28 | 2011-10-28 | UART (Universal Asynchronous Receiver/Transmitter) voice communication signal inverting circuit based on phase inverter |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103095286A (en) * | 2011-10-28 | 2013-05-08 | 成都高新区尼玛电子产品外观设计工作室 | Universal asynchronous receiver transmitter (UART) voice communication signal reversal phase circuit based on phase inverter |
| US20220344255A1 (en) * | 2021-04-27 | 2022-10-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Apparatus and methods for generating a circuit with high density routing layout |
-
2011
- 2011-10-28 CN CN2011204192017U patent/CN202261230U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103095286A (en) * | 2011-10-28 | 2013-05-08 | 成都高新区尼玛电子产品外观设计工作室 | Universal asynchronous receiver transmitter (UART) voice communication signal reversal phase circuit based on phase inverter |
| US20220344255A1 (en) * | 2021-04-27 | 2022-10-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Apparatus and methods for generating a circuit with high density routing layout |
| US11923297B2 (en) * | 2021-04-27 | 2024-03-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Apparatus and methods for generating a circuit with high density routing layout |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120530 Termination date: 20121028 |