CN202258364U - Multichannel storing device based on semiconductor package - Google Patents
Multichannel storing device based on semiconductor package Download PDFInfo
- Publication number
- CN202258364U CN202258364U CN2011204072852U CN201120407285U CN202258364U CN 202258364 U CN202258364 U CN 202258364U CN 2011204072852 U CN2011204072852 U CN 2011204072852U CN 201120407285 U CN201120407285 U CN 201120407285U CN 202258364 U CN202258364 U CN 202258364U
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- flash memory
- nude film
- memory nude
- circuit substrate
- interarea
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- Semiconductor Memories (AREA)
Abstract
The utility model relates to a multichannel storing device based on semiconductor package; a circuit substrate comprises a first main surface and a second main surface which is opposite to the first main surface; flash memory bare chip groups are arranged on the first main surface of the circuit substrate; the first main surface of the circuit substrate is provided with a plurality of channel routing areas connected with input/ output (I/ O) interfaces; the I/ O interfaces are arranged on the second main surface of the circuit substrate; and the flash memory bare chip groups are connected with the I/ O interfaces by the channel routing areas. By adopting the flash memory bare chip groups which respectively comprise one or more flash memory bare chip(s) and a plurality of I/ O channels, the multichannel storing device based on semiconductor package is capable of using a single flash memory to support the of I/ O channels, and leading each I/ O channel to support storage devices of a plurality of flash memory wafers, thus meeting the demand of high-speed and high-capacity products in a way of a single chip and reducing the sizes of the products of an application terminal to the utmost extent.
Description
Technical field
The utility model relates to a kind of solid-state storage device, relates in particular to a kind of multiple channel storage device of based semiconductor encapsulation.
Background technology
Flash chip is good with its readwrite performance, and cost performance is high, non-volatile advantages such as (under powering-off state, still can keep institute's data information stored); Become the most successful at present; Most popular semiconductor storage medium is at USB (USB: mobile storage Universal Serial Bus), SSD (solid state hard disc: Solid State Disk); Media player; Portable communication device, Netbook (net book), widespread use on the MID products such as (mobile internet device Mobile Internet Device).
Conventional at present flash chip; Inside is packaged with one or more flash memory nude films; Each flash memory nude film is placed on a slice metal substrate, and the mode through routing links together the pin that function is identical on the flash memory nude film then, also possesses one group of pin with identical function definition simultaneously on the metal substrate; Link together the corresponding pin of the pin of flash memory nude film and metal substrate through the routing mode again, form a flash chip that possesses memory function.For the MCU or the CPU (main control chip) that drive and manage flash chip, the shared one group of I/O mouth of one or more flash memory nude films (data IO port) in the flash chip, this group I/O mouth is a transmission channel.Therefore each flash chip can only be supported a passage.
Because the data transmission capabilities of each group I/O port is limited, when the higher data transmission capabilities of product needed that uses flash chip, possess simultaneously more jumbo the time, just must use multichannel technology (organize I/O port walk abreast work simultaneously) more.Such as USB mobile storage at a high speed, products such as SSD solid state hard disc, and other need flash memory to make the portable equipment of system's storage.When using multichannel technology, if need to support 2 passages, 4 passages; With regard to the minimum flash chip that needs respective numbers, i.e. 2 flash chips of the minimum needs of 2 passages, 4 flash chips of the minimum needs of 4 passages; And the area that every flash chip takies is fixed; Will make the bigger area of multi-channel type application end product needed place flash chip like this, be unfavorable for the miniaturization of product, cause product global design difficulty to increase simultaneously.
The utility model content
The technical matters that the utility model solves is: make up a kind of multiple channel storage device of based semiconductor encapsulation, overcoming the prior art multiple channel storage device needs a plurality of flash chips, is unfavorable for the technical matters of miniaturization.
The technical scheme of the utility model is: the multiple channel storage device that makes up a kind of based semiconductor encapsulation; Comprise a plurality of flash memory nude film groups, circuit substrate, IO port, the web member of flash memory nude film group are installed; Said circuit substrate comprises first interarea and second interarea relative with said first interarea; Said flash memory nude film group is installed in first interarea of said circuit substrate; First interarea of said circuit substrate is provided with a plurality of passage routings district that connects said IO port, and said IO port is arranged on second interarea of said circuit substrate, and said a plurality of flash memory nude film groups connect said IO port through a plurality of passage routings district.
The further technical scheme of the utility model is: said flash memory nude film group is made up of one or more flash memory nude films.
The further technical scheme of the utility model is: said a plurality of flash memory nude film groups stack.
The further technical scheme of the utility model is: said flash memory nude film group comprises the routing end, and said adjacent flash memory nude film group routing end dislocation stacks.
The further technical scheme of the utility model is: said adjacent flash memory nude film group routing end is 90 degree dislocation and stacks.
The further technical scheme of the utility model is: said adjacent flash memory nude film group routing end is 180 degree dislocation and stacks.
The further technical scheme of the utility model is: also comprise bonding film, between the said flash memory nude film group through said bonding film bonding connection.
The further technical scheme of the utility model is: also comprise the sealing resin that seals said flash memory nude film.
The technique effect of the utility model is: the multiple channel storage device that makes up a kind of based semiconductor encapsulation; Comprise a plurality of flash memory nude film groups, circuit substrate, IO port, the web member of flash memory nude film group are installed; Said circuit substrate comprises first interarea and second interarea relative with said first interarea; Said flash memory nude film group is installed in first interarea of said circuit substrate; First interarea of said circuit substrate is provided with a plurality of passage routings district that connects said IO port, and said IO port is arranged on second interarea of said circuit substrate, and said a plurality of flash memory nude film groups connect said IO port through a plurality of passage routings district.The utility model adopts a plurality of flash memory nude film groups; Said flash memory nude film group comprises one or more flash memory nude films; Adopt a plurality of IO channels simultaneously, realize that single flash memory supports many IO channels, each IO channel is supported the memory storage of many flash memory wafers; Satisfy the design requirement of high-speed high capacity product with the mode of single-chip, reduce the design size of application end product to greatest extent.
Description of drawings
Fig. 1 is the structural representation of the utility model.
Fig. 2 connects synoptic diagram for the utility model flash chip.
Fig. 3 stacks synoptic diagram for a kind of flash memory nude film of the utility model group.
Fig. 4 stacks synoptic diagram for the another kind of flash memory nude film of the utility model group.
Embodiment
Below in conjunction with specific embodiment, the utility model technical scheme is further specified.
As shown in Figure 1; The embodiment of the utility model is: the multiple channel storage device that makes up a kind of based semiconductor encapsulation; Comprise a plurality of flash memory nude film group 3, circuit substrate 2, IO port 6, the web member 7 of flash memory nude film group 3 are installed; Said circuit substrate 2 comprises the first interarea 2b and the second interarea 2a relative with the said first interarea 2b; Said flash memory nude film group 3 is installed in the first interarea 2b of said circuit substrate 2; The first interarea 2b of said circuit substrate 2 is provided with a plurality of passage routings district that connects said IO port 6, and said IO port 6 is arranged on the second interarea 2a of said circuit substrate 2, and said a plurality of flash memory nude film groups 3 connect said IO port 6 through a plurality of passage routings district.
Like Fig. 1, shown in Figure 2; The practical implementation process of the utility model is following: the utility model adopts a plurality of flash memory nude film groups 3; Said flash memory nude film group 3 is installed in the first interarea 2b of said circuit substrate 2; The first interarea 2b of said circuit substrate 2 is provided with a plurality of passage routings district that connects said IO port 6, and said IO port 6 is arranged on the second interarea 2a of said circuit substrate 2, and said a plurality of flash memory nude film groups 3 connect said IO port 6 through a plurality of passage routings district.The utility model adopts a plurality of flash memory nude film groups 3; Said flash memory nude film group 3 comprises one or more flash memory nude films; Adopt a plurality of IO channels 5 simultaneously, realize that single flash memory supports many IO channels 5, each IO channel 5 is supported the memory storage of many flash memory wafers; Satisfy the design requirement of high-speed high capacity product with the mode of single-chip, reduce the design size of application end product to greatest extent.In the utility model specific embodiment; Also comprise the master controller chip; Said master controller chip and flash memory nude film group 3 are electrically connected through web member 7 at said circuit substrate 2; Said a plurality of flash memory nude film group 3 is encapsulated as flash chip after connecting, adopt hyperchannel to connect between said master controller chip and the said flash chip.
The preferred implementation of the utility model is: said a plurality of flash memory nude film groups 3 stack.Said flash memory nude film group 3 comprises the routing end, and said adjacent flash memory nude film group 3 routing ends dislocation stacks.As shown in Figure 3, in the specific embodiment, said adjacent flash memory nude film group 3 routing ends are 90 degree dislocation and stack, and more convenient like this setting is connected with the routing district, realizes hyperchannel.As shown in Figure 4, in the specific embodiment, said adjacent flash memory nude film group routing end is 180 degree dislocation and stacks, and arrangement is more neat like this, is convenient to minification.As shown in Figure 1, the preferred implementation of the utility model is: the flash memory nude film group 3 for stacking, also comprise bonding film 4, between the said flash memory nude film group 3 through said bonding film 4 bonding connections.In the utility model specific embodiment, also comprise the sealing resin 8 that seals said flash memory nude film 3.
The technique effect of the utility model is: the multiple channel storage device that makes up a kind of based semiconductor encapsulation; Comprise a plurality of flash memory nude film group 3, circuit substrate 2, IO port 6, the web member 7 of flash memory nude film group 3 are installed; Said circuit substrate 2 comprises the first interarea 2b and the second interarea 2a relative with the said first interarea 2b; Said flash memory nude film group 3 is installed in the first interarea 2b of said circuit substrate 2; The first interarea 2b of said circuit substrate 2 is provided with a plurality of passage routings district that connects said IO port 6; Said IO port 6 is arranged on the second interarea 2a of said circuit substrate 2, and said a plurality of flash memory nude film groups 3 connect said IO port 6 through a plurality of passage routings district.The present invention adopts a plurality of flash memory nude film groups; Adopt a plurality of IO channels simultaneously; Realize single flash memory support hyperchannel; Every passage is supported the memory storage of many flash memory wafers, satisfies the design requirement of high-speed high capacity product with the mode of single-chip, reduces the design size of application end product to greatest extent.
Above content is the further explain that combines concrete preferred implementation that the utility model is done, and can not assert that the practical implementation of the utility model is confined to these explanations.For the those of ordinary skill of technical field under the utility model, under the prerequisite that does not break away from the utility model design, can also make some simple deduction or replace, all should be regarded as belonging to the protection domain of the utility model.
Claims (8)
1. the multiple channel storage device of based semiconductor encapsulation; It is characterized in that; Comprise a plurality of flash memory nude film groups, circuit substrate, IO port, the web member of flash memory nude film group are installed; Said circuit substrate comprises first interarea and second interarea relative with said first interarea, and said flash memory nude film group is installed in first interarea of said circuit substrate, and first interarea of said circuit substrate is provided with a plurality of passage routings district that connects said IO port; Said IO port is arranged on second interarea of said circuit substrate, and said a plurality of flash memory nude film groups connect said IO port through a plurality of passage routings district.
2. according to the multiple channel storage device of the said based semiconductor encapsulation of claim 1, it is characterized in that said flash memory nude film group is made up of one or more flash memory nude films.
3. according to the multiple channel storage device of the said based semiconductor encapsulation of claim 1, it is characterized in that said a plurality of flash memory nude film groups stack.
4. according to the multiple channel storage device of the said based semiconductor encapsulation of claim 1, it is characterized in that said flash memory nude film group comprises the routing end, said adjacent flash memory nude film group routing end dislocation stacks.
5. according to the multiple channel storage device of the said based semiconductor encapsulation of claim 4, it is characterized in that said adjacent flash memory nude film group routing end is 90 degree dislocation and stacks.
6. according to the multiple channel storage device of the said based semiconductor encapsulation of claim 4, it is characterized in that said adjacent flash memory nude film group routing end is 180 degree dislocation and stacks.
7. according to the multiple channel storage device of the said based semiconductor of claim 3 encapsulation, it is characterized in that, also comprise bonding film, between the said flash memory nude film group through said bonding film bonding connection.
8. according to the multiple channel storage device of the said based semiconductor encapsulation of claim 1, it is characterized in that, also comprise the sealing resin that seals said flash memory nude film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011204072852U CN202258364U (en) | 2011-10-24 | 2011-10-24 | Multichannel storing device based on semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011204072852U CN202258364U (en) | 2011-10-24 | 2011-10-24 | Multichannel storing device based on semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202258364U true CN202258364U (en) | 2012-05-30 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011204072852U Expired - Fee Related CN202258364U (en) | 2011-10-24 | 2011-10-24 | Multichannel storing device based on semiconductor package |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109359720A (en) * | 2018-11-30 | 2019-02-19 | 深圳豪杰创新电子有限公司 | A kind of mobile memory module device of miniature semiconductor Type-C |
-
2011
- 2011-10-24 CN CN2011204072852U patent/CN202258364U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109359720A (en) * | 2018-11-30 | 2019-02-19 | 深圳豪杰创新电子有限公司 | A kind of mobile memory module device of miniature semiconductor Type-C |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: SHENZHEN BIWIN STORAGE TECHNOLOGY CO., LTD. Free format text: FORMER NAME: SHENZHEN TAISHENGWEI TECHNOLOGY CO., LTD. |
|
| CP03 | Change of name, title or address |
Address after: 518055, Guangdong, Nanshan District province Taoyuan Shenzhen street with the rich industrial city No. 4 factory building, 6 floor Patentee after: Biwin Storage Technology Limited Address before: 518000 Guangdong city of Shenzhen province Nanshan District Tang Lang Xili town with rich industrial city 4 Patentee before: Shenzhen Taishengwei Technology Co.,Ltd. |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120530 Termination date: 20141024 |
|
| EXPY | Termination of patent right or utility model |