CN201788702U - Flash array concentrator, cascaded flash array and staggered and cascaded flash array - Google Patents
Flash array concentrator, cascaded flash array and staggered and cascaded flash array Download PDFInfo
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- CN201788702U CN201788702U CN2010205192382U CN201020519238U CN201788702U CN 201788702 U CN201788702 U CN 201788702U CN 2010205192382 U CN2010205192382 U CN 2010205192382U CN 201020519238 U CN201020519238 U CN 201020519238U CN 201788702 U CN201788702 U CN 201788702U
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Abstract
The utility model discloses a flash array concentrator, a cascaded flash array and a staggered and cascaded flash array, which is capable of realizing higher capacity and higher performance. The technical scheme includes that the staggered and cascaded flash array consists of a plurality of flash array concentrators, each flash array concentrator comprises a plurality of parallel data input ports, a serial data input port, a serial data output port and a processor chip, wherein the parallel data input ports are used for being connected with flash memory equipment or other flash array concentrators, the serial data input port is used for being connected with the other flash array concentrators, the serial data output port is used for being connected with the other flash array concentrators or computers, the processor chip is connected with the serial data input port, the serial data output port and the parallel data input ports and used for processing storage of data, and the parallel data input ports of each flash array concentrator are in staggered connection with the flash memory equipment or the other flash array concentrators.
Description
Technical field
The utility model relates to a kind of flash memory device, relates in particular to a kind of equipment that improves the flash array performance.
Background technology
At present, hard disk drive has very big capacity, but relatively heavier, and flash memory is then because its high density, non-volatile and the little advantage of size is arranged and come into vogue with respect to hard disk drive.Flash memory is based on the technology of EPROM and EEPROM.In the EPROM flash memory, a large amount of storage unit (byte) can be simultaneously deleted, and the byte of EERPOM must be wiped free of separately.Two types flash memory is arranged: NOR flash memory and nand flash memory on the market.Nand flash memory is because the storage array of its more compact structure has higher density.The flash memory of the application's indication should be understood that to use the flash memory of NOR or NAND or other types.
Solid state hard disc (SSD) adopts solid-state memory to store persistant data.Most of solid state hard disc manufacturer uses nonvolatile memory.Solid state hard disc based on flash memory does not have moving-member, in therefore traditional dynamo-electric disk the intrinsic addressing time in flash memories, can ignore.Single NAND chip speed is slower, and reason is narrow relatively asynchronous IO interface.In order to reach high performance SSD, flash chip is generally parallel to be used.Yet present solid state hard disc is very expensive and is non-extendability.
The applicant has submitted patent of invention (the publication No. CN 101178933A of " a kind of flash memory array device " before this to, date of publication is on May 14th, 2008), utilize this patent, flash memory can be added when needed, delete or substitute, and the commercial flash memory by a plurality of cheapnesss of parallel connection reaches high power capacity and high-performance.In addition, the applicant has also submitted patent of invention (the publication No. CN 101178942A of " a kind of abrasion wear process method of data block and device " to, date of publication is on May 14th, 2008), this wearing and tearing processing mode can be applied in the flash array, has better reliability and more long-life device to design.
The patent of invention of " a kind of flash memory array device " utilizes parallel flash memory to improve the capacity and the performance of flash memory array device.Yet use an in parallel defective to be in storage system: they often need the interconnecting interface between a large amount of equipment, so that make this device transmit information concurrently.In addition, because the delay of interconnect signal in parallel the propagation, the quantity of including equipment in these subsystems in is limited.
The utility model content
The purpose of this utility model is to address the above problem, and a kind of flash array hub is provided, and can realize the performance of bigger capacity and Geng Gao.
Another purpose of the present utility model has been to provide a kind of stacked flash array, can realize the set of more flash array hubs by overlapped way, so that the performance of bigger capacity and Geng Gao to be provided.
Another purpose of the present utility model has been to provide a kind of flash array of intersecting, can realize the set of more flash array hubs by the mode of intersecting, can realize more handling capacities of flash array and the performance of more optimizing.
The technical solution of the utility model is: the utility model has disclosed a kind of flash array hub, comprising:
The serial datum input port is used to connect other flash array hub;
The serial datum output port is used to connect other flash array hub or computing machine;
Several parallel data input ports are used to connect other flash array hub or flash memory device;
Processor chips connect this serial data input port, this serial data output port and this several parallel data input ports, are used for the deal with data storage.
The utility model has also disclosed a kind of stacked flash array, is made up of several flash array hubs, and wherein each flash array hub comprises:
Several parallel data input ports are used to connect flash memory device or other flash array hub;
The serial datum input port is used to connect other flash array hub;
The serial datum output port is used to connect other flash array hub or computing machine;
Processor chips connect this serial data input port, this serial data output port and this several parallel data input ports, are used for the deal with data storage.
According to an embodiment of stacked flash array of the present utility model, these several parallel data input ports comprise usb type, SD card type or miniature SD card type.
According to an embodiment of stacked flash array of the present utility model, this serial data input port and this serial data output port comprise the transmission of wireless signals interface.
The utility model has disclosed a kind of flash array of intersecting in addition, is made up of several flash array hubs, and wherein each flash array hub comprises:
Several parallel data input ports are used to connect flash memory device or other flash array hub;
The serial datum input port is used to connect other flash array hub;
The serial datum output port is used to connect other flash array hub or computing machine;
Processor chips connect this serial data input port, this serial data output port and this several parallel data input ports, are used for the deal with data storage;
Wherein several parallel data input ports of each flash array hub are the configuration relations that is cross-linked with flash memory device that is connected or other flash array hub.
According to an embodiment of the flash array of intersecting of the present utility model, the configuration of the relation that is cross-linked of the parallel data input port in the flash array hub is that the mode by the circuit board wiring realizes.
According to an embodiment of the flash array of intersecting of the present utility model, the configuration of the relation that is cross-linked of the parallel data input port in the flash array hub is that the mode by the software control in the flash array hub realizes.
According to an embodiment of the flash array of intersecting of the present utility model, these several parallel data input ports comprise usb type, SD card type or miniature SD card type.
According to an embodiment of the flash array of intersecting of the present utility model, this serial data input port and this serial data output port comprise the transmission of wireless signals interface.
The utility model contrast prior art has following beneficial effect: the utility model is by designing a flash array hub, interface on it is divided into two types: as the device port of parallel input and the I/O port that is used as the serial input and output, the former is used to connect various flash memory devices, and the latter is used for the connection of a plurality of flash array hubs or main frame.Constitute a flash array by these flash array hubs are integrated in stacked mode, connect the device port and all kinds of flash memory device of flash array again with interlace mode, with capacity that increases flash array and the performance of optimizing flash array.
Description of drawings
Fig. 1 is the structural drawing of the embodiment of flash array hub of the present utility model.
Fig. 2 is the structural drawing of the embodiment of stacked flash array of the present utility model.
Fig. 3 is the structural drawing of the stacked flash array realized in the noninterlace mode.
Fig. 4 is the structural drawing of the stacked flash array of realizing with interlace mode of the present utility model.
Embodiment
The utility model will be further described below in conjunction with drawings and Examples.
The embodiment of flash array hub
Fig. 1 shows the structure of the embodiment of flash array hub of the present utility model.See also Fig. 1, the flash array hub of present embodiment comprises processor chips 10, serial data input port 12, serial data output port 14 and a plurality of parallel data input port 16.Annexation between these assemblies is: serial data input port (USB input port) 12, serial data output port (USB output port) 14 are connected with processor chips 10 respectively with a plurality of parallel data input ports 16.
Wherein each parallel data input port 16 can insert flash memory device or other flash array hub, and the flash memory device here is meant the memory storage that flash memories all in the prior art is realized.The physical interface type of parallel data input port 16 is divided into multiple, for example is usb type, SD card type or miniature SD card type etc.Usually, a flash array hub can design 3～4 parallel data input ports 16, and each parallel data input port 16 connects flash memory device or other flash array hub.These parallel data input ports 16 can make externally between the serial data output port 14 of the flash memory device that connects and flash array hub it is to improve the capacity of memory device and performance by data parallel transmission (read/write).
Serial data input port 12 is used for connecting other flash array hub, and serial data output port 14 is used for connecting other flash array hub or computing machine.
The data that processor chips 10 receive from serial data input port 12, a plurality of parallel data input ports 16 are carried out data storage, and these data are outputed to the outside by serial data output port 14.
The purpose that the flash array hub of present embodiment exists is exactly to allow the bandwidth that is provided by USB interface farthest is provided, and allows a plurality of equipment to use this USB interface simultaneously.
The embodiment of stacked flash array
Fig. 2 shows the structure of the embodiment of stacked flash array of the present utility model.Please participate in Fig. 2, the stacked flash array of present embodiment is to be made up of flash array hub 1a～1c of a plurality of Fig. 1 embodiment (be shown 3 in Fig. 2, actual can have a plurality of arbitrarily).Wherein the inner structure of each flash array hub is all identical with Fig. 1 embodiment.
With flash array hub 1a is example, and it comprises processor chips 10a, serial data input port 12a, serial data output port 14a and a plurality of parallel data input port 16a.Annexation between these assemblies is: serial data input port (USB input port) 12a, serial data output port (USB output port) 14a are connected with processor chips 10a respectively with a plurality of parallel data input port 16a.
Wherein each parallel data input port 16a can insert flash memory device or other flash array hub, and the flash memory device here is meant the memory storage that flash memories all in the prior art is realized.The physical interface type of parallel data input port 16a is divided into multiple, for example is usb type, SD card type or miniature SD card type etc.Usually, a flash array hub can design 3～4 parallel data input port 16a, and each parallel data input port 16a connects flash memory device or other flash array hub.These parallel data input ports 16a can make externally between the serial data output port 14a of the flash memory device that connects and flash array hub it is to improve the capacity of memory device and performance by data parallel transmission (read/write).
Serial data input port 12a is used for connecting other flash array hub, and serial data output port 14a is used for connecting other flash array hub (for example flash array hub 1b among Fig. 2) or computing machine.Input port and output port can comprise the transmission of wireless signals interface, for example wireless transmission method such as Wifi, bluetooth.
The port of flash array hub 1a is divided into two types: device port and I/O port.So-called device port is exactly a plurality of parallel data input port 16a in fact, and the meaning is exactly that parallel data input port 16a connects flash memory device.The I/O port is exactly serial data input port 12a and serial data output port 14a in fact, the meaning be exactly serial data input port 12a and output port 14a be as the input and output of flash memory hub, promptly exchange with other flash array hub (for example flash array hub 1b) or main frame.
Below all be to be that example illustrates with flash array hub 1a, the inner structure of other flash array hubs such as 1b, 1c etc. is identical.And these flash array hubs all are connected with the serial data output port by the serial data input port each other, and external flash equipment is connected to the parallel data input port of these flash array hubs usually.
This means that the flash array hub that has only at least one device port of support and an I/O port just can be applied use and need not other adapter.This means that also as the hub device of a plug-in unit, its I/O port must be linked into the device port of female hub.Each female hub can be supported a plurality of sub-hubs, because it has a plurality of device ports, but each sub-hub can only have a female hub.
The embodiment of the flash array of intersecting
Fig. 3 shows a kind of stacked flash array that interlace mode is realized that do not have.Fig. 3 is one, and to embody flash memory device be the rough schematic how to be connected with device port in the flash array.34 port integrated circuit under the laminated configuration are adopted in this design.In some cases, if saturated reading of while, four parallel flash memory devices in first IC chip just can allow its bandwidth saturated.In this case, first IC chip operate in saturation, and other two IC chips leave unused.
Detailed says, in Fig. 3, U1～U12 refers to outside flash memory device (for example USB device), and I1～I12 is the device port (these parallel data input ports just) on the flash array hub in the flash array.In the connected mode of Fig. 3, for example IC1 chip (being exactly processor chips) can only be handled USB device U1～U4, if U1～U4 saturated reading of while just can allow whole device bandwidth saturated usually.In this case, first IC chip operate in saturation, and other two IC chips leave unused.In other words, common exactly saturated reading of 4 ports while just can allow the bandwidth of whole device reach capacity.
In order to address this problem, the applicant has developed the flash array of intersecting shown in Figure 4.See also Fig. 4, the flash array of the intersecting of present embodiment is to be based upon on the basis of stacked flash array shown in Figure 2 to realize, the part of its innovation be the parallel data input port and the flash memory device that connected between the configuration of annexation.
See stacked flash array first, the stacked flash array of present embodiment is to be made up of a plurality of flash array hub 2a～2c (be shown 3 in Fig. 3, actual can have a plurality of arbitrarily).Wherein all the embodiment with Fig. 1 and Fig. 2 is identical for the inner structure of each flash array hub.
With flash array hub 2a is example, and it comprises processor chips 20a, serial data input port 22a, serial data output port 24a and a plurality of parallel data input port 26a.Annexation between these assemblies is: serial data input port (USB input port) 22a, serial data output port (USB output port) 24a are connected with processor chips 20a respectively with a plurality of parallel data input port 26a.
Wherein each parallel data input port 26a can insert flash memory device or other flash array hub, and the flash memory device here is meant the memory storage that flash memories all in the prior art is realized.The physical interface type of parallel data input port 26a is divided into multiple, for example is usb type, SD card type or miniature SD card type etc.Usually, a flash array hub can design 3～4 parallel data input port 26a, and each parallel data input port 26a connects flash memory device or other flash array hub.These parallel data input ports 26a can make externally between the serial data output port 24a of the flash memory device that connects and flash array hub it is to improve the capacity of memory device and performance by data parallel transmission (read/write).
Serial data input port 22a is used for connecting other flash array hub, and serial data output port 24a is used for connecting other flash array hub (for example flash array hub 2b among Fig. 4) or computing machine.Input port and output port can be the transmission of wireless signals interfaces, for example are wireless transmission methods such as Wifi, bluetooth.
The port of flash array hub 2a is divided into two types: device port and I/O port.So-called device port is exactly a plurality of parallel data input port 26a in fact, and the meaning is exactly that parallel data input port 26a connects flash memory device.The I/O port is exactly serial data input port 22a and serial data output port 24a in fact, the meaning be exactly serial data input port 22a and output port 24a be as the input and output of flash memory hub, promptly exchange with other flash array hub (for example flash array hub 2b) or main frame.
Below all be to be that example illustrates with flash array hub 2a, the inner structure of other flash array hubs such as 2b, 2c etc. is identical.And these flash array hubs all are connected with the serial data output port by the serial data input port each other, and external flash equipment is connected to the parallel data input port of these flash array hubs usually.
Focusing on of present embodiment: the port corresponding relation between the parallel data input port of each flash array hub and the flash memory device that is connected (for example flash memory device of USB interface).
In the rough schematic of Fig. 3, be to be docile and obedient preface to concern one to one between flash memory device U1～U12 and the parallel data input port I1～I12.Caused like this as the IC1 chip and can only handle flash memory device U1～U4, if their saturated reading simultaneously just can allow whole device bandwidth saturated usually.
And in the present embodiment, be interconnected between parallel data input port I1～I12 of flash memory device U1～U12 and these flash array hubs 2a～2b.So-called interconnected, in Fig. 4 be as can be seen: flash memory device U1 connects the parallel data input port I1 of flash array hub 2a, flash memory device U2 connects the parallel data input port I5 of flash array hub 2b, flash memory device U3 connects the parallel data input port I9 of flash array hub 2c, flash memory device U4 connects the parallel data input port I2 of flash array hub 2a, flash memory device U5 connects the parallel data input port I6 of flash array hub 2b, flash memory device U6 connects the parallel data input port I10 of flash array hub 2c, flash memory device U7 connects the parallel data input port I3 of flash array hub 2a, flash memory device U8 connects the parallel data input port I7 of flash array hub 2b, flash memory device U9 connects the parallel data input port I11 of flash array hub 2c, flash memory device U10 connects the parallel data input port I4 of flash array hub 2a, flash memory device U11 connects the parallel data input port I8 of flash array hub 2b, and flash memory device U12 connects the parallel data input port I12 of flash array hub 2c.
Certainly, Fig. 4 only is as interconnected a kind of example, so long as not regarding the interconnected mode that the utility model should be protected as according to the configuration mode one to one of number order.
Like this interconnected can be handled the flash memory module that is connected on other chips so that IC chip can interlock, such configuration can make and make these 3 IC chips always handle the flash memory device of equality quantity by flash array alternate selection flash memory device from the different IC chips.The example of comparison diagram 3, the interconnected flash memory device of present embodiment, because the flash memory device that it can alternate run be cross-linked, make maximum 4 configuring ports of script, 8 ports or 12 ports have been become, when the quantity of the flash memory device that inserts at flash array does not reach its state of saturation, the interconnected effect of playing load balance.This interconnected mode of present embodiment can realize on hardware or software view, and hardware is to realize that by as shown in Figure 4 circuit board wiring software can be realized by the controller in the flash array.
The foregoing description provides to those of ordinary skills and realizes or use of the present utility model; those of ordinary skills can be under the situation that does not break away from invention thought of the present utility model; the foregoing description is made various modifications or variation; thereby protection domain of the present utility model do not limit by the foregoing description, and should be the maximum magnitude that meets the inventive features that claims mention.
Claims (9)
1. a flash array hub is characterized in that, comprising:
The serial datum input port is used to connect other flash array hub;
The serial datum output port is used to connect other flash array hub or computing machine;
Several parallel data input ports are used to connect other flash array hub or flash memory device;
Processor chips connect this serial data input port, this serial data output port and this several parallel data input ports, are used for the deal with data storage.
2. a stacked flash array is characterized in that, is made up of several flash array hubs, and wherein each flash array hub comprises:
Several parallel data input ports are used to connect flash memory device or other flash array hub;
The serial datum input port is used to connect other flash array hub;
The serial datum output port is used to connect other flash array hub or computing machine;
Processor chips connect this serial data input port, this serial data output port and this several parallel data input ports, are used for the deal with data storage.
3. stacked flash array according to claim 2 is characterized in that, these several parallel data input ports comprise usb type, SD card type or miniature SD card type.
4. stacked flash array according to claim 2 is characterized in that, this serial data input port and this serial data output port comprise the transmission of wireless signals interface.
5. the flash array of an intersecting is characterized in that, is made up of several flash array hubs, and wherein each flash array hub comprises:
Several parallel data input ports are used to connect flash memory device or other flash array hub;
The serial datum input port is used to connect other flash array hub;
The serial datum output port is used to connect other flash array hub or computing machine;
Processor chips connect this serial data input port, this serial data output port and this several parallel data input ports, are used for the deal with data storage;
Wherein several parallel data input ports of each flash array hub are the configuration relations that is cross-linked with flash memory device that is connected or other flash array hub.
6. the flash array of intersecting according to claim 5 is characterized in that, the configuration of the relation that is cross-linked of the parallel data input port in the flash array hub is that the mode by the circuit board wiring realizes.
7. the flash array of intersecting according to claim 5 is characterized in that, the configuration of the relation that is cross-linked of the parallel data input port in the flash array hub is that the mode by the software control in the flash array hub realizes.
8. the flash array of intersecting according to claim 5 is characterized in that, these several parallel data input ports comprise usb type, SD card type or miniature SD card type.
9. the flash array of intersecting according to claim 5 is characterized in that, this serial data input port and this serial data output port comprise the transmission of wireless signals interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010205192382U CN201788702U (en) | 2010-09-07 | 2010-09-07 | Flash array concentrator, cascaded flash array and staggered and cascaded flash array |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2010205192382U CN201788702U (en) | 2010-09-07 | 2010-09-07 | Flash array concentrator, cascaded flash array and staggered and cascaded flash array |
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| CN201788702U true CN201788702U (en) | 2011-04-06 |
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| CN2010205192382U Expired - Lifetime CN201788702U (en) | 2010-09-07 | 2010-09-07 | Flash array concentrator, cascaded flash array and staggered and cascaded flash array |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101976574A (en) * | 2010-09-07 | 2011-02-16 | 苏州壹世通科技有限公司 | Flash array concentrator, stacked flash array and cross stacked flash array |
-
2010
- 2010-09-07 CN CN2010205192382U patent/CN201788702U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101976574A (en) * | 2010-09-07 | 2011-02-16 | 苏州壹世通科技有限公司 | Flash array concentrator, stacked flash array and cross stacked flash array |
| CN101976574B (en) * | 2010-09-07 | 2013-09-25 | 苏州壹世通科技有限公司 | Flash array concentrator, stacked flash array and cross stacked flash array |
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