CN202257088U - GPS (global positioning system) frequency scale locking time interval measuring system based on TDC-GP2 chip - Google Patents
GPS (global positioning system) frequency scale locking time interval measuring system based on TDC-GP2 chip Download PDFInfo
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- CN202257088U CN202257088U CN2011203115418U CN201120311541U CN202257088U CN 202257088 U CN202257088 U CN 202257088U CN 2011203115418 U CN2011203115418 U CN 2011203115418U CN 201120311541 U CN201120311541 U CN 201120311541U CN 202257088 U CN202257088 U CN 202257088U
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Abstract
The utility model provides a GPS (global positioning system) frequency scale locking time interval measuring system based on a TDC-GP2 chip, which comprises a GPS receiving unit, TDC-GP2 chip units, an FPGA (field programmable gate array) frequency divider and a singlechip, wherein the GPS receiving unit and the FPGA frequency divider are respectively connected with the TDC-GP2 chip units; and the singlechip is connected with the TDC-GP2 chip units. The GPS frequency scale locking time interval measuring system based on the TDC-GP2 chip can widen the measuring range to -3.25ms-+3.25ms without adding any hardware circuit, and the time resolution can reach 65PS.
Description
Technical field
The utility model relates to a kind of GPS frequency marking interval measurement locking time system, relates in particular to a kind of GPS frequency marking interval measurement locking time system based on the TDC-GP2 chip.
Background technology
Resolution is superior to the time interval measurement technology of nanosecond; Not only important effect is arranged in fundamental research fields such as geodynamics research, relativity research, pulsar cycle studies and artificial satellite dynamics geodetics; And in such as applied research, national defence and the developments of the national economy such as Aero-Space, deep space communication, satellites transmits and monitoring, geological mapping, navigation communication, electric power transfer and Scientific Measurements, general application is arranged also, be deep into the people different social sectors.
Traditional time interval measurement method has length vernier method, analog interpolation, TVC time-amplitude conversion method etc.Though length vernier method measuring accuracy is very high, it is narrow to be superior to measurement range, and its application is restricted; The analog interpolation temporal resolution was lower than for 0.1 nanosecond, the mimic channel more complicated, and difficulty is all compared in debugging and calibration.TVC time-amplitude transformation approach, same mimic channel more complicated, debugging is difficulty, and time resolution is lower than 400PS.
The utility model content
The utility model relates to a kind of GPS frequency marking interval measurement locking time system based on the TDC-GP2 chip, is not increasing in addition under the situation of hardware circuit, can make measurement range expand to-3.25ms～+ 3.25ms, temporal resolution reaches 65PS.
The technical solution of the utility model is: a kind of GPS frequency marking interval measurement locking time system based on the TDC-GP2 chip, and its special character is: said measuring system comprises GPS receiving element, TDC-GP2 chip unit, FPGA frequency divider and single-chip microcomputer; Said GPS receiving element and FPGA frequency divider are connected to the TDC-GP2 chip unit; Said single-chip microcomputer is connected with the TDC-GP2 chip unit.
Said system also comprises the 10M high stability crystal oscillator, and said 10M high stability crystal oscillator is connected with TDC-GP2 chip unit and FPGA frequency divider respectively.
Above-mentioned FPGA frequency divider output two-way signal second, wherein leading another road signal second of signal one tunnel second.
The temporal resolution of above-mentioned TDC-GP2 chip unit is 65PS.
Above-mentioned single-chip microcomputer is MSP430.
The utility model proposes the GPS frequency marking interval measurement locking time system based on the TDC-GP2 chip, 1) circuit is simple, cheap, and temporal resolution can reach 65PS; 2) increase by one road frequency division output 1PPS2, solved the range and the phase problem of time interval measurement cleverly, range ability can reach-3.25 milliseconds～+ 3.25 milliseconds.
Description of drawings
Fig. 1 is the structural representation of the utility model;
Fig. 2, Fig. 3 are the embodiment synoptic diagram of the utility model;
Embodiment
Referring to Fig. 1, the GPS frequency marking interval measurement locking time system based on the TDC-GP2 chip of the utility model comprises GPS receiving element 1, TDC-GP2 chip unit 2, FPGA frequency divider 3,10M high stability crystal oscillator 4 and MSP430 single-chip microcomputer 5; GPS receiving element 1 is connected to TDC-GP2 chip unit 2 with FPGA frequency divider 3 and 10M high stability crystal oscillator 4; 10M high stability crystal oscillator 4 outputs one road signal is connected to TDC_GP2 as high-frequency clock; FPGA frequency divider 3 output two-way signal second 1PPS1 and 1PPS2.
Frequently be set at 4 when TDC-GP2 presorts, 10Mhz is that 2.5Mhz is as the inner high speed clock through 4 frequency divisions.Measurement range one is 2.0ns-1.8us; Measurement range two is 800ns-6.553ms; Temporal resolution is 65PS.Two measurement ranges all have automatic calibration function, use very flexible.Owing in the GPS frequency marking lock-in techniques, require the scope of time interval measurement wide more good more, obviously TDC-GP2 measurement range one 2.0ns-1.8us can not satisfy request for utilization.Measurement range two is 800ns-6.553ms, and the reference time measurement upper limit can meet the demands, but not energy measurement less than the time interval of 800ns.In GPS frequency marking interval measurement locking time, time deviation mainly concentrates on the 0-800ns scope.Therefore to use TDC_GP2 must expand measurement range.
The measuring system principle of work of the utility model is referring to Fig. 1, Fig. 2, and 1PPS is the second signal of GPS receiving element 1 output among the figure, and 1PPS1 is the pulse per second (PPS) of local crystal oscillator 10Mhz frequency division output; 1PPS2 is the subsidiary signal of leading 1PPS13.25mS.Through measuring the time interval of 1PPS2 and 1PPS, can obtain the phase place time difference of 1PPS and 1PPS1 indirectly.Can find out among Fig. 1 that 1PPS1 does not participate in measuring, dotted line is marked among Fig. 2, shows sequential relationship.Because TDC-GP2 inner high speed clock is 2.5Mhz, therefore the leading 1PPS1 of corresponding 2.5Mhz frequency 1PPS2 is 8125 clock period.In measurement range 2, measurement result is the multiple in high-frequency clock cycle.For example; The time interval that TDC-GP2 chip unit 2 is measured between beginning START (1PPS2) and the STOP (1PPS) is 8125 clock period; 8125 clock period that deduct the leading 1PPS1 of 1PPS2 just in time equal 0, and the 1PPS1 that dotted line as shown in Figure 2 is represented just in time aims at the 1PPS phase place.
If the 1PPS2 that measures and the 1PPS time interval were 9800.1258 clock period.Referring to Fig. 3,9800.1258 deduct 8125 equals 1675.1258, shows 1675.1258 clock period of the leading 1PPS of 1PPS1 phase place.
If the 1PPS2 that measures and the 1PPS time interval were 6800.0123 clock period, deduct 8125 and equal-1324.9877 and show 1324.9877 clock period of 1PPS1 phase lag 1PPS.
Claims (5)
1. GPS frequency marking interval measurement locking time system based on the TDC-GP2 chip, it is characterized in that: said measuring system comprises GPS receiving element, TDC-GP2 chip unit, FPGA frequency divider and single-chip microcomputer; Said GPS receiving element and FPGA frequency divider are connected to the TDC-GP2 chip unit; Said single-chip microcomputer is connected with the TDC-GP2 chip unit.
2. the GPS frequency marking interval measurement locking time system based on the TDC-GP2 chip according to claim 1; It is characterized in that: said system also comprises the 10M high stability crystal oscillator, and said 10M high stability crystal oscillator is connected with TDC-GP2 chip unit and FPGA frequency divider respectively.
3. the GPS frequency marking interval measurement locking time system based on the TDC-GP2 chip according to claim 2 is characterized in that: said FPGA frequency divider output two-way signal second, wherein leading another road signal second of signal one tunnel second.
4. according to claim 1 or 2 or 3 described GPS frequency marking interval measurement locking time systems based on the TDC-GP2 chip, it is characterized in that: the temporal resolution of said TDC-GP2 chip unit is 65PS.
5. the GPS frequency marking interval measurement locking time system based on the TDC-GP2 chip according to claim 4, it is characterized in that: said single-chip microcomputer is MSP430.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011203115418U CN202257088U (en) | 2011-08-25 | 2011-08-25 | GPS (global positioning system) frequency scale locking time interval measuring system based on TDC-GP2 chip |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011203115418U CN202257088U (en) | 2011-08-25 | 2011-08-25 | GPS (global positioning system) frequency scale locking time interval measuring system based on TDC-GP2 chip |
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| CN202257088U true CN202257088U (en) | 2012-05-30 |
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| CN2011203115418U Expired - Lifetime CN202257088U (en) | 2011-08-25 | 2011-08-25 | GPS (global positioning system) frequency scale locking time interval measuring system based on TDC-GP2 chip |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103412474A (en) * | 2013-05-24 | 2013-11-27 | 西安交通大学 | TDC-GP2 time study range high-precision expansion circuit based on FPGA |
| CN105629704A (en) * | 2016-01-14 | 2016-06-01 | 北京卫星导航中心 | Time interval measurement accuracy metrological verification method and device of controlled frequency offset |
| CN111061145A (en) * | 2019-12-30 | 2020-04-24 | 嘉兴泰传光电有限公司 | Time delay settable time interval measuring device and measuring method based on FPGA |
-
2011
- 2011-08-25 CN CN2011203115418U patent/CN202257088U/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103412474A (en) * | 2013-05-24 | 2013-11-27 | 西安交通大学 | TDC-GP2 time study range high-precision expansion circuit based on FPGA |
| CN103412474B (en) * | 2013-05-24 | 2015-11-25 | 西安交通大学 | Range high-precision expanded circuit when TDC-GP2 based on FPGA surveys |
| CN105629704A (en) * | 2016-01-14 | 2016-06-01 | 北京卫星导航中心 | Time interval measurement accuracy metrological verification method and device of controlled frequency offset |
| CN111061145A (en) * | 2019-12-30 | 2020-04-24 | 嘉兴泰传光电有限公司 | Time delay settable time interval measuring device and measuring method based on FPGA |
| CN111061145B (en) * | 2019-12-30 | 2022-07-05 | 嘉兴泰传光电有限公司 | Time delay settable time interval measuring device and measuring method based on FPGA |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: NINGBO XIDIAN LIREN INFORMATION TECHNOLOGY CO., LT Free format text: FORMER OWNER: XI'AN LIREN SCIENCE + TECHNOLOGY CO., LTD. Effective date: 20140731 |
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| C41 | Transfer of patent application or patent right or utility model | ||
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Free format text: CORRECT: ADDRESS; FROM: 710065 XI'AN, SHAANXI PROVINCE TO: 315200 NINGBO, ZHEJIANG PROVINCE |
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| TR01 | Transfer of patent right |
Effective date of registration: 20140731 Address after: 2, building 123, block B, West Ningbo Industrial Park, No. 315200 West Zhenning Road, Zhejiang, Ningbo Patentee after: Ningbo Xidian Information Technology Co., Ltd. Address before: 710065, Xi'an high tech Road, Shaanxi province 52 No. six Liren science and Technology Park, block A, 6 Patentee before: Xi'an Liren Technology Co., Ltd. |
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| TR01 | Transfer of patent right |
Effective date of registration: 20191213 Address after: 710065, Xi'an high tech Zone, Shaanxi province six hi tech Road, 52, set up science and Technology Park, A block, 4 floor Patentee after: Xi'an Liren Science and Technology Co., Ltd. Address before: 2, building 123, block B, West Ningbo Industrial Park, No. 315200 West Zhenning Road, Zhejiang, Ningbo Patentee before: Ningbo Xidian Information Technology Co., Ltd. |
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Granted publication date: 20120530 |
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| CX01 | Expiry of patent term |