CN109120260A - A kind of clock module high-precision phase demodulation system and method based on ASIC-TDC - Google Patents
A kind of clock module high-precision phase demodulation system and method based on ASIC-TDC Download PDFInfo
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- H—ELECTRICITY
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- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
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Abstract
The present invention relates to technical field of communication equipment, disclose a kind of clock module high-precision phase demodulation system and method based on ASIC-TDC, including local clock module, signal processor, ASIC-TDC chip and reference clock module；Signal processor includes PLL times of frequency module, system clock module, PID computing module and 1PPSForTdc signal output module, and system clock generates local 1PPS signal；Signal processor receives the reference signal of reference clock module compared with the 1PPS signal of local, obtain thick phase demodulation value, signal processor exports the second local 1PPS signal to the Start pin of ASIC-TDC chip, with reference to the Stop pin of 1PPS signal input ASIC-TDC chip, ASIC-TDC chip carries out thin phase demodulation according to the second local 1PPS signal and with reference to 1PPS signal.The present invention solve ASIC-TDC test scope it is too small and can only single direction measurement limitation, precision of phase discrimination when locking can be stablized with reference to 1PPS is increased to 50ps or so, the short steady precision for having matched local clock well, greatly improves the stability of clock module.
Description
Technical field
The present invention relates to technical field of communication equipment, in particular to a kind of clock module high-precision based on ASIC-TDC is reflected
Phase system and method.
Background technique
Current communication network is higher and higher to the time synchronization requirement synchronous with clock, and global environment deteriorates, natural
Disaster takes place frequently, it is ensured that and on the one hand the stabilization of time dissemination system and constant needs to take more reference source redundancy backups, and in addition one
Aspect need reference source fail in the case where, still keep high-precision punctual ability within a certain period of time, due to TD-SCDMA,
It is 24 hours 1.5us that the clock synchronous networks of new generation such as the synchronous net of WiMax, electric power, which want the holding capacity of seeking time, this index is suitable
It is 1.74E-11 in 24 hourly average frequency offsets, is very harsh index.
Requirements above local clock has very high stability and punctual ability, and wherein the high stability of local clock is just
The stability of phase accuracy and local clock output frequency including local 1PPS.It is local in high-precision time service Time keeping system
Clock generallys use atomic clock and two kinds of OCXO, and the second of usually atomic clock surely in E-10 magnitude, the second of OCXO surely in E-11, shows
So, the local 1PPS phase bps stability that local clock generates can eventually pass through PID if precision of phase discrimination is not better than ns better than ns
The short-term stability that will deteriorate local clock when control local clock is gone, while bringing unnecessary shaking to local 1PPS,
So that the stability decline of whole clock module, therefore improving precision of phase discrimination is to improve time service Time keeping system clock module to stablize
One of key link of degree.
TDC (Time-to-Digital Converter) is known as time-to-digital converter technology, for measuring two time things
The interval of part is widely used in time and frequency measurement, aerospace, satellite navigation, radar fix, laser ranging, nuclear physics and particle
The fields such as physical detecting, and the advanced level in these fields and the precision of time interval measurement are closely related.TDC implementation method
Mainly there are direct counting method, vernier method, gate delays mensuration etc., reaches the high-precision TDC technology master of ps class precision at present
It to be based on gate delays mensuration principle, is divided into ASIC-TDC and two kinds of implementations of FPGA-TDC, is determined since ASIC belongs to
Circuit processed can allow the path delay of signal to immobilize, and FPGA will receive the influence of placement-and-routing's strategy, and being difficult construction has
The delay chain of good delay consistency, therefore realize that the resolution ratio of TDC is difficult within 200ps by FPGA, and ASIC-
TDC can realize the measurement accuracy better than 50ps.
There are mainly three types of the ways of the 1PPS phase demodulation of industry internal clock module progress at present: 1) using the system of FPGA/CPLD
Clock carries out counting phase demodulation；The precision of phase discrimination of this scheme depends primarily on input clock, is usually taken 10MHz times of local clock
Frequency is used as input clock to several hundred million, then counts phase demodulation along simultaneously using rise and fall, can achieve higher precision of phase discrimination,
But it is generally only ns grades；2) MCU system clock timer timing phase demodulation is used；This way precision of phase discrimination depends on what MCU was supported
Highest system clock, within generally 200MHz, precision of phase discrimination is also only 5ns or so.This two kinds of ways are several hundred due to producing
Million system clock will increase system power dissipation, can also generate radio frequency interference；3) FPGA-TDC implementation is used；The method needs
Larger size of code is wanted, another aspect precision is also difficult to accomplish within 200ps.
Although ASIC-TDC is able to achieve the measurement accuracy better than 50ps, but its application has some limitations: (1) measurement range
Us grades are generally only, by taking the ASIC-TDC chip of German ACAM company as an example, measurement range is 2.0ns~1.8us, Bu Nengman
The requirement of sufficient clock module 1PPS phase measurement range highest 1s, and it is unable to measure the phase difference less than 2ns；(2) it can only carry out
Single direction measurement, i.e., can only test the time interval from Start pin 1PPS signal to Stop pin 1PPS signal, if
The 1PPS phase lag signal of Start pin is then unable to measure in the 1PPS signal of Stop pin, i.e., can not generate negative phase difference,
And clock module two 1PPS signal phases when calibrating clock can constantly replace, phase difference has positive and negative variation.
Since phase difference is generally stabilized within 100ns clock module when locking is with reference to 1PPS, ASIC- is complied fully with
TDC measurement range can carry out fine phase demodulation, during upper electric tracing phase difference it is excessive exceed ASIC-TDC measurement range when adopt
With system clock phase demodulation, adjusts local clock and draw small phase difference, precision of phase discrimination reaches ns grades at this time.
Summary of the invention
Invention is designed to provide a kind of clock module high-precision phase demodulation system and method based on ASIC-TDC, this hair
It is bright solve ASIC-TDC test scope it is too small and can only single direction measurement limitation, be successfully applied to clock module
High-precision phase demodulation, precision of phase discrimination when locking can be stablized with reference to 1PPS is increased to 50ps or so, with traditional phase detecting method phase
Than improving about 100 times, the short steady precision of local clock is had matched well, greatly improves the stability of clock module, with
Solve the problems mentioned above in the background art.
To achieve the above object, the invention provides the following technical scheme:
A kind of clock module high-precision phase demodulation system based on ASIC-TDC, including local clock module, signal processor,
ASIC-TDC chip and reference clock module；The signal processor includes PLL times of frequency module, system clock module, PID meter
Calculate module and 1PPSForTdc signal output module, the rate-adaptive pacemaker module output frequency of the local clock module to PLL
Times frequency module, the PLL times of frequency module carry out frequency multiplication to frequency and are sent to system clock module, and system clock module generates system
System clock, system clock generate local 1PPS signal；
The signal processor receives the reference signal of reference clock module compared with the 1PPS signal of local, obtains thick phase demodulation
Value, PID computing module calculate voltage-controlled value according to thick phase demodulation value and are sent to the voltage-controlled end of local clock module, local clock module
According to the output frequency of voltage-controlled value adjustment rate-adaptive pacemaker module, signal processor exports the second local 1PPS signal to ASIC-TDC
The Start pin of chip, with reference to the Stop pin of 1PPS signal input ASIC-TDC chip, the ASIC-TDC chip is according to the
Two local 1PPS signals and reference 1PPS signal carry out thin phase demodulation.
Further, the local clock module is OCXO, and signal processor is ARM chip, and OCXO and ARM chip connect
It connects, thick phase demodulation is carried out by ARM chip.
Further, the second local 1PPS signal is the 1PPSForTdc signal for having fixed phase difference with local 1PPS signal,
Thin phase demodulation threshold value is set according to the stability of reference clock and the maximum time measurement range of ASIC-TDC chip.
Further, voltage-controlled value is calculated according to thick phase demodulation value in PID computing module, and voltage-controlled value is sent to OCXO's
Voltage-controlled end, OCXO adjust frequency according to the voltage-controlled value.
The present invention provides a kind of another technical solution: clock module High Resolution Phase Detecting Method based on ASIC-TDC, packet
Include following steps:
S1, thick phase demodulation: local 1PPS signal phase value is compared with the phase value with reference to 1PPS signal, obtains phase
Difference carries out thick phase demodulation, obtains thick phase demodulation value when phase difference is greater than thin phase demodulation threshold value；
S2, frequency adjustment: voltage-controlled value is calculated according to thick phase demodulation value, the voltage-controlled end of local clock module is adjusted according to voltage-controlled value
The frequency of local clock module；
S3, thin phase demodulation: when the frequency of local clock module adjust to make phase difference be less than thin phase demodulation threshold value when, pass through
The time measurement function of ASIC-TDC chip carries out thin phase demodulation, adjusts the phase value.
Further, step S1 specifically: OCXO offer 10MHz signal input ARM chip, PLL times of ARM chip interior
10MHz signal frequency multiplication is 150MHz as system clock module by frequency module, and system clock module generates local 1PPS signal,
Local 1PPS signal compared with the reference 1PPS signal that reference clock module inputs carries out capture, is obtained thick phase demodulation by ARM chip
Value.
Further, thin phase demodulation threshold value is 100ns.
Compared with prior art, the beneficial effects of the present invention are: the clock module proposed by the present invention based on ASIC-TDC
High-precision phase demodulation system and method, the present invention by the ps grade high precision time measurement functional application of ASIC-TDC in clock module into
The thin phase demodulation of row, will not band while improving precision of phase discrimination in conjunction with the thick phase demodulation scheme of ns grade of traditional MCU or FPGA/CPLD
It improves power consumption height caused by clock frequency and interferes big problem, the present invention is compared with traditional phase detecting method, precision of phase discrimination energy
100 times or so are improved, the raising of precision of phase discrimination is beneficial to subsequent clock module tracks locking precision and keeps algorithm modeling essence
The raising of degree solves the too small limitation with single direction measurement of measurement range of ASIC-TDC, is successfully applied to clock
The high-precision phase demodulation of module improves about 100 times of precision of phase discrimination compared to traditional phase detecting method, so that tracking sensitivity mentions significantly
Height finally improves the frequency stability of local 1PPS phase stability and local clock.
Detailed description of the invention
Fig. 1 is the hardware block diagram of the clock module high-precision phase demodulation system of ASIC-TDC of the invention；
Fig. 2 is the flow chart of the clock module High Resolution Phase Detecting Method of ASIC-TDC of the invention.
In figure: 1, local clock module；11, rate-adaptive pacemaker module；2, signal processor；21, PLL times of frequency module；22, it is
System clock module；23, PID computing module；24,1PPSForTdc signal output module；3, ASIC-TDC chip；4, reference clock
Module.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Referring to Fig. 1, a kind of clock module high-precision phase demodulation system based on ASIC-TDC, including local clock module 1,
Signal processor 2, ASIC-TDC chip 3 and reference clock module 4；Signal processor 2 includes PLL times of frequency module 21, system
Clock module 22, PID computing module 23 and 1PPSForTdc signal output module 24, local clock module 1 are OCXO (constant temperature
Crystal oscillator), signal processor 2 is ARM chip, and OCXO is connect with ARM chip, carries out thick phase demodulation by ARM chip, substantially
Principle is local clock module 1OCXO tracking lock with reference to 1PPS signal, itself frequency is harmonized while reaching adjustment local 1PPS
The purpose of rate may finally export accurately local 1PPS signal and frequency signal.The rate-adaptive pacemaker module of local clock module 1
To PLL times of frequency module 21, PLL times of frequency module 21 carries out frequency multiplication to frequency and is sent to system clock module 22 11 output frequencies,
System clock module 22 generates system clock, and system clock generates local 1PPS signal, and PID computing module 23 is according to thick phase demodulation value
Voltage-controlled value is calculated, and voltage-controlled value is sent to the voltage-controlled end of OCXO, OCXO adjusts frequency according to voltage-controlled value；
Signal processor 2 receives the reference signal of reference clock module 4 compared with the 1PPS signal of local, obtains thick phase demodulation
Value, PID computing module 23 calculate voltage-controlled value according to thick phase demodulation value and are sent to the voltage-controlled end of local clock module 1, local clock
Module 1 adjusts the output frequency of rate-adaptive pacemaker module 11 according to voltage-controlled value, and signal processor 2 exports the second local 1PPS signal and arrives
The Start pin of ASIC-TDC chip 3, with reference to the Stop pin of 1PPS signal input ASIC-TDC chip 3, due to ASIC-TDC
The signal of input Start pin can only be tested to the signal of Stop pin, i.e., if the 1PPS signal of input Stop is ahead of
The 1PPS signal of Start, ASIC-TDC measurement will malfunction.Therefore it needs in addition to generate one and has fixed phase difference with local 1PPS
1PPSForTdc signal dedicated for the thin phase demodulation of ASIC-TDC, in such a way that thickness phase demodulation combines, local 1PPS with
When larger with reference to 1PPS phase phase difference, phase adjustment is carried out according to the phase value that traditional thick phase detecting method obtains, when two
It is switched to ASIC-TDC chip 3 when the small Mr. Yu's threshold value of 1PPS phase difference and carries out thin phase demodulation, the second local 1PPS signal is and local
1PPS signal has the 1PPSForTdc signal of fixed phase difference, in the 1PPSForTdc signal for having fixed phase difference dedicated for ASIC-
The thin phase demodulation of TDC is switched to ASIC-TDC chip 3 in the small Mr. Yu's threshold value of phase difference and carries out thin phase demodulation, this threshold value is according to reference
The stability of 1PPS and the maximum time measurement range of ASIC-TDC are set, due to 1PPSForTdc be by MCU or
The thick phase demodulation system of FPGA/CPLD generates, so fixed phase difference must be set to the integral multiple of thick precision of phase discrimination, otherwise finally changes
The phase demodulation value of calculation has error.
Referring to Fig. 2, a kind of clock module High Resolution Phase Detecting Method based on ASIC-TDC, comprising the following steps:
S1, thick phase demodulation: local 1PPS signal phase value is compared with the phase value with reference to 1PPS signal, obtains phase
Difference, when phase difference is greater than thin phase demodulation threshold value, thin phase demodulation threshold value is 100ns, carries out thick phase demodulation, it is defeated that OCXO provides 10MHz signal
Enter ARM chip, 10MHz signal frequency multiplication is 150MHz as system clock module by the PLL times of frequency module 21 of ARM chip interior
22, system clock module 22 generates local 1PPS signal, and ARM chip inputs local 1PPS signal and reference clock module 4
Capture comparison is carried out with reference to 1PPS signal, obtains thick phase demodulation value；
S2, frequency adjustment: voltage-controlled value is calculated according to thick phase demodulation value, the voltage-controlled end of local clock module 1 is adjusted according to voltage-controlled value
The frequency of whole local clock module 1；Voltage-controlled value is calculated according to thick phase demodulation value in PID computing module 23, and voltage-controlled value is sent
To the voltage-controlled end of OCXO, OCXO adjusts frequency according to voltage-controlled value；
S3, thin phase demodulation: when the frequency of local clock module 1 adjust to make phase difference be less than thin phase demodulation threshold value when, pass through
The time measurement function of ASIC-TDC chip 3 carries out thin phase demodulation, adjustment phase place value, and the output of ARM chip has with local 1PPS signal
The 1PPSForTdc signal of fixed phase difference inputs ASIC-TDC core with reference to 1PPS signal to the Start pin of ASIC-TDC chip 3
The Stop pin of piece 3, when phase difference is less than thin phase demodulation threshold value, ASIC-TDC chip 3 carries out thin phase demodulation, thin phase demodulation threshold value according to
The stability of reference clock and the maximum time measurement range of ASIC-TDC chip 3 are set, and thin phase demodulation threshold value is 100ns.
The present invention using local OCXO output 10MHz it is divided after obtain 5MHz input ASIC-TDC as calibrate clock, then
The greatest measurement of ASIC-TDC is 2*Tref=400ns；Start signal can only be accurately calculated additionally, due to ASIC-TDC to arrive
The phase difference of Stop signal, this method are believed by the 1PPSForTdc signal fixed lead generated by ARM chip in local 1PPS
Number 200ns phase, the value of phase demodulation is switched to ASIC-TDC when thick phase demodulation value is arranged in less than 100ns, then track stablize when
Thin phase demodulation value -200 phase demodulation value=TDC, precision is about 50ps.
The working principle of the invention: firstly, providing 10MHz signal by local clock module 1OCXO inputs ARM chip, ARM
PLL times of frequency module of chip interior is to 150MHz as system clock.Local 1PPS signal is generated by system clock, the ginseng with input
It examines 1PPS signal and carries out capture comparison, obtain thick phase demodulation value, then the precision of this thick phase demodulation value is 1/150us, about 6.67ns, is led to
The pid algorithm for crossing PID computing module 23 obtains the frequency for the voltage-controlled end adjustment OCXO of VC that corresponding voltage-controlled value controls OCXO, when
OCXO frequency is harmonized to a certain extent, when so that local 1PPS and reference 1PPS phase difference being less than 100ns, is switched to ASIC-TDC
Thin phase demodulation value carries out PID calculating, and the precision of this thin phase demodulation value is about 50ps, to reach high-precision phase demodulation time service purpose.
To sum up, the clock module high-precision phase demodulation system and method proposed by the present invention based on ASIC-TDC, the present invention will
The ps grade high precision time measurement functional application of ASIC-TDC carries out thin phase demodulation in clock module, in conjunction with traditional MCU or FPGA/
The thick phase demodulation scheme of the ns grade of CPLD, while improving precision of phase discrimination, will not bring power consumption height caused by improving clock frequency with
Big problem is interfered, the present invention is compared with traditional phase detecting method, and precision of phase discrimination can improve 100 times or so, the raising of precision of phase discrimination
It is beneficial to subsequent clock module tracks locking precision and keeps the raising of algorithm modeling accuracy, solve the measurement of ASIC-TDC
The too small limitation with single direction measurement of range, is successfully applied to the high-precision phase demodulation of clock module, compared to traditional phase demodulation
Method improves about 100 times of precision of phase discrimination, so that tracking sensitivity greatly improves, finally improves local 1PPS phase stability
With the frequency stability of local clock.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
Anyone skilled in the art within the technical scope of the present disclosure, according to the technique and scheme of the present invention and its
Inventive concept is subject to equivalent substitution or change, should be covered by the protection scope of the present invention.
Claims (7)
1. a kind of clock module high-precision phase demodulation system based on ASIC-TDC, including local clock module (1), signal processor
(2), ASIC-TDC chip (3) and reference clock module (4)；It is characterized in that, the signal processor (2) includes PLL times
Frequency module (21), system clock module (22), PID computing module (23) and 1PPSForTdc signal output module (24), institute
Rate-adaptive pacemaker module (11) output frequency of local clock module (1) is stated to PLL times of frequency module (21), the PLL times of frequency module
(21) frequency multiplication is carried out to frequency and be sent to system clock module (22), system clock module (22) generates system clock, system
Clock generates local 1PPS signal；
The signal processor (2) receives the reference signal of reference clock module (4) compared with the 1PPS signal of local, is slightly reflected
Mutually it is worth, PID computing module (23) calculates voltage-controlled value according to thick phase demodulation value and is sent to the voltage-controlled end of local clock module (1), this
Output frequency of the ground clock module (1) according to voltage-controlled value adjustment rate-adaptive pacemaker module (11), signal processor (2) output second
Ground 1PPS signal inputs the Stop of ASIC-TDC chip (3) with reference to 1PPS signal to the Start pin of ASIC-TDC chip (3)
Pin, the ASIC-TDC chip (3) carry out thin phase demodulation according to the second local 1PPS signal and with reference to 1PPS signal.
2. a kind of clock module high-precision phase demodulation system based on ASIC-TDC according to claim 1, which is characterized in that
The local clock module (1) is OCXO, and signal processor (2) is ARM chip, and OCXO is connect with ARM chip, passes through ARM core
Piece carries out thick phase demodulation.
3. a kind of clock module high-precision phase demodulation system based on ASIC-TDC according to claim 1, which is characterized in that
Second local 1PPS signal is the 1PPSForTdc signal for having fixed phase difference with local 1PPS signal, and thin phase demodulation threshold value is according to reference
The stability of clock and the maximum time measurement range of ASIC-TDC chip (3) are set.
4. a kind of clock module high-precision phase demodulation system based on ASIC-TDC according to claim 1, which is characterized in that
Voltage-controlled value is calculated according to thick phase demodulation value in PID computing module (23), and voltage-controlled value is sent to the voltage-controlled end of OCXO, OCXO root
Frequency is adjusted according to the voltage-controlled value.
5. a kind of clock module High Resolution Phase Detecting Method according to claim 1 based on ASIC-TDC, which is characterized in that
The following steps are included:
S1, thick phase demodulation: local 1PPS signal phase value being compared with the phase value with reference to 1PPS signal, obtains phase difference,
When phase difference is greater than thin phase demodulation threshold value, thick phase demodulation is carried out, thick phase demodulation value is obtained；
S2, frequency adjustment: voltage-controlled value is calculated according to thick phase demodulation value, the voltage-controlled end of local clock module (1) is adjusted according to voltage-controlled value
The frequency of local clock module (1)；
S3, thin phase demodulation: when the frequency of local clock module (1) adjust to make phase difference be less than thin phase demodulation threshold value when, pass through
The time measurement function of ASIC-TDC chip (3) carries out thin phase demodulation, adjusts the phase value.
6. a kind of clock module High Resolution Phase Detecting Method based on ASIC-TDC according to claim 5, which is characterized in that
Step S1 specifically: OCXO provides 10MHz signal and inputs ARM chip, and the PLL times of frequency module (21) of ARM chip interior is by 10MHz
Signal frequency multiplication is 150MHz as system clock module (22), and system clock module (22) generates local 1PPS signal, ARM chip
By local 1PPS signal compared with the reference 1PPS signal that reference clock module (4) inputs carries out capture, thick phase demodulation value is obtained.
7. a kind of clock module High Resolution Phase Detecting Method based on ASIC-TDC according to claim 5, which is characterized in that
Thin phase demodulation threshold value is 100ns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811042050.0A CN109120260A (en) | 2018-09-07 | 2018-09-07 | A kind of clock module high-precision phase demodulation system and method based on ASIC-TDC |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811042050.0A CN109120260A (en) | 2018-09-07 | 2018-09-07 | A kind of clock module high-precision phase demodulation system and method based on ASIC-TDC |
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| CN109120260A true CN109120260A (en) | 2019-01-01 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111143048A (en) * | 2019-12-25 | 2020-05-12 | 西安电子工程研究所 | Radar accurate timing method based on VxWorks system clock |
| CN113364550A (en) * | 2020-03-04 | 2021-09-07 | 大唐移动通信设备有限公司 | Clock adjusting method and device |
-
2018
- 2018-09-07 CN CN201811042050.0A patent/CN109120260A/en not_active Withdrawn
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111143048A (en) * | 2019-12-25 | 2020-05-12 | 西安电子工程研究所 | Radar accurate timing method based on VxWorks system clock |
| CN111143048B (en) * | 2019-12-25 | 2022-10-28 | 西安电子工程研究所 | Radar accurate timing method based on VxWorks system clock |
| CN113364550A (en) * | 2020-03-04 | 2021-09-07 | 大唐移动通信设备有限公司 | Clock adjusting method and device |
| CN113364550B (en) * | 2020-03-04 | 2022-07-19 | 大唐移动通信设备有限公司 | Clock adjusting method and device |
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Application publication date: 20190101 |