CN202210472U - Capacitor and electronic device possessing same - Google Patents
Capacitor and electronic device possessing same Download PDFInfo
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- CN202210472U CN202210472U CN2011203051825U CN201120305182U CN202210472U CN 202210472 U CN202210472 U CN 202210472U CN 2011203051825 U CN2011203051825 U CN 2011203051825U CN 201120305182 U CN201120305182 U CN 201120305182U CN 202210472 U CN202210472 U CN 202210472U
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Abstract
The utility model relates to a capacitor and an electronic device possessing the same. The capacitor includes a first pole plate, a second pole plate, and a dielectric layer arranged between the first pole plate and the second pole plate. The first pole plate and the second pole plate are electrically connected with a device structure in a semiconductor chip. The first pole plate is a block conducting layer in a top conducting layer of the semiconductor chip. The chip is arranged on a base plate. The second pole plate is arranged on the base plate. The technical scheme utilizes the top conducting layer of the chip and the conducting layer of an external base plate to form a big capacitance for circuit use, and does not increase extra cost.
Description
Technical field
The utility model relates to field of semiconductor devices, the electronic device that relates in particular to capacitor and comprise this capacitor.
Background technology
Capacitor is a kind of element that can store electric charge, also is one of the most frequently used electronic component.In DC circuit, capacitor is equivalent to open circuit.In alternating current circuit; Electric current becomes certain functional relation to change in time, and capacitor charging/discharging process need certain hour, this time; Forming the electric field that changes on the capacitor between bottom crown; This electric field also is time dependent function, and in fact, electric current is to pass through between capacitor through the form of field.Capacitor utilizes the element of its characteristic in alternating current circuit as the storage electric charge.
As a kind of element of storing electric charge, capacitor has various uses, and it can be used as shunt capacitance is that local device provides the accumulator for accumulating energy part, makes the output homogenizing of pressurizer, reduces loading demand; Also can be used as decoupling capacitor and play the effect of " battery ", satisfy the drive circuit change in current, avoid mutual coupled interference; Can also be used as other effect such as filtering, energy storage.
All have capacitor in the electronic device chip of prior art, this capacitor is formed on chip internal usually, utilizes the two conductive layers of chip internal and the dielectric layer between the two conductive layers to form capacitor.Many patent and patent applications about capacitor are arranged in the prior art, and for example the application number of application on April 10th, 1998 is 98106601.1 patent application, discloses a kind of " capacitor that forms the method for integrated-circuit capacitor and form thus ".
The utility model content
The purpose of the utility model is to provide a kind of new capacitor, utilizes the conductive layer on chip top layer conductive layer and the external substrate to form big electric capacity, and use on the power supply road, does not increase extra cost simultaneously.
For addressing the above problem; The utility model specific embodiment provides a kind of capacitor; Comprise first pole plate, second pole plate and the capacitor dielectric layer between first pole plate and second pole plate, said first pole plate, second pole plate are electrically connected with the inner device architecture of semiconductor chip respectively;
Block conductive layer in the top layer conductive layer that said first pole plate is said semiconductor chip;
Said semiconductor chip is located on the substrate, and said second pole plate is positioned on the said substrate.
Optional, the top layer conductive layer surface of said semiconductor chip has passivation layer; Said semiconductor chip is installed on the substrate after encapsulation, and said first pad-face is to said substrate, and the semiconductor chip surface after the said encapsulation has encapsulation medium;
Have conductive layer on said substrate and the said first pole plate facing surfaces, this conductive layer is as said second pole plate;
Said capacitor dielectric layer comprises encapsulation medium, the air between said passivation layer, said first pole plate and said second pole plate.
Optional, said semiconductor chip is installed on the substrate after encapsulation, and the said dorsad substrate of said first pole plate;
Have conductive layer on said substrate and the said first pole plate facing surfaces, this conductive layer is as said second pole plate;
Said capacitor dielectric layer comprises dielectric layer, the air between said first pole plate and said second pole plate.
Optional, the said dorsad substrate of said first pole plate; Have conductive layer on said substrate and the said first pole plate facing surfaces, this conductive layer is as said second pole plate;
Said capacitor dielectric layer comprises dielectric layer, the air between said first pole plate and said second pole plate.
Optional, the top layer conductive layer surface of said semiconductor chip has passivation layer; Said first pad-face is to said substrate; Have conductive layer on said substrate and the said first pole plate facing surfaces, this conductive layer is as said second pole plate;
Said capacitor dielectric layer comprises said passivation layer, air.
Optional, said substrate is pcb board, ceramic substrate or silicon substrate.
Optional, the material of said first pole plate is the nonmetal of metal or conduction; The material of said second pole plate is the nonmetal of metal or conduction.
The utility model also provides a kind of electronic device that comprises above each described capacitor.
Compared with prior art, the utility model technical scheme has the following advantages:
The capacitor of the utility model specific embodiment does not form in semiconductor chip; And be formed between semiconductor chip top layer and the external substrate; First pole plate is the block conductive layer in the top layer conductive layer of said semiconductor chip; Said chip is located on the outside substrate, and second pole plate is positioned on the substrate; Dielectric layer is the dielectric layer between said first pole plate and second pole plate.The present technique scheme utilizes the block conductive layer in the chip top layer conductive layer to form big electric capacity with conductive layer on the outside substrate like this, and use on the power supply road, does not increase extra cost simultaneously.
Description of drawings
Fig. 1 is for showing the schematic top plan view of semiconductor chip top layer conductive layer;
Fig. 2 is the cross-sectional view of the capacitor of the utility model first embodiment;
Fig. 3 is the cross-sectional view of the capacitor of the utility model second embodiment;
Fig. 4 is the cross-sectional view of the capacitor of the utility model the 3rd embodiment;
Fig. 5 is the cross-sectional view of the capacitor of the utility model the 4th embodiment.
Embodiment
In order to make those skilled in the art better understood the utility model,, the capacitor of the utility model is detailed below in conjunction with specific embodiment.
In the semiconductor technology, the method that forms semiconductor chip is generally: substrate is provided, on this substrate, forms device layer, this device layer can comprise a plurality of transistors, also can comprise a plurality of other devices, and the kind of device is definite according to the function that chip institute will realize.After forming device layer, need above device layer, form interconnection structure each device in the device layer is electrically connected, also possibly above device layer, form other device layer, then form interconnection structure then again.After interconnection structure forms; With reference to figure 1, form one deck conductive layer at the chip top layer, be called the top layer conductive layer in the utility model; The conductive layer 11 that has a plurality of bulks in the top layer conductive layer, block conductive layer 11 is used separately as electric power connection line, ground wire connecting line or signal connecting line.
For the performance that prevents that the top layer conductive layer is corroded, oxidation etc. influences semiconductor chip, on this top layer conductive layer, form passivation layer usually, to protect this top layer conductive layer.
Utilize in the semiconductor chip the block conductive layer in the top layer conductive layer as first pole plate of capacitor in the utility model; First pole plate can be original block conductive layer in the top layer conductive layer; Such as in order to do the block conductive layer of electric power connection line, ground wire connecting line or signal connecting line; But be not limited to original block conductive layer in the top layer conductive layer, can form block conductive layer at top layer specially in order to form electric capacity.
Need to prove; " the top layer conductive layer " described in the utility model refers to the conductive layer of the top one deck in the semiconductor chip; The conductive layer that has a plurality of bulks in the top layer conductive layer; In the utility model specific embodiment, " block conductive layer " refers to the block conductive layer with certain function that marks off in the top layer conductive layer can be used separately as electric power connection line, ground wire connecting line or signal connecting line.
Below in conjunction with specific embodiment, specify the capacitor of the utility model.
First specific embodiment
After semiconductor chip forms, can encapsulate semiconductor chip, after encapsulation is accomplished, on semiconductor chip surface, can form one deck encapsulation medium layer, this encapsulation medium layer is used for sealing, protection chip and strengthen electric heating property.After semiconductor chip encapsulated completion, semiconductor chip is fixed on the substrate for use, this substrate can be pcb board, also can be ceramic substrate, can also be silicon substrate etc.
With reference to figure 2, in this first specific embodiment, after semiconductor chip 10 encapsulation are accomplished, semiconductor chip 10 upside-down mountings are located on the substrate 20.Therefore; In this first embodiment, first pole plate is the block conductive layer 11 in the top layer conductive layer of semiconductor chip, and semiconductor chip 10 is installed on the substrate 20 after encapsulation; First pad-face is to said substrate 20; That is to say for semiconductor chip 10, the first pole plates near substrate 20, and the substrate in the semiconductor chip 10 (among the figure not label) is away from substrate 20.On the top layer conductive layer, be formed with passivation layer 12, semiconductor chip 10 surfaces after the said encapsulation have encapsulation medium 13, have conductive layer 21 on substrate 20 and the said first pole plate facing surfaces, and this conductive layer 21 is as said second pole plate.Capacitor dielectric layer comprises encapsulation medium 13 and the air between this passivation layer 12, said first pole plate and said second pole plate.
First pole plate of capacitor is electrically connected with other interior devices of semiconductor chip through the interconnection structure in the semiconductor chip, and said second pole plate is electrically connected with the device architecture of chip internal through substrate.Because substrate is the carrier of semiconductor chip; And semiconductor chip is electrically connected with other outside devices through substrate; Usually on substrate, be formed with the circuit that is electrically connected with the device of chip internal, therefore can be electrically connected with the inner device architecture of semiconductor chip, that is to say that second pole plate is connected with this line electricity through the circuit that forms on the substrate; The device of chip internal is connected with this line electricity, is electrically connected with the device of chip internal to realize second pole plate.
The kind of the capacitor that can use according to reality about the area of first pole plate, second pole plate, between the two distance and the dielectric layer kind between first pole plate and second pole plate is confirmed.The material of said first pole plate is the nonmetal of metal or conduction.The material of said second pole plate is the nonmetal of metal or conduction.
This first specific embodiment utilizes block conductive layer and the conductive layer on the external substrate in the chip top layer conductive layer to form electric capacity, and use on the power supply road, does not increase extra cost simultaneously.
Second specific embodiment
With reference to figure 3, in this second specific embodiment, semiconductor chip does not have upside-down mounting, and the substrate of semiconductor chip 10 is nearest from substrate 20, and the block conductive layer 11 in the top layer conductive layer is substrate 20 dorsad, that is to say first pole plate substrate 20 dorsad; Have conductive layer 21 on substrate 20 and the said first pole plate facing surfaces, this conductive layer 21 is as said second pole plate; The dielectric layer of capacitor comprises other dielectric materials such as dielectric layer between said first pole plate and said second pole plate, air.Dielectric layer between first pole plate and second pole plate can be confirmed according to the semiconductor chip that reality forms.
The semiconductor chip upside-down mounting of first embodiment is on substrate; Second embodiment does not have upside-down mounting, and therefore in first embodiment and second embodiment, the material that capacitor dielectric layer comprises can be had any different; Other details of the capacitor of second embodiment can be with reference to first embodiment, does not do at this and give unnecessary details.
The 3rd embodiment
In figure 4, the three embodiment, semiconductor chip 10 not encapsulation is installed on the substrate 20, and semiconductor chip 10 upside-down mountings are on substrate 20, and this substrate 20 can be pcb board, also can be ceramic substrate, can also be for silicon substrate etc.
On the block conductive layer 11 of top layer conductive layer, be formed with passivation layer 12, capacitor dielectric layer comprises the passivation layer 12 between said first pole plate and said second pole plate, just is formed on passivation layer 12 and air on the block conductive layer 11.
The difference of the 3rd embodiment and first embodiment is: the semiconductor chip of first embodiment has passed through encapsulation, and the semiconductor chip of the 3rd embodiment is through encapsulation, and the part identical with first embodiment do not done at this and to be given unnecessary details.
The 3rd specific embodiment utilizes chip top layer conductive layer and conductive layer on the outside substrate to form electric capacity, and use on the power supply road, does not increase extra cost simultaneously.
The 4th embodiment
In figure 5, the four embodiment, semiconductor chip 10 is encapsulation not, and semiconductor chip 10 is installed on the substrate 20, and this substrate 20 can be pcb board, also can be ceramic substrate, can also be for silicon substrate etc.
Capacitor dielectric layer comprises other dielectric materials such as dielectric layer between said first pole plate and said second pole plate, air.Dielectric layer between first pole plate and second pole plate can be confirmed according to the semiconductor chip that reality forms.Because semiconductor chip does not have upside-down mounting, so does not comprise passivation layer 12 in the dielectric layer of capacitor.
Other are identical with second embodiment, do not do at this and give unnecessary details.
The utility model embodiment also provides a kind of electronic device, and said electronic device comprises any capacitor described in above-mentioned first embodiment, second embodiment, the 3rd embodiment and the 4th embodiment.
The above is merely the specific embodiment of the utility model; In order to make those skilled in the art better understand the spirit of the utility model; Yet the protection range of the utility model is not a limited range with the specific descriptions of this specific embodiment; Any those skilled in the art can make an amendment the specific embodiment of the utility model in the scope that does not break away from the utility model spirit, and does not break away from the protection range of the utility model.
Claims (8)
1. a capacitor comprises first pole plate, second pole plate and the capacitor dielectric layer between first pole plate and second pole plate, and said first pole plate, second pole plate are electrically connected with the inner device architecture of semiconductor chip respectively;
It is characterized in that,
Block conductive layer in the top layer conductive layer that said first pole plate is said semiconductor chip;
Said semiconductor chip is located on the substrate, and said second pole plate is positioned on the said substrate.
2. capacitor as claimed in claim 1 is characterized in that, the top layer conductive layer surface of said semiconductor chip has passivation layer; Said semiconductor chip is installed on the substrate after encapsulation, and said first pad-face is to said substrate, and the semiconductor chip surface after the said encapsulation has encapsulation medium;
Have conductive layer on said substrate and the said first pole plate facing surfaces, this conductive layer is as said second pole plate;
Said capacitor dielectric layer comprises encapsulation medium, the air between said passivation layer, said first pole plate and said second pole plate.
3. capacitor as claimed in claim 1 is characterized in that, said semiconductor chip is installed on the substrate after encapsulation, and the said dorsad substrate of said first pole plate;
Have conductive layer on said substrate and the said first pole plate facing surfaces, this conductive layer is as said second pole plate;
Said capacitor dielectric layer comprises dielectric layer, the air between said first pole plate and said second pole plate.
4. capacitor as claimed in claim 1 is characterized in that, the said dorsad substrate of said first pole plate; Have conductive layer on said substrate and the said first pole plate facing surfaces, this conductive layer is as said second pole plate;
Said capacitor dielectric layer comprises dielectric layer, the air between said first pole plate and said second pole plate.
5. capacitor as claimed in claim 1 is characterized in that, the top layer conductive layer surface of said semiconductor chip has passivation layer; Said first pad-face is to said substrate; Have conductive layer on said substrate and the said first pole plate facing surfaces, this conductive layer is as said second pole plate;
Said capacitor dielectric layer comprises said passivation layer, air.
6. capacitor as claimed in claim 1 is characterized in that, said substrate is pcb board, ceramic substrate or silicon substrate.
7. capacitor as claimed in claim 1 is characterized in that, the material of said first pole plate is the nonmetal of metal or conduction; The material of said second pole plate is the nonmetal of metal or conduction.
8. electronic device that comprises each described capacitor of claim 1～7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011203051825U CN202210472U (en) | 2011-08-19 | 2011-08-19 | Capacitor and electronic device possessing same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011203051825U CN202210472U (en) | 2011-08-19 | 2011-08-19 | Capacitor and electronic device possessing same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202210472U true CN202210472U (en) | 2012-05-02 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011203051825U Expired - Fee Related CN202210472U (en) | 2011-08-19 | 2011-08-19 | Capacitor and electronic device possessing same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202210472U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102385986A (en) * | 2011-08-19 | 2012-03-21 | 上海丽恒光微电子科技有限公司 | Capacitor and electronic device with same |
| CN104062026A (en) * | 2013-03-22 | 2014-09-24 | 上海丽恒光微电子科技有限公司 | Temperature sensor |
-
2011
- 2011-08-19 CN CN2011203051825U patent/CN202210472U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102385986A (en) * | 2011-08-19 | 2012-03-21 | 上海丽恒光微电子科技有限公司 | Capacitor and electronic device with same |
| CN104062026A (en) * | 2013-03-22 | 2014-09-24 | 上海丽恒光微电子科技有限公司 | Temperature sensor |
| CN104062026B (en) * | 2013-03-22 | 2017-04-26 | 上海丽恒光微电子科技有限公司 | Temperature sensor |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120502 Termination date: 20150819 |
|
| EXPY | Termination of patent right or utility model |