CN202206373U - Double-group switched capacitor circuits suitable for flow line type analog-digital converter - Google Patents
Double-group switched capacitor circuits suitable for flow line type analog-digital converter Download PDFInfo
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- CN202206373U CN202206373U CN2011202870701U CN201120287070U CN202206373U CN 202206373 U CN202206373 U CN 202206373U CN 2011202870701 U CN2011202870701 U CN 2011202870701U CN 201120287070 U CN201120287070 U CN 201120287070U CN 202206373 U CN202206373 U CN 202206373U
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Abstract
The utility model discloses double-group switched capacitor circuits suitable for a flow line type analog-digital converter, which comprise an operational amplifier, a sub digital-analog converter, two groups of switched capacitor circuits, two groups of dynamic element matching circuits and two groups of registers. Two groups of switched capacitor circuits are used in the utility model for alternately sampling and operating, so that a sampling and holding operational amplifier can be saved, thereby improving the performance and reducing the current consumption of the converter.
Description
Technical field
The utility model relates to a kind of two group switched-capacitor circuits that are applicable to the pipeline system analog-digital converter.
Background technology
Traditional multidigit pipeline system analog-digital converter needs an operational amplifier to be used for realizing that sampling keeps, and can introduce extra snr loss and current drain.
The utility model content
A kind of two group switched-capacitor circuits that are applicable to the pipeline system analog-digital converter that the utility model provides avoid the use of sampling and keep operational amplifier, not only can improve performance but also can reduce current drain.
In order to achieve the above object; The utility model provides a kind of two group switched-capacitor circuits that are applicable to the pipeline system analog-digital converter; This pair group switched-capacitor circuit comprises operational amplifier, sub-figure analog converter, first switched-capacitor circuit and second switch condenser network; The first dynamic element match circuit and the second dynamic element match circuit, and first register and second register;
Input input analog input signal Vin and total clock signal ph of said sub-figure analog converter, output output digital output signal Dout;
The output of the input connexon digital analog converter of the said first dynamic element match circuit;
The output of the input connexon digital analog converter of the said second dynamic element match circuit;
The input of said first register connects the output of the first dynamic element match circuit, and the input of first register is imported the first clock signal ph1;
The input of said second register connects the output of the second dynamic element match circuit, the input input second clock signal ph2 of second register;
The input of said first switched-capacitor circuit connects the output of first register and operational amplifier; Input input analog input signal Vin and positive reference voltage signal vrefp, zero reference voltage signal vcm, the negative reference voltage signal vrefn of first switched-capacitor circuit, and analog output signal Vout;
The input of said second switch condenser network connects the output of second register and operational amplifier; Input input analog input signal Vin and positive reference voltage signal vrefp, zero reference voltage signal vcm, the negative reference voltage signal vrefn of second switch condenser network, and analog output signal Vout;
The input of said operational amplifier connects first switched-capacitor circuit and second switch condenser network, the output output analog output signal Vout of operational amplifier.
Described first switched-capacitor circuit comprises n equivalent capacitor C 1, C2 ..., Cn, n input switch Sa1, Sa2 ..., San, n multiselect switch Sb 1, Sb2 ..., Sbn, an output switch S c and an earthed switch Sd;
Described each input switch Sa1, Sa2 ..., equivalent capacitor C 1 of the corresponding connection of the end of San, C2 ..., Cn, the other end connect input analog input signal Vin; Described each multiselect switch Sb 1, Sb2 ..., the end of Sbn can select to connect positive reference voltage signal vrefp; Perhaps zero reference voltage signal vcm, perhaps negative reference voltage signal vrefn, perhaps analog output signal Vout, the other end is corresponding to connect an equivalent capacitor C 1; C2 ..., Cn; The break-make of described output switch S c is controlled by the first clock signal ph1, when the first clock signal ph1 is closed when being high, opens when low; Described earthed switch Sd is by second clock signal ph2 control, when second clock signal ph2 is closed when being high, opens when low.
Described input switch Sa1, Sa2 ..., the break-make of San is by second clock signal ph2 control, when second clock signal ph2 is closed when being high, opens when low.
Each signal of first register output all is used for controlling a multiselect switch, and when this signal was 1, the multiselect switch met positive reference voltage signal vrefp; When this signal is 0; Multiselect switch connecting to neutral reference voltage signal vcm, when this signal was-1, the multiselect switch met negative reference voltage signal vrefn; When being not above situation, the multiselect switch meets analog output signal Vout.
Described second switch condenser network comprises n equivalent capacitor C 1, C2 ..., Cn, n input switch Sa1, Sa2 ..., San, n multiselect switch Sb 1, Sb2 ..., Sbn, an output switch S c and an earthed switch Sd;
Described each input switch Sa1, Sa2 ..., equivalent capacitor C 1 of the corresponding connection of the end of San, C2 ..., Cn, the other end connect input analog input signal Vin; Described each multiselect switch Sb 1, Sb2 ..., the end of Sbn can select to connect positive reference voltage signal vrefp; Perhaps zero reference voltage signal vcm, perhaps negative reference voltage signal vrefn, perhaps analog output signal Vout, the other end is corresponding to connect an equivalent capacitor C 1; C2 ..., Cn; The break-make of described output switch S c is by second clock signal ph2 control, when second clock signal ph2 is closed when being high, opens when low; Described earthed switch Sd is controlled by the first clock signal ph1, when the first clock signal ph1 is closed when being high, opens when low.
Described input switch Sa1, Sa2 ..., the break-make of San is controlled by the first clock signal ph1, when the first clock signal ph1 is closed when being high, opens when low.
Each signal of second register output all is used for controlling a multiselect switch, and when this signal was 1, the multiselect switch met positive reference voltage signal vrefp; When this signal is 0; Multiselect switch connecting to neutral reference voltage signal vcm, when this signal was-1, the multiselect switch met negative reference voltage signal vrefn; When being not above situation, the multiselect switch meets analog output signal Vout.
The frequency of total clock signal ph is the twice of the first clock signal ph1 and second clock signal ph2 frequency; The rising edge of the first clock signal ph1 is consistent with the odd number rising edge sequential of total clock signal ph; The rising edge of second clock signal ph2 is consistent with the even number rising edge sequential of total clock signal ph; Perhaps; The rising edge of the first clock signal ph1 is consistent with the even number rising edge sequential of total clock signal ph, and the rising edge of second clock signal ph2 is consistent with the odd number rising edge sequential of total clock signal ph.
The capacitance of described n equivalent electric capacity equates that its value is C0.
The utility model uses two groups of switched-capacitor circuits, and hocket sampling and computing so just can avoid the use of sampling and keep operational amplifier, not only can improve performance but also can reduce current drain.
Description of drawings
Fig. 1 is the circuit diagram of the utility model;
Fig. 2 is the clock signal sequential chart of the utility model.
Embodiment
Following according to Fig. 1 and Fig. 2, specify the preferred embodiment of the utility model:
As shown in Figure 1; It is the circuit diagram that is applicable to two group switched-capacitor circuits of pipeline system analog-digital converter; These two group switched-capacitor circuits that are applicable to the pipeline system analog-digital converter comprise operational amplifier 4,1, two group of switched-capacitor circuit 301 of sub-figure analog converter and 302; Two groups of dynamic element match circuits 101 and 102, and two groups of registers 201 and 202.
Input input analog input signal Vin and total clock signal ph of said sub-figure analog converter 1, output output digital output signal Dout.
The output of the input connexon digital analog converter 1 of the said first dynamic element match circuit 101.
The output of the input connexon digital analog converter 1 of the said second dynamic element match circuit 102.
The input of said first register 201 connects the output of the first dynamic element match circuit 101, and the input of first register 201 is imported the first clock signal ph1.
The input of said second register 202 connects the output of the second dynamic element match circuit 102, the input input second clock signal ph2 of second register 202.
The input of said first switched-capacitor circuit 301 connects the output of first register 201 and operational amplifier 4; Input input analog input signal Vin and positive reference voltage signal vrefp, zero reference voltage signal vcm, the negative reference voltage signal vrefn of first switched-capacitor circuit 301, and analog output signal Vout.
The input of said second switch condenser network 302 connects the output of second register 202 and operational amplifier 4; Input input analog input signal Vin and positive reference voltage signal vrefp, zero reference voltage signal vcm, the negative reference voltage signal vrefn of second switch condenser network 302, and analog output signal Vout.
The input of said operational amplifier 4 connects first switched-capacitor circuit 301 and second switch condenser network 302, the output output analog output signal Vout of operational amplifier 4.
Described first switched-capacitor circuit 301 comprises n equivalent capacitor C 1, C2 ..., Cn, n input switch Sa1, Sa2 ..., San, n multiselect switch Sb 1, Sb2 ..., Sbn, an output switch S c and an earthed switch Sd; Described each input switch Sa1, Sa2 ..., equivalent capacitor C 1 of the corresponding connection of the end of San; C2 ..., Cn, the other end connect input analog input signal Vin; Input switch Sa1, Sa2 ... The break-make of San is by second clock signal ph2 control, when second clock signal ph2 is closed when being high, opens when low; Described each multiselect switch Sb 1, Sb2 ..., the end of Sbn can select to connect signal vrefp; Perhaps vcm, perhaps vrefn, perhaps analog output signal Vout, the other end is corresponding to connect an equivalent capacitor C 1; C2 ..., Cn, each signal of first register, 201 outputs all is used for controlling a multiselect switch; When this signal was 1, the multiselect switch met vrefp, and when this signal was 0, the multiselect switch met vcm; When this signal was-1, the multiselect switch met vrefn, and when being not above situation, the multiselect switch meets analog output signal Vout; The break-make of described output switch S c is controlled by the first clock signal ph1, when the first clock signal ph1 is closed when being high, opens when low; Described earthed switch Sd is by second clock signal ph2 control, when second clock signal ph2 is closed when being high, opens when low.
Described second switch condenser network 302 comprises n equivalent capacitor C 1, C2 ..., Cn, n input switch Sa1, Sa2 ..., San, n multiselect switch Sb 1, Sb2 ..., Sbn, an output switch S c and an earthed switch Sd; Described each input switch Sa1, Sa2 ..., equivalent capacitor C 1 of the corresponding connection of the end of San; C2 ..., Cn, the other end connect input analog input signal Vin; Input switch Sa1, Sa2 ... The break-make of San is controlled by the first clock signal ph1, when the first clock signal ph1 is closed when being high, opens when low; Described each multiselect switch Sb 1, Sb2 ..., the end of Sbn can select to connect signal vrefp; Perhaps vcm, perhaps vrefn, perhaps analog output signal Vout, the other end is corresponding to connect an equivalent capacitor C 1; C2 ..., Cn, each signal of second register, 202 outputs all is used for controlling a multiselect switch; When this signal was 1, the multiselect switch met vrefp, and when this signal was 0, the multiselect switch met vcm; When this signal was-1, the multiselect switch met vrefn, and when being not above situation, the multiselect switch meets analog output signal Vout; The break-make of described output switch S c is by second clock signal ph2 control, when second clock signal ph2 is closed when being high, opens when low; Described earthed switch Sd is controlled by the first clock signal ph1, when the first clock signal ph1 is closed when being high, opens when low.
As shown in Figure 2; It is the sequential chart of total clock signal ph, the first clock signal ph1 and second clock signal ph2; The frequency of total clock signal ph is the twice of the first clock signal ph1 and second clock signal ph2 frequency; The rising edge of the first clock signal ph1 is consistent with the odd number rising edge sequential of total clock signal ph, and the rising edge of second clock signal ph2 is consistent with the even number rising edge sequential of total clock signal ph, perhaps; The rising edge of the first clock signal ph1 is consistent with the even number rising edge sequential of total clock signal ph, and the rising edge of second clock signal ph2 is consistent with the odd number rising edge sequential of total clock signal ph.
The pipelined analog digital quantizer has a lot of level, the just one-level wherein that the utility model is described.The quantization error signal of this one-level is exported by operational amplifier, can be transported to next stage and continue to convert to digital signal, thereby make whole analog-digital converter reach higher precision.
As shown in Figure 1; The structure that the wherein one-level that two group switched-capacitor circuits that the utility model is described are the pipelined analog digital quantizer is suitable for; It has input end of analog signal, digital signal output end, and analog signal output (being the quantization error output); Its operation sequential chart is as shown in Figure 2, and total clock signal ph, the first clock signal ph1 and second clock signal ph2 are provided by other circuit.
Have n equivalent electric capacity respectively in first switched-capacitor circuit 301 and the second switch condenser network 302, its value is C0, is numbered C1, C2 ... Cn, connected input switch are Sa1, Sa2 ..., San; The multiselect switch is Sb1, Sb2 ..., Sbn; With first switched-capacitor circuit 301 is example, and as second clock signal ph2 when being high, Sa1 to San all closes, and voltage signal charges to electric capacity; Vin samples to analog input signal, when second clock signal ph2 when low, input switch Sa1 to San all opens, sampling finishes; In like manner, second switch condenser network 302 is sampled to analog input signal Vin when being high at the first clock signal ph1.
With first switched-capacitor circuit 301 is example, and the total amount of electric charge that each sampling obtains is:
Submodule intend digital quantizer 1 total clock signal ph when being high to analog input signal Vin, and at the trailing edge of total clock signal ph the output of the digital signal of conversion.The output that submodule is intended digital quantizer 1 is sent to first switched-capacitor circuit 301 when being high at the first clock signal ph1 after through dynamic element match circuit and register, is sent to second switch condenser network 302 when being high at second clock signal ph2.Each signal of register output all is used for controlling a multiselect switch, and when this signal of register output was 1, the multiselect switch met vrefp; When being 0, the multiselect switch meets vcm; When being-1, the multiselect switch meets vrefn; When being not above situation, the multiselect switch connects operational amplifier output, and promptly analog output signal Vout has at every turn and have only a multiselect switch connection analog output signal Vout.
Be example still, suppose that capacitor C n connects analog output signal Vout with first switched-capacitor circuit 301, the output signal di=-1 of first register 201,0 or 1, i=1 wherein, 2 ..., n-1.The total amount of electric charge that the first clock signal ph1 obtains when being high is:
Thereby the digital signal of bundle analog-digital converter 1 output converts analog signal into.
Since charge conservation, Q1=Q2, so
First switched-capacitor circuit 301 can deduct the analog signal that is converted to from the input signal that sampling obtains, the output that obtains is exactly to amplify the quantization error that n submodule is doubly intended digital quantizer.
Like this; Using first switched-capacitor circuit 301 to calculate the quantization error of gained can be in first clock signal ph1 output when high; Use quantization error that second switch condenser network 302 calculates to be delivered to the conversion that next stage is proceeded analog signal to digital signal in second clock signal ph2 output when high.
Although the content of the utility model has been done detailed introduction through above-mentioned preferred embodiment, will be appreciated that above-mentioned description should not be considered to the restriction to the utility model.After those skilled in the art have read foregoing, for the multiple modification of the utility model with to substitute all will be conspicuous.Therefore, the protection range of the utility model should be limited appended claim.
Claims (9)
1. two group switched-capacitor circuits that are applicable to the pipeline system analog-digital converter; It is characterized in that; This pair group switched-capacitor circuit comprises operational amplifier (4), sub-figure analog converter (1), first switched-capacitor circuit (301) and second switch condenser network (302); The first dynamic element match circuit (101) and the second dynamic element match circuit (102), and first register (201) and second register (202);
Input input analog input signal Vin and total clock signal ph of said sub-figure analog converter (1), output output digital output signal Dout;
The output of the input connexon digital analog converter (1) of the said first dynamic element match circuit (101);
The output of the input connexon digital analog converter (1) of the said second dynamic element match circuit (102);
The input of said first register (201) connects the output of the first dynamic element match circuit (101), and the input of first register (201) is imported the first clock signal ph1;
The input of said second register (202) connects the output of the second dynamic element match circuit (102), the input input second clock signal ph2 of second register (202);
The input of said first switched-capacitor circuit (301) connects the output of first register (201) and operational amplifier (4); Input input analog input signal Vin and positive reference voltage signal vrefp, zero reference voltage signal vcm, the negative reference voltage signal vrefn of first switched-capacitor circuit (301), and analog output signal Vout;
The input of said second switch condenser network (302) connects the output of second register (202) and operational amplifier (4); Input input analog input signal Vin and positive reference voltage signal vrefp, zero reference voltage signal vcm, the negative reference voltage signal vrefn of second switch condenser network (302), and analog output signal Vout;
The input of said operational amplifier (4) connects first switched-capacitor circuit (301) and second switch condenser network (302), the output output analog output signal Vout of operational amplifier (4).
2. the two group switched-capacitor circuits that are applicable to the pipeline system analog-digital converter as claimed in claim 1 is characterized in that described first switched-capacitor circuit (301) comprises n equivalent capacitor C 1, C2;, Cn, n input switch Sa1, Sa2;, San, n multiselect switch Sb 1, Sb2;, Sbn, an output switch S c and an earthed switch Sd;
Described each input switch Sa1, Sa2 ..., equivalent capacitor C 1 of the corresponding connection of the end of San, C2 ..., Cn, the other end connect input analog input signal Vin; Described each multiselect switch Sb 1, Sb2 ..., the end of Sbn can select to connect positive reference voltage signal vrefp; Perhaps zero reference voltage signal vcm, perhaps negative reference voltage signal vrefn, perhaps analog output signal Vout, the other end is corresponding to connect an equivalent capacitor C 1; C2 ..., Cn; The break-make of described output switch S c is controlled by the first clock signal ph1, when the first clock signal ph1 is closed when being high, opens when low; Described earthed switch Sd is by second clock signal ph2 control, when second clock signal ph2 is closed when being high, opens when low.
3. the two group switched-capacitor circuits that are applicable to the pipeline system analog-digital converter as claimed in claim 2 is characterized in that described input switch Sa1; Sa2 ..., the break-make of San is controlled by second clock signal ph2; When second clock signal ph2 is closed when being high, open when low.
4. the two group switched-capacitor circuits that are applicable to the pipeline system analog-digital converter as claimed in claim 2 is characterized in that each signal of first register (201) output all is used for controlling a multiselect switch; When this signal is 1; The multiselect switch meets positive reference voltage signal vrefp, when this signal is 0, and multiselect switch connecting to neutral reference voltage signal vcm; When this signal is-1; The multiselect switch meets negative reference voltage signal vrefn, and when being not above situation, the multiselect switch meets analog output signal Vout.
5. the two group switched-capacitor circuits that are applicable to the pipeline system analog-digital converter as claimed in claim 1 is characterized in that described second switch condenser network (302) comprises n equivalent capacitor C 1, C2;, Cn, n input switch Sa1, Sa2;, San, n multiselect switch Sb 1, Sb2;, Sbn, an output switch S c and an earthed switch Sd;
Described each input switch Sa1, Sa2 ..., equivalent capacitor C 1 of the corresponding connection of the end of San, C2 ..., Cn, the other end connect input analog input signal Vin; Described each multiselect switch Sb 1, Sb2 ..., the end of Sbn can select to connect positive reference voltage signal vrefp; Perhaps zero reference voltage signal vcm, perhaps negative reference voltage signal vrefn, perhaps analog output signal Vout, the other end is corresponding to connect an equivalent capacitor C 1; C2 ..., Cn; The break-make of described output switch S c is by second clock signal ph2 control, when second clock signal ph2 is closed when being high, opens when low; Described earthed switch Sd is controlled by the first clock signal ph1, when the first clock signal ph1 is closed when being high, opens when low.
6. the two group switched-capacitor circuits that are applicable to the pipeline system analog-digital converter as claimed in claim 5 is characterized in that described input switch Sa1; Sa2 ..., the break-make of San is controlled by the first clock signal ph1; When the first clock signal ph1 is closed when being high, open when low.
7. the two group switched-capacitor circuits that are applicable to the pipeline system analog-digital converter as claimed in claim 5 is characterized in that each signal of second register (202) output all is used for controlling a multiselect switch; When this signal is 1; The multiselect switch meets positive reference voltage signal vrefp, when this signal is 0, and multiselect switch connecting to neutral reference voltage signal vcm; When this signal is-1; The multiselect switch meets negative reference voltage signal vrefn, and when being not above situation, the multiselect switch meets analog output signal Vout.
8. like any described two group switched-capacitor circuits that are applicable to the pipeline system analog-digital converter among the claim 1-7; It is characterized in that; The frequency of total clock signal ph is the twice of the first clock signal ph1 and second clock signal ph2 frequency; The rising edge of the first clock signal ph1 is consistent with the odd number rising edge sequential of total clock signal ph, and the rising edge of second clock signal ph2 is consistent with the even number rising edge sequential of total clock signal ph, perhaps; The rising edge of the first clock signal ph1 is consistent with the even number rising edge sequential of total clock signal ph, and the rising edge of second clock signal ph2 is consistent with the odd number rising edge sequential of total clock signal ph.
9. like claim 2 or the 5 described two group switched-capacitor circuits that are applicable to the pipeline system analog-digital converter, it is characterized in that the capacitance of described n equivalent electric capacity equates that its value is C0.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011202870701U CN202206373U (en) | 2011-08-09 | 2011-08-09 | Double-group switched capacitor circuits suitable for flow line type analog-digital converter |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011202870701U CN202206373U (en) | 2011-08-09 | 2011-08-09 | Double-group switched capacitor circuits suitable for flow line type analog-digital converter |
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| CN202206373U true CN202206373U (en) | 2012-04-25 |
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| CN2011202870701U Expired - Lifetime CN202206373U (en) | 2011-08-09 | 2011-08-09 | Double-group switched capacitor circuits suitable for flow line type analog-digital converter |
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Address after: Room 403, No. 2966 Jinke Road, Zhangjiang High-tech Park, Pudong New Area, Shanghai, 201203 Patentee after: Lexin Information Technology (Shanghai) Co., Ltd. Address before: Room 403, No. 2966 Jinke Road, Zhangjiang High-tech Park, Pudong New Area, Shanghai, 201203 Patentee before: Yue Xin information technology (Shanghai) Co., Ltd. |
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Granted publication date: 20120425 |