The test probe platform of image sensor chip
Technical field
The utility model relates to the testing apparatus of a kind of imageing sensor (CIS) chip, especially relates to the probe station that is applied to the performance test of imageing sensor (CIS) sensing chip.
Background technology
Probe station is a kind of equipment that is used for wafer sort in the semiconductor production process; It is accomplished the wafer sort probe card and contacts with the reliable of wafer mainly as the precision positioning unit, and the signal linkage function of probe station and test machine etc.; Observing and controlling pin platform in being referred to as, implementation step is following:
1, will have multi-plate chip to arrange the Silicon Wafer that links together is positioned on the probe station;
2, Electric Machine Control XY locatees to motion platform, and wherein a slice semi-conductor chip to be measured in the Silicon Wafer is positioned under the probe testing needle;
3, Electric Machine Control Z makes the wafer lifting to lifting table, and the wherein a slice semi-conductor chip in the wafer is contacted with the probe testing needle;
4, probe station sends the signal that begins to test to test machine, and test machine is received the beginning test signal, begins semi-conductor chip is tested, and after test was accomplished, test machine returned to probe station with test result;
5, after probe station is received test result, semi-conductor chip is handled, and kept corresponding data confession later process according to test result;
6, probe station navigate to next semi-conductor chip to be measured, repeat the 2-5 step, accomplish up to whole wafer sort.
Surveying probe station in this has good positioning function, and probe station is connected simply with the signal of test machine, still, not can be applicable to CIS chip testing.
The CIS chip is a kind of image-signal processor chip, and this chip aims at image sensor chip, and it is handled the light of accepting (image), extensively is used in scanner, facsimile recorder, DV, the camera.Along with the continuous expansion in CIS chip application market, JEDEC pallet dress or CHIP pallet dress CIS chip testing machine are used more and more widely, and concrete testing procedure is following:
CIS chip to be measured is loaded in JEDEC or the CHIP pallet, and pallet is packed in the feed bin of automatic charging, picks and places mechanical arm and from pallet, picks up the CIS chip and be positioned in the measurement jig; Light source is in the polishing of CIS chip optical surface, and test machine begins the CIS chip is tested, after test is accomplished; Light source is closed; Pick and place mechanical arm and from measurement jig, pick up the CIS chip again, the CIS chip is classified and put into another pallet according to test result, CIS chip testing is accomplished in all pallets to be measured.
Because in the CIS chip testing process, the CIS chip all is being placed in the pallet of monolithic, every test a slice all need repeat chip picked up puts action; Damage chip easily; The possibility that causes yield to descend, and bearing accuracy is bad, makes tester table abnormality processing often occur; Pick up and put the non-cutting time that the action needs are grown, so the testing efficiency of test machine is also very low.
The utility model content
The utility model is aimed at the conventional semiconductor manufacturing process and equipment can not be applied to CIS chip testing, and provide a kind of simple in structure, versatility good, input cost is low, testing efficiency is high to the probe station of the image sensing performance test of CIS chip.
In order to reach above-mentioned requirements; The technical scheme of the utility model is: but it includes the XY platform that all around moves horizontally; The lifting table that can move up and down is installed on the XY platform, be equipped with on the lifting table supply to place wafer and can do to rotate in a circumferential direction carry brilliant dish, carry brilliant dish above pass through bracing frame; The unsettled probe that is equipped with is characterized in that being provided with the light source that produces light in the lifting table below carrying brilliant dish.
Said light source is arranged on the center of carrying brilliant dish below, and the axis coinciding of the axle center of light source and probe.
Described light source is the light source of led array light source after convex lens Jiao gathers.Described light source is provided with the jacking gear that moves up and down with respect to carrying brilliant dish.
Described light source is for producing the light source of parallel rays.
The chip of above-mentioned imageing sensor to be tested is behind electric performance test; Under the state that not exclusively cuts after the wafer encapsulation is accomplished or do not cut; Make the CIS chip on wafer, keep original arrangement; Whole then wafer is accomplished the test to the image sensing performance on probe station, when guaranteeing bearing accuracy, also can reduce the damage to the CIS chip like this, has also improved the automaticity and the efficient of test greatly.
Description of drawings
Fig. 1 is a plurality of CIS chips are formed wafer together with arrayed a schematic perspective view;
Fig. 2 is the probe station schematic perspective view of test CIS chip;
Fig. 3 is lifting table, the three-dimensional enlarged diagram that carries brilliant dish;
Fig. 4 is the light source scheme of installation of probe station under the broken section state of test CIS chip.
Among the figure: 1, chip; 2, wafer; 3, XY platform; 4, lifting table; 5, carry brilliant dish; 6, bracing frame; 7, probe; 8, light source; 9, jacking gear.
Embodiment
The utility model is explained in detail through embodiment below in conjunction with accompanying drawing.
The chip of imageing sensor to be tested is made up of a plurality of chips 1 and is carried out under wafer 2 state as shown in Figure 1.It is that chip 1 at imageing sensor to be tested is behind electric performance test, still tests under the state with wafer 2 through encapsulation.
The probe station that the utility model designed is like Fig. 2,3, shown in 4; But include the XY platform 3 that all around moves horizontally, the lifting table 4 that can move up and down is installed on XY platform 3, be equipped with on the lifting table 4 and supply to place year brilliant dish 5 that wafer 2 also can be done to rotate in a circumferential direction; Above year brilliant dish 5, be provided with bracing frame 6; Probe 7 is installed on the bracing frame 6, and probe 7 is unsettled with year crystalline substance dish 5, in carrying the brilliant lifting table 4 that coils below 5, is provided with the light source 8 of generation light.
Said light source 8 is arranged on the center of carrying brilliant dish 4 belows, and the axis coinciding of the axle center of light source 8 and probe 7.
The light source 8 that needs according to test can be for like the light source 8 of led array light source after convex lens Jiao gathers, and described light source 8 coils and is provided with the jacking gear 9 that moves up and down with respect to carrying a crystalline substance.Also can be the light source 8 that produces parallel rays.
When said probe station was worked, implementation step was following:
1, will be positioned over by the wafer 2 that multi-disc CIS chip is formed on the brilliant dish 5 of carrying of probe station;
2, Electric Machine Control XY platform 3 is made XY to motion positions, and the wherein a certain CIS chip 1 in the wafer 2 to be measured is positioned under probe 7 testing needles;
3, Electric Machine Control Z makes wafer 2 liftings to lifting table 4, and CIS chip 1 upper surface tin ball is just contacted with probe 7 testing needles;
4, Electric Machine Control jacking gear 9 makes light source 8 liftings, the protruding contact chip 1 lower surface optical surface of light source 8 upper surfaces, and make the slight extruding force of generation between chip 1 upper surface tin ball and probe 7 testing needles, guarantee that the tin ball well contacts with testing needle fully;
5, probe station sends the signal that begins to test to test machine, and test machine is received the beginning test signal, begins CIS chip 1 is tested, and after test was accomplished, test machine returned test result to the group probe station;
6, after probe station is received test result, CIS chip 1 is handled, and kept corresponding data confession later process according to test result;
7, probe station navigates to next CIS chip to be measured 1 position, repeats the 2-5 step, all changes a wafer 2 that needs test again after the test completion up to the CIS chip on the whole wafer 21.
The described probe station of the utility model has solved middle survey probe station and can't test the problem of CIS chip image sensing capabilities, and a kind of JEDEC of being superior to or CHIP pallet dress CIS chip testing machine are provided, and testing efficiency also improves greatly.