CN202189369U - Integrated circuit capable of preventing power consumption attack - Google Patents
Integrated circuit capable of preventing power consumption attack Download PDFInfo
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- CN202189369U CN202189369U CN2011202542548U CN201120254254U CN202189369U CN 202189369 U CN202189369 U CN 202189369U CN 2011202542548 U CN2011202542548 U CN 2011202542548U CN 201120254254 U CN201120254254 U CN 201120254254U CN 202189369 U CN202189369 U CN 202189369U
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
- G06F21/755—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation with measures against power attack
Abstract
The utility model provides an integrated circuit capable of preventing a power consumption attack, which comprises a power supply, a power supply management module, an arithmetic module, a memory unit, a control logic module and an anti-attack module. The anti-attack module comprises a truth random number generator and a scrambling arithmetic module adopting a management operating system (MOs) circuit. A random consumption circuit is provided with a high random degree so that a power consumption curve is covered, and safety and reliability of the whole chip information communication are improved.
Description
Technical field
The utility model relates to the information security circuit field, is specifically related to a kind of integrated circuit of defending power consumption attack.
Background technology
Field of information security technology uses hardware device to encrypt important information usually in modern times.But the power consumption curve of hardware device can be stolen in normal course of operation, and the assailant utilizes the power consumption curve that obtains and uses statistical analysis technique just can infer the key messages such as key that encryption system.Simple power consumption analysis SPA (Simple Power Analysis) and differential power consumption analysis DPA (Differential Power Analysis) are two kinds of attack methods of information security fast and effectively that utilize power consumption attack to realize, it has all caused huge harm to userspersonal information and whole information network security.
At present, the method for defence power consumption attack mainly contains algorithm level protection and two kinds of mechanism of circuit stages protection.The algorithm level protection mechanism mainly is to improve to algorithm, hides intermediate result through in algorithm, introducing the mask that produces at random, makes the signal of chip internal and the power consumption of cryptographic calculation add up uncorrelated, thereby realizes covering the power consumption curve; The circuit stages protection mechanism mainly is to realize covering or upsetting the power consumption curve of cryptographic calculation through the mode of circuit, and main implementation method has customization and the incoherent standard cell lib of power consumption, add at random current drain circuit etc.
Customization is to realize the constant logical block of power consumption through full customization with the basic thought of the incoherent standard cell lib of power consumption, and power consumption is constant when making circuit working, and is uncorrelated with algorithm that is moving and data, thereby has covered the power consumption curve of algorithm operation.The realization of this mode need not to increase extra auxiliary circuit; Only need in the circuit synthesis process, adopt the standard cell lib of customization to get final product; But the full customization of standard cell lib realizes that difficulty is bigger; Customization fully is also need do the correctness that a large amount of checking work could guarantee design except circuit and domain need, and whole in addition area of chip also increases greatly, thus present based on customize and the effect of the incoherent standard cell lib of power consumption unsatisfactory; Though method of current can well realize the scrambling to the power consumption curve and add at random, the randomness of the electric current at random that is added wants enough height could guarantee scrambling effect preferably.
The utility model content
The purpose of the utility model is; Propose a kind of based on the integrated circuit of the defence power consumption attack of current drain circuit at random; The mode that said integrated circuit adopts real random number generator and scrambling algorithm process to combine makes and consumes circuit at random and have high degree of randomness; Thereby realized preferably the covering of power consumption curve promoted the security and the reliability of chip information communication.
For realizing above-mentioned purpose; The utility model provides a kind of integrated circuit of defending power consumption attack; The integrated circuit of said defence power consumption attack comprises: power supply, power management module, algoritic module, storage unit and steering logic unit; Its improvements are, this integrated circuit also comprises and is used to receive the power supply signal VCC1/VSS1 of said power management module output and the attack protection module of the instruction that said steering logic unit sends; The steering logic unit is connected with algoritic module, storage unit and attack protection module respectively; Said power management module receive signal that said power supply sends and after internal conversion out-put supply signal VCC1/VSS1, said power supply signal VCC1/VSS1 is said algoritic module, said storage unit, said steering logic unit and said attack protection module for power supply as internal power supply domain; Said steering logic unit also sends instruction to said algoritic module, and receives the signal from said algoritic module; Said algoritic module in operational process from said storage unit reading of data, and result data and intermediate data write in the said storage unit; Said steering logic unit writes or reads data required in the said storage unit in said storage unit when executing instruction operations.
In the optimal technical scheme that the utility model provides, said power management module and said storage unit are to isolate separately; Putting together in said algoritic module and said steering logic unit, but keeps apart with other modules; Said attack protection module and other circuit are isolated.
In second optimal technical scheme that the utility model provides, said attack protection module comprises oscillator on biasing circuit, the sheet, real random number generator, scrambling algoritic module, voltage-to-current modular converter and current source array; Said biasing circuit is connected with said real random number generator with said voltage-to-current converting unit, said last oscillator; Said current source array is connected with said scrambling algoritic module, current source array; Go up oscillator for said and be connected with said real random number generator, scrambling algoritic module, said real random number generator is connected with said scrambling algoritic module.
In the 3rd optimal technical scheme that the utility model provides, said biasing circuit is that said voltage-to-current converting unit, said last oscillator and said real random number generator provide bias voltage; The said output square-wave signal of going up oscillator is that said real random number generator and said scrambling algoritic module provide synchronous clock; Said real random number generator is output as N road control signal Xctrl [N:1], as the input of said scrambling algoritic module, obtains N road output Yctrl [N:1] after the said N road control signal process scrambling algorithm process; The voltage signal that said voltage-to-current converting unit provides said biasing circuit converts the current offset signal into, as the current reference source of said current source array; Said current source array inside comprises the unequal current source of N road current value, and each road current source is separately by way switch control, and the switch of the N road current source of said current source array is controlled on N road signal Yctrl [N:1] of said scrambling algoritic module output respectively.
In the 4th optimal technical scheme that the utility model provides, said biasing circuit comprises band gap reference and bleeder circuit, wherein, after the stable DC voltage that is produced by said band gap reference is handled through said bleeder circuit, produces reference voltage level Vref.
In the 5th optimal technical scheme that the utility model provides, said scrambling algoritic module adopts the MOS circuit.
With the prior art ratio, the beneficial effect of the utility model is in the integrated circuit of defence power consumption attack, to add the attack protection module and realized the function of shielding of algorithm power consumption curve has been improved security feature; Adopt real random number generator as the control signal that changes power consumption, improved the degree of randomness that consumes power consumption, realized reliable shielding the power consumption curve; In the attack protection module, added the scrambling algoritic module and realized scrambling process, further improved reliability the shielding of power consumption curve to random series; And the laying out pattern of the integrated circuit of defence power consumption attack is reasonable, and crosstalking of intermodule signal reduced, and has guaranteed the integrality of signal and the reliability of function.
Description of drawings
Fig. 1 is the synoptic diagram of the integrated circuit of defence power consumption attack.
Fig. 2 is the block architecture diagram of attack protection module.
Fig. 3 is the structured flowchart of biasing circuit.
Fig. 4 is the structured flowchart of scrambling algoritic module.
Fig. 5 is the layout domain of the integrated circuit of defence power consumption attack.
Embodiment
The integrated circuit of the defence power consumption attack of the utility model is shown in accompanying drawing 1, and the integrated circuit 1 of defence power consumption attack is made up of power management module 2, algoritic module 3, storage unit 4, steering logic unit 5 and attack protection module 6.
Power supply VCC/VSS is the integrated circuit 1 of defence power consumption attack and the power supply of power management module 2, through exporting power supply signal VCC1/VSS1 stable and that have certain driving force after power management module 2 internal conversion.Wherein, VCC1/VSS1 is algoritic module 3, storage unit 4, steering logic unit 5 and 6 power supplies of attack protection module in the system as internal power supply domain.Steering logic unit 5 is responsible for sending instruction to algoritic module 3 and attack protection module 6, and receives the signal from algoritic module 3.Algoritic module 3 in operational process from storage unit 4 reading of data, and will export result data and intermediate data is written in the storage unit 4; Steering logic unit 5 writes data in storage unit 4 when executing instruction operations, from storage unit 4, read required data simultaneously.
Because the power domain VCC1/VSS1 of algoritic module comes from power management module 2, the power domain of power management module 2 comes from system power supply territory VCC/VSS, and the power consumption calibration curve information of algoritic module 3 just has been reflected on the VCC/VSS of system power supply territory like this.And the system power supply territory can from external monitoring to, the technology of the power consumption attack through the outside just can steal the key messages such as key of system like this.In the integrated circuit 1 of defence power consumption attack, add attack protection module 6, attack protection module 6 and algoritic module 3 shared power domain can realize the protection to algoritic module 3 operational processs through the power consumption shield technology of attack protection module 6 simultaneously.
The block architecture diagram of attack protection module 6 is shown in accompanying drawing 2.Main modular comprises oscillator 8 on biasing circuit 7, the sheet, real random number generator 9, scrambling algoritic module 10, voltage-to-current modular converter 11 and current source array 12.The power domain of attack protection module 6 is VCC1/VSS1, comes from power management module 2.
In attack protection module 6, biasing circuit 7 provides stable bias voltage for oscillator 8 and real random number generator 9 on voltage-to-current converting unit 11, the sheet; Oscillator 8 is oscillating units that integrated circuit is realized on the sheet on the sheet, and its output frequency characteristic is relevant with its input offset voltage, and the output square-wave signal of oscillator 8 is that real random number generator 9 provides synchronous clock with scrambling algoritic module 10 on the sheet; Real random number generator 9 is based on the real random number generator with high degree of randomness that the resistance noise characteristic realizes; The degree of randomness of its output sequence is relevant with the statistical property that resistance noise is had; Real random number generator 9 is output as N road control signal Xctrl [N:1]; As the input of scrambling algoritic module 10, obtain N road output Yctrl [N:1] after this N road control signal process scrambling algorithm process; The effect of voltage-to-current converting unit 11 is to convert the stable voltage signal that biasing circuit 7 provides into stable current offset signal, as the current reference source of current source array 12; Current source array 12 inside comprise the unequal current source of N road current value, and each road current source is separately by way switch control, and the N road signal Yctrl [N:1] of scrambling algoritic module 10 outputs is the switch of the N road current source of Control current source array 12 respectively.Like this, as the control signal of current source array, power consumed also can demonstrate random character on the power supply, thereby has realized the function of shielding to the power consumption curve after the random number sequence process scrambling algorithm process that real random number generator generates.
Accompanying drawing 4 is structured flowcharts of scrambling algoritic module 10.Scrambling algoritic module 10 mainly is made up of out of order module 15, XOR module 16 and out of order module 17.The N road control signal Xctrl [N:1] that is generated by real random number generator 9 has realized the logic of each control signal out of order through out of order module 15; Do XOR through XOR module 16 again and handle, realize logic scrambling out of order module 15 output signals; Through the out of order processing of the logic of out of order module 16 back output N road control signal Yctrl [N:1], be used for the current supply switch of Control current source array 12 at last.Through above signal processing, scrambling algoritic module 10 has been realized the scrambling to real random number generator 9 formation sequences.
For guaranteeing the function and the characteristic of total system,, design need carry out rational deployment when realizing to the domain of each module.Accompanying drawing 5 is layout domains of the integrated circuit 1 of defence power consumption attack, and bold box is wherein represented protection ring, is used to isolate crosstalking on the domain.As shown in Figure 5, power management 2 is to isolate separately with storage unit 4; Algoritic module 3 in the digital circuit is put together with steering logic unit 5 and other modules are kept apart; Attack protection module 6 is isolated with other circuit, and inside is divided into following 4 parts again: biasing circuit 7, voltage-to-current converting unit 11 and current source array; Oscillator 8 on the sheet; Real random number generator 9; Scrambling algoritic module 10.
What need statement is that the utility model content and embodiment are intended to prove the practical application of technical scheme that the utility model provides, and should not be construed as the qualification to the utility model protection domain.Those skilled in the art can do various modifications, be equal to replacement or improvement under the spirit and principle inspiration of the utility model.But these changes or modification are all in the protection domain that application is awaited the reply.
Claims (6)
1. integrated circuit of defending power consumption attack; The integrated circuit of said defence power consumption attack comprises: power supply (1), power management module (2), algoritic module (3), storage unit (4) and steering logic unit (5); It is characterized in that this integrated circuit also comprises the attack protection module (6) of the instruction that the power supply signal VCC1/VSS1 that is used to receive said power management module (2) output and said steering logic unit (5) send; Steering logic unit (5) is connected with algoritic module (3), storage unit (4) and attack protection module (6) respectively;
Said power management module (2) receive signal that said power supply (1) sends and after internal conversion out-put supply signal VCC1/VSS1, said power supply signal VCC1/VSS1 is said algoritic module (3), said storage unit (4), said steering logic unit (5) and said attack protection module (6) power supply as internal power supply domain;
Said steering logic unit (5) also sends instruction to said algoritic module (3), and receives the signal from said algoritic module (3); Said algoritic module (3) in operational process from said storage unit (4) reading of data, and result data and intermediate data write in the said storage unit (4); Said steering logic unit (5) writes or reads required data in the said storage unit (4) in said storage unit (4) when executing instruction operations.
2. the integrated circuit of defence power consumption attack as claimed in claim 1 is characterized in that, said power management module (2) and said storage unit (4) are to isolate separately; Putting together in said algoritic module (3) and said steering logic unit (5), but keeps apart with other modules; Said attack protection module (6) is isolated with other circuit.
3. the integrated circuit of defence power consumption attack as claimed in claim 1; It is characterized in that; Said attack protection module (6) comprises oscillator (8) on biasing circuit (7), the sheet, real random number generator (9), scrambling algoritic module (10), voltage-to-current modular converter (11) and current source array (12); Said biasing circuit (7) is connected with said real random number generator (9) with said voltage-to-current converting unit (11), said last oscillator (8); Said current source array (12) is connected with said scrambling algoritic module (10), current source array (12); Go up oscillator (8) for said and be connected with said real random number generator (9), scrambling algoritic module (10), said real random number generator (9) is connected with said scrambling algoritic module (10).
4. the integrated circuit of defence power consumption attack as claimed in claim 3 is characterized in that, said biasing circuit (7) is that said voltage-to-current converting unit (11), said go up oscillator (8) and said real random number generator (9) provides bias voltage;
The said output square-wave signal of going up oscillator (8) is that said real random number generator (9) and said scrambling algoritic module (10) provide synchronous clock;
Said real random number generator (9) is output as N road control signal Xctrl [N:1], as the input of said scrambling algoritic module (10), obtains N road output Yctrl [N:1] after the said N road control signal process scrambling algorithm process;
Said voltage-to-current converting unit (11) converts the voltage signal that said biasing circuit (7) provides into the current offset signal, as the current reference source of said current source array (12);
Said current source array (12) inside comprises the unequal current source of N road current value; Each road current source is separately by way switch control, and the switch of the N road current source of said current source array (12) is controlled on N road signal Yctrl [N:1] of said scrambling algoritic module (10) output respectively.
5. the integrated circuit of defence power consumption attack as claimed in claim 3; It is characterized in that; Said biasing circuit comprises band gap reference (13) and bleeder circuit (14); Wherein, after the stable DC voltage that is produced by said band gap reference (13) is handled through said bleeder circuit (14), produce reference voltage level Vref.
6. the integrated circuit of defence power consumption attack as claimed in claim 3 is characterized in that, said scrambling algoritic module adopts the MOS circuit.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011202542548U CN202189369U (en) | 2011-07-18 | 2011-07-18 | Integrated circuit capable of preventing power consumption attack |
| PCT/CN2011/083060 WO2013010362A1 (en) | 2011-07-18 | 2011-11-28 | Integrated circuit and method for defending against power attack |
| BR112014001209A BR112014001209A2 (en) | 2011-07-18 | 2011-11-28 | an integrated circuit and its method against power loss attack |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011202542548U CN202189369U (en) | 2011-07-18 | 2011-07-18 | Integrated circuit capable of preventing power consumption attack |
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| CN202189369U true CN202189369U (en) | 2012-04-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2011202542548U Expired - Lifetime CN202189369U (en) | 2011-07-18 | 2011-07-18 | Integrated circuit capable of preventing power consumption attack |
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|---|---|
| CN (1) | CN202189369U (en) |
| BR (1) | BR112014001209A2 (en) |
| WO (1) | WO2013010362A1 (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102735985A (en) * | 2012-06-12 | 2012-10-17 | 福建睿矽微电子科技有限公司 | Random current type anti-detection device and anti-detection method |
| CN103023636A (en) * | 2012-11-15 | 2013-04-03 | 北京昆腾微电子有限公司 | Voltage stabilizer capable of resisting power consumption analysis attack for code chip as well as code chip |
| CN104283673A (en) * | 2014-10-09 | 2015-01-14 | 东南大学 | Random and dynamic voltage regulation anti-attack method for password circuit system and circuit system |
| CN106503590A (en) * | 2016-10-17 | 2017-03-15 | 杭州国芯科技股份有限公司 | A kind of anti-power consumption attack circuit of chip and the method for preventing power consumption attack |
| CN107040364A (en) * | 2017-03-29 | 2017-08-11 | 北京华大信安科技有限公司 | It is a kind of to prevent the circuit of power consumption attack |
| CN108205349A (en) * | 2016-12-19 | 2018-06-26 | 北京兆易创新科技股份有限公司 | A kind of band-gap reference circuit |
| CN109617668A (en) * | 2018-12-14 | 2019-04-12 | 四川长虹电器股份有限公司 | A method of preventing bypass attack |
| CN112149065A (en) * | 2020-09-16 | 2020-12-29 | 北京中电华大电子设计有限责任公司 | Software defense fault injection method |
| WO2021046978A1 (en) * | 2019-09-12 | 2021-03-18 | 华中科技大学 | Gaussian sampling circuit resistant to simple power consumption analysis attacks |
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| CN110908634B (en) * | 2019-11-13 | 2023-07-07 | 北京中电华大电子设计有限责任公司 | Random sequence generating device and control method thereof |
| CN112035854B (en) * | 2020-08-13 | 2024-02-23 | 南京低功耗芯片技术研究院有限公司 | Method for resisting power consumption attack based on cyclic shift of bit permutation and fixed permutation table |
| CN112699420A (en) * | 2020-12-31 | 2021-04-23 | 广州万协通信息技术有限公司 | Active shielding protection device and method for security chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| DE10162309A1 (en) * | 2001-12-19 | 2003-07-03 | Philips Intellectual Property | Method and arrangement for increasing the security of circuits against unauthorized access |
| CN1485857A (en) * | 2002-09-27 | 2004-03-31 | 北京华虹集成电路设计有限责任公司 | Prevention method of encrypted integrated circuit against electrical source attack |
| CN101025771B (en) * | 2006-02-17 | 2010-05-12 | 联想(北京)有限公司 | Security chip |
| JP2010062635A (en) * | 2008-09-01 | 2010-03-18 | Sony Corp | Encryption processing apparatus and integrated circuit |
| CN101695021A (en) * | 2009-10-22 | 2010-04-14 | 杭州晟元芯片技术有限公司 | System and method for resisting SPA/DPA attack |
-
2011
- 2011-07-18 CN CN2011202542548U patent/CN202189369U/en not_active Expired - Lifetime
- 2011-11-28 WO PCT/CN2011/083060 patent/WO2013010362A1/en active Application Filing
- 2011-11-28 BR BR112014001209A patent/BR112014001209A2/en not_active IP Right Cessation
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102735985A (en) * | 2012-06-12 | 2012-10-17 | 福建睿矽微电子科技有限公司 | Random current type anti-detection device and anti-detection method |
| CN102735985B (en) * | 2012-06-12 | 2016-05-25 | 福建睿矽微电子科技有限公司 | The anti-sniffer of random current type and anti-detection method |
| CN103023636A (en) * | 2012-11-15 | 2013-04-03 | 北京昆腾微电子有限公司 | Voltage stabilizer capable of resisting power consumption analysis attack for code chip as well as code chip |
| CN104283673A (en) * | 2014-10-09 | 2015-01-14 | 东南大学 | Random and dynamic voltage regulation anti-attack method for password circuit system and circuit system |
| CN106503590A (en) * | 2016-10-17 | 2017-03-15 | 杭州国芯科技股份有限公司 | A kind of anti-power consumption attack circuit of chip and the method for preventing power consumption attack |
| CN106503590B (en) * | 2016-10-17 | 2019-02-01 | 杭州国芯科技股份有限公司 | A kind of method chip anti-power consumption attack circuit and prevent power consumption attack |
| CN108205349A (en) * | 2016-12-19 | 2018-06-26 | 北京兆易创新科技股份有限公司 | A kind of band-gap reference circuit |
| CN107040364A (en) * | 2017-03-29 | 2017-08-11 | 北京华大信安科技有限公司 | It is a kind of to prevent the circuit of power consumption attack |
| CN107040364B (en) * | 2017-03-29 | 2020-05-08 | 北京华大信安科技有限公司 | Circuit for preventing power consumption attack |
| CN109617668A (en) * | 2018-12-14 | 2019-04-12 | 四川长虹电器股份有限公司 | A method of preventing bypass attack |
| WO2021046978A1 (en) * | 2019-09-12 | 2021-03-18 | 华中科技大学 | Gaussian sampling circuit resistant to simple power consumption analysis attacks |
| CN112149065A (en) * | 2020-09-16 | 2020-12-29 | 北京中电华大电子设计有限责任公司 | Software defense fault injection method |
Also Published As
| Publication number | Publication date |
|---|---|
| BR112014001209A2 (en) | 2017-06-13 |
| WO2013010362A1 (en) | 2013-01-24 |
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