CN202171819U

CN202171819U - Chip used for identifying article to realize anti-counterfeit tracking

Info

Publication number: CN202171819U
Application number: CN2011201901986U
Authority: CN
Inventors: 林加缪; 徐良雨; 周华
Original assignee: 徐良雨; 林加缪; 周华
Current assignee: HANGZHOU BOLIAN ZHIXIN TECHNOLOGY CO., LTD.
Priority date: 2011-05-27
Filing date: 2011-05-27
Publication date: 2012-03-21
Anticipated expiration: 2021-05-27

Abstract

The utility model relates to a chip used for identifying articles to realize anti-counterfeit tracking, belonging to the technical field of anti-counterfeit tracking. The chip comprises a microprocessor, a general interface module and an internal memory, wherein the general interface module is connected with the microprocessor, the microprocessor is connected with the internal memory; the general interface module receives verification request information sent by a handset and sends the information to the microprocessor, and receives anti-counterfeit information sent by the microprocessor and sends the anti-counterfeit information to the handset; the microprocessor receives the verification request information from the general interface module, reads the anti-counterfeit information from the internal memory, and sends the anti-counterfeit information to the general interface module; and the internal memory stores the anti-counterfeit information. The chip solves the problems that the current anti-counterfeit tracking technology is not convenient for a user to use and is high in cost. The chip is unique, confidential, high in tracking performance, good in anti pollution capability, convenient for the user to use, etc.

Description

Be used for identify objects to realize the chip of false proof tracking

Technical field

The utility model belongs to false proof tracer technique field, relates in particular to a kind of identify objects that is used for to realize the chip of false proof tracking.

Background technology

Anti-counterfeiting technology is meant the measure of taking in order to reach false proof purpose, and it is accurately to discern the false from the genuine within the specific limits, and is difficult for by technology imitated and that duplicate.Briefly be exactly to prevent to copy counterfeit technology.

Existing false proof tracing product roughly can be divided into four types from technical characterictic and function evolution angular divisions: laser anti-counterfeit, digital code anti-false, the false proof tracking of bar code, RFID discern false proof tracer technique.For laser antifalsification technology, because the user do not recognize the ability that label is true and false, and label also is easy to forge, but therefore under the situation that lacks comparative, 60% counterfeit and 100% genuine piece are difficult to affirmation; Next is that temperature becomes label, also is easy to forge though the user is easy to identification; The query formulation numerical code anti-fake label, the user can pass through the true and false of phone, note, internet checking digital label.But because the false proof essence of this type all is to need the user from line operate, comparatively loaded down with trivial details on the program, therefore some users that are unfamiliar with note and online may abandon.

The two-dimensional bar technology is the increasing anti-counterfeiting technology of using in recent years, but because two-dimensional bar itself does not possess too many information and value, and its value has only through networking and carries out after data query checks, and it is meaningful just to seem.Existing two-dimensional bar code anti-counterfeiting technology rests on easy single cognitive phase mostly, does not possess the online query function.Help Center's server also majority rests on the self-built stage of company, does not possess large-scale networked query capability.

RFID is a kind of new life's a false proof tracer technique, in logistics management, is widely used.But existing rfid system need adopt special-purpose read-write equipment and cost an arm and a leg, and is unwell to the terminal client buying.

The utility model content

In order to solve problems such as inconvenient user's use of when article being realized false proof the tracking, being run into, cost height; The utility model provides a kind of identify objects that is used for to realize the chip of false proof tracking; Said chip comprises microprocessor, common interface module and internal storage; Said common interface module is connected with said microprocessor, and said microprocessor is connected with said internal storage, and wherein: said common interface module receives the checking solicited message that mobile phone sends; Should verify that solicited message transferred to microprocessor processes, and receive anti-counterfeiting information that microprocessor sends and send this anti-counterfeiting information to mobile phone; Said microprocessor receives the checking solicited message that comes from said common interface module, based on this checking solicited message, from said internal storage, reads said anti-counterfeiting information, and said anti-counterfeiting information is sent to common interface module; Said internal storage is stored said anti-counterfeiting information.

The chip that the utility model proposes, wherein, said common interface module supports the GSM signal to communicate with mobile phone, said internal storage can be disposable programmable read only memory (OTP ROM).

The chip that the utility model proposes, wherein, said microprocessor also receives the initialization anti-counterfeiting information that comes from the special chip read write line, and in said internal storage, writes anti-counterfeiting information.

The chip that the utility model proposes, wherein, the input port of said common interface module is a port one 04, port one 05 and port one 09; Output port is a port one 06, port one 07 and port one 08; Port one 04 is set up communication with outside port one 01 and is connected, and is used for transmission checking solicited message A1 [7:0], and port one 05 is set up communication with outside port one 02 and is connected, and is used for receive clock 1; Port one 06 is set up communication with outside port one 03 and is connected, and is used for sending outside anti-counterfeiting information B1 [7:0] to the outside; Port one 07 links to each other with the port one 10 of microprocessor, is used to transmit the checking solicited message A [7:0] of input; Port one 08 links to each other with the port one 11 of microprocessor, is used for clock 1 is sent into microprocessor; Port one 09 links to each other with 112 ports of microprocessor, is used to receive the output anti-counterfeiting information B [7:0] that microprocessor sends.

The chip that the utility model proposes, wherein, ports having 116 of said disposable programmable read only memory input port and port one 17; Output port is a port one 18; Input port 116 links to each other with the port one 13 of microprocessor; The anti-counterfeiting information J [7:0] that writes is write in the disposable programmable read only memory; The zone to be written of disposable programmable read only memory can only be written into primary information under the control of microprocessor, information can not be modified thereafter; If will append information, then under the control of microprocessor, the information of appending is write other zones to be written of disposable programmable read only memory; Zone to be written then can't be revised once the information of being written into; The area size to be written of disposable programmable read only memory is by the memory capacity decision of disposable programmable read only memory; Input port 117 links to each other with the port one 14 of microprocessor, is used for address Addr [10:0] is sent into the address end of disposable programmable read only memory; Output port 118 links to each other with the port one 15 of microprocessor, is used for the anti-counterfeiting information L [7:0] of address Addr [10:0] appointment is sent into microprocessor.

The chip that the utility model proposes, wherein, the input port of microprocessor is a port one 10, port one 11, port one 15, port one 22, port one 23 and port one 24; The input port of microprocessor is a port one 12, port one 13 and port one 14; Input port 122 links to each other with the port one 19 of the special chip read write line of outside, is used to receive initialization Authority Verification information D; The port one 20 of port one 23 and special chip read write line links to each other, and is used for receive clock 2; The port one 21 of port one 24 and special chip read write line links to each other, and is used to receive initialization anti-counterfeiting information E.

The chip that the utility model proposes, wherein, the communication mode of said initialization anti-counterfeiting information E is a serial communication, communication protocol meets I ²The C bus protocol; Line between port one 21 and the port one 24 is as I ²The data line SDA of C bus; Line between port one 20 and the port one 23 is I ²The clock SCL of C bus; The communication mode of initialization Authority Verification information D is a serial communication, and communication protocol meets I ²The C bus protocol; Line between port one 19 and the port one 22 is as I ²The data line SDA of C bus; Line between port one 20 and the port one 23 is I ²The clock SCL of C bus; The content of initialization Authority Verification information D is 512 Authority Verification sign indicating numbers, 512 Authority Verification check codes, and 512 authorization codes are authorized check code for 512.

The chip that the utility model proposes, wherein, said 512 its verification modes of Authority Verification check code are 512 Authority Verification sign indicating numbers to be divided into 8 groups 64 message block, are respectively D0 [63:0]; D1 [63:0], D2 [63:0], D3 [63:0], D4 [63:0]; D5 [63:0], D6 [63:0], D7 [63:0]; With D0 [63:0] is example, and 64 message block D0 [63:0] adopt CRC-32 to generate 32 Cyclic Redundancy Code C0 [31:0], and generator polynomial brief note formula is 04C11DB7 or other feasible generator polynomials; Message block D0 [0:63] is adopting CRC-32 to generate 32 Cyclic Redundancy Code C0 [63:32], and generator polynomial brief note formula is 1EDC6F41 or other feasible generator polynomials, and the check code of forming at last is { C0 [63:0]; C1 [63:0], C2 [63:0], C3 [63:0]; C4 [63:0]; C5 [63:0], C6 [63:0], C7 [63:0] } be 512 Authority Verification check codes.

The chip that the utility model proposes, wherein, said 512 its verification modes of mandate check code are 512 authorization codes to be divided into 8 groups 64 message block, are respectively D10 [63:0]; D11 [63:0], D12 [63:0], D13 [63:0], D14 [63:0]; D15 [63:0], D16 [63:0], D17 [63:0]; With D10 [63:0] is example, and 64 message block D10 [63:0] adopt CRC-32 to generate 32 Cyclic Redundancy Code C10 [31:0], and generator polynomial brief note formula is 04C11DB7 or other feasible generator polynomials; Message block D10 [0:63] is adopting CRC-32 to generate 32 Cyclic Redundancy Code C10 [63:32], and generator polynomial brief note formula is 1EDC6F41 or other feasible generator polynomials, and the check code of forming at last is { C10 [63:0]; C11 [63:0], C12 [63:0], C13 [63:0]; C14 [63:0]; C15 [63:0], C16 [63:0], C17 [63:0] } be 512 mandate check codes.

The chip that the utility model proposes, wherein, microprocessor comprises that serial communication controller 1, serial communication controller 2, the temporary module of information input, intrusion detection module, information are read in module, information is write out module and message output module.

The chip that the utility model proposes, wherein, serial communication controller 1 meets I with serial communication controller 2 ²The C bus communication protocol; The input port of serial communication controller 1 is a port 230, port 231; Serial communication controller 1 output port is a port 228, port 229; Port 230 links to each other with the port one 22 of microprocessor, is used to receive initialization authority information D; Port 231 links to each other with microprocessor port one 23, is used for receive clock 2; Port 229 links to each other with the port 220 of invading detection module, is used for sending permission authorization information D1 to the port of invading detection module 220; Port 228 links to each other with the port 221 of invading detection module, and port 228 is direct-connected with port 231, so port 228 is sent to clock 2 port 221 of invading detection module; The input port of serial communication controller 2 is a port 234, port 235; Serial communication controller 2 output ports are port 232, port 233; Port 235 links to each other with the port one 24 of microprocessor, is used to receive initialization anti-counterfeiting information E; Port 234 links to each other with microprocessor port one 23, is used for receive clock 2; Port 232 links to each other with the port 207 of the temporary module of information input, is used to send the port 207 of anti-counterfeiting information E1 to the temporary module of information input; Port 233 links to each other with the port 206 of the temporary module of information input, and port 233 is direct-connected with port 234, so port 233 is sent to clock 2 port 206 of the temporary module of information input.

The chip that the utility model proposes, wherein, the input port of the temporary module of information input is a port 201, port 202, port 204, port 206; The output port of the temporary module of information input is a port 203, port 205; Port 201 is one eight a bit parallel port, links to each other with eight buses of the port one 10 of microprocessor are corresponding one by one, is used to receive the checking solicited message A [7:0] of input; Port 202 links to each other with the port one 11 of microprocessor, is used for receive clock 1; Port 204 links to each other with the port 212 of invading detection module, is used to receive signal mode control; Port 203 links to each other with two ports 213 of invading detection module, is used for the output system clock; Port 205 links to each other with the port 211 of invading detection module, is used to send input information F to invading detection module; The temporary module of information input is 1 by a width, and the degree of depth is 512 push-up storage, 1 MUX, and 1 parallel-serial converter, one and string signal maker, a system clock maker constitutes; The input end of system clock maker is the clock 1 of port 202 inputs, the clock 2 of port 206 inputs, and the pattern control of port 204 inputs is output as the system clock that port 203 is exported; When the pattern of port 204 inputs is controlled to be high level; The clock 1 of port 202 inputs is from port 203 outputs and as system clock; When the pattern of port 204 inputs was controlled to be low level, the clock 2 of port 206 inputs was from port 203 outputs and as system clock; And the string signal maker is made up of one two input and door and mould 9 counters 1; With the input end of door be the clock 1 of port 202 inputs and two signals of pattern control of port 204 inputs, with the output terminal of door clock trigger end as mould 9 counters 1; Mould 9 counters 1 count value be 9 o'clock output signal also-the string switching signal is a high level, during its remainder values also-the string switching signal is a low level; Parallel-serial converter is when the system clock rising edge of port 203 output, and also-when the string switching signal is high level, be written into the parallel data fake certification information A [7:0] of port 201 inputs, otherwise an input end of SOD serial output data to multichannel selector switch; When MUX is controlled to be high level in the pattern of port 204 inputs; The output terminal of output valve to the push-up storage of output parallel-serial converter; When the pattern of port 204 inputs was controlled to be low level, output anti-counterfeiting information E1 was to the output terminal of push-up storage; Push-up storage is made up of 512 d type flip flops, and the data input pin and the data output end of 512 triggers join end to end, and data output end is the input information F of port 205 outputs.

The chip that the utility model proposes, wherein, the input port that information is read in module is 224,223; The output port that information is read in module is 222; Port 224 links to each other with the port one 15 of microprocessor, is used to receive the anti-counterfeiting information L [7:0] of disposable programmable read only memory output; Port 223 links to each other with the port 215 of invading detection module, is used for the receiving system clock; Port 222 links to each other with the port 216 of invading detection module, is used to export anti-counterfeiting information H to invading detection module; It is 8 by a width that information is read in module, the degree of depth be 1 also-string transition trigger device group and mould 9 counters 2 formations; Mould 9 counters 2 the system clock rising edge of port 223 input trigger down counting and output signal also-go here and there switching signal 1; Count value be 9 o'clock also-string switching signal 1 is high level, during its remainder values also-string switching signal 1 is a low level; Parallel-serial converter is when the system clock rising edge of port 223 inputs; And also-when string switching signal 1 is high level; Be written into the anti-counterfeiting information L [7:0] of parallel data port 224 inputs, otherwise SOD serial output data to port 222 is invaded detection module as anti-counterfeiting information H output valve.

The chip that the utility model proposes, wherein, the input port that information is write out module is a port 225, port 226; The output port that information is write out module is a port one 13; Port 225 links to each other with the port 219 of invading detection module, is used to receive the anti-counterfeiting information I that writes; Port 226 links to each other with the port 218 of invading detection module, is used for the receiving system clock; Port 227 links to each other with the port one 13 of microprocessor, is used to export the anti-counterfeiting information J [7:0] that writes; It is 8 by a width that information is write out module, the degree of depth be 1 string-and transition trigger device group constitute; This string-and the input end of transition trigger device be the anti-counterfeiting information I that writes of port 225 inputs, trigger down at the system clock rising edge of port 226 inputs, export the anti-counterfeiting information J [7:0] that parallel datas write through port 227.

The chip that the utility model proposes, wherein, the input port of message output module is 209,236; The output port of message output module is 208; Port 209 links to each other with the port 214 of invading detection module, is used to receive anti-counterfeiting information G to be exported; Port 208 links to each other with the port one 12 of microprocessor, is used for sending output anti-counterfeiting information B [7:0]; Port 236 links to each other with the port 203 of the temporary module of information input, is used for the receiving system clock; Message output module is 8 by a width, the degree of depth be 1 string-and transition trigger device group constitute; This string-and the input end of transition trigger device be the anti-counterfeiting information G to be exported that port 209 receives, trigger down the output anti-counterfeiting information B [7:0] that walks abreast through port 208 outputs at the system clock rising edge of port 236 inputs.

The chip that the utility model proposes, wherein, the input port of invading detection module is a port 211, port 213, port 216, port 220, port 221; The output port of invading detection module is a port 212, port 214, port 215, port 217, port 218, port 219; Input port 213 and output port 215, port 218 is direct-connected, and port 215, port 218 are used for direct output system clock; Input port 216 links to each other with output port 214, is used for anti-counterfeiting information H directly is sent to the input port 209 of message output module; The output port 114 of port 217 and microprocessor links to each other, and is used for to disposable programmable read only memory OPADD Addr [10:0]; Invade detection module and form mode control signal maker, address generation module, anti-counterfeiting information programming module by following module.

The chip that the utility model proposes, wherein, the mode control signal maker is by three d type flip flops, and the rejection gate of one three input one output is formed; Joining end to end of three d type flip flops, input end are the Authority Verification information D 1 of port 220 inputs; The clock end of three d type flip flops all links to each other with clock 2; The output terminal of three a d type flip flops input end of AND respectively links to each other; The output terminal of rejection gate is the pattern control of port 212 outputs.

The chip that the utility model proposes, wherein, the address generation module is formed with door and address generator by one; Address generator is counting under the rising edge with door output triggers, and count value is exported through port 217 as 11 address Addr [10:0].

The chip that the utility model proposes, wherein, anti-counterfeiting information programming module is 1 by two width, the degree of depth is 512 push-up storage, XOR gate, two and door, mould 1024 frequency dividers, a d type flip flop, a CRC maker is formed; Push-up storage 1 is made up of 512 d type flip flops; The data input pin and the data output end of 512 triggers join end to end; Push-up storage 1 data output end is the Authority Verification information D 1 of port 220 inputs, and input end of data output end and XOR gate links to each other; The clock end of push-up storage 1 is the system clock of port 213 inputs; Push-up storage 2 is made up of 512 d type flip flops, and the data input pin and the data output end of 512 triggers join end to end, and push-up storage 2 data output ends are the check code of CRC maker output, and input end of output terminal and XOR gate links to each other; The clock end of push-up storage 2 is the system clock of port 213 inputs; Mould 1024 frequency dividers carry out frequency division to the system clock of port 213 input, and divide ratio is 1024, output terminal with link to each other with an input end of door 1; Mould 1024 frequency dividers carry out frequency division to the system clock of port 213 inputs; The output terminal of XOR gate with link to each other with another output terminal of door 1; Link to each other with the clock end of d type flip flop with the output terminal of door 1; The data terminal of d type flip flop links to each other with power supply, and the oppisite phase data end of d type flip flop links to each other with the data input pin with door 2; The input information F of port 211 inputs links to each other with another data input pin of door 2; Be the anti-counterfeiting information I that writes and pass through port 219 outputs with the data output end of door 2.

The chip that the utility model proposes, wherein, microprocessor has the writing information pattern, and two mode of operations of information contrastive pattern are by the mode of operation of invading the control module control microprocessor.

The chip that the utility model proposes, wherein, special-purpose chip read write line is down synchronous clock 2, through port one 24 initialization anti-counterfeiting information E is write in the serial communication controller 2, and serial communication controller 2 is according to I ²The C bus protocol reverts to anti-counterfeiting information E1 with initialization anti-counterfeiting information E, and anti-counterfeiting information E1 is sent into the information temporary storage module; Special-purpose chip read write line is down synchronous clock 2, through port one 22 initialization Authority Verification information D is write in the serial communication controller 1, and serial communication controller 1 is according to I ²The C bus protocol reverts to serial data Authority Verification information D 1 with initialization Authority Verification information D, and Authority Verification information D 1 is sent into the intrusion detection module; The intrusion detection module is sent the anti-counterfeiting information I that writes into information and is write out module when detecting Authority Verification information D 1 for after the legal information; Information is write out module and under the triggering of system clock, the anti-counterfeiting information J [7:0] that writes is write disposable programmable read only memory; Disposable programmable read only memory writes assigned address with the anti-counterfeiting information J [7:0] that writes under the control of address Addr [10:0].

The chip that the utility model proposes, wherein, mobile phone through common interface module clock 1 synchronously down, the fake certification information A [7:0] of input is sent into the temporary module of information input; Trigger down with the rising edge of signal at system clock and input information F, intrusion detection module calculated address Addr [10:0] sends into disposable programmable read only memory; Information is read in the anti-counterfeiting information L [7:0] that module is read in disposable programmable read only memory output; The anti-counterfeiting information H that the intrusion detection module reads in information in the module directly sends into message output module as anti-counterfeiting information G to be exported; Last under the triggering of clock, message output module will be exported anti-counterfeiting information B [7:0] and send to mobile phone through common interface module.

The chip that the utility model proposes; Wherein, Said chip is fixed in article surface, and the anti-counterfeiting information of storing in the said internal storage is used for said article are discerned, and said anti-counterfeiting information is associated with the information of the printing decals that is fixed in article surface equally; Be printed with the two-dimensional bar and the ordinary numbers security code of traceable identify objects on the said printing decals; Said two-dimensional bar, ordinary numbers security code and corresponding anti-counterfeiting information are generated by item information data storehouse server, said anti-counterfeiting information is write in the said chip, and the relevant information of said article is arrived central database server through Network Transmission; Said central database server links to each other with item information data storehouse server through network, stores the relevant information of said article, receives by the anti-counterfeiting information of mobile phone transmission and with the authorization information of respective articles and sends to mobile phone.

The chip that the utility model proposes; Wherein, Also store item tracing information in the internal storage of said chip, said item tracing information is write by the special chip read write line of transfer website through separately, and wherein each transfer website has corresponding numbering and binds with special chip read write line separately; The said terminal data in real time relevant with said tracked information of naming a person for a particular job is sent to central database server; And on the server of item information data storehouse, upgrade, the terminal user uses mobile phone to send said anti-counterfeiting information to central database server, and from the central database server, obtains the tracked information of respective articles.

The chip that the utility model proposes; Wherein, The terminal user downloads reading software on the center service database; Read the said anti-counterfeiting information of chip-stored through mobile phone, and said anti-counterfeiting information is sent to central database server, confirm the true and false of article or obtain the tracking and the production information of these article through the internet.

The chip that the utility model proposes; Wherein, Mobile phone also can obtain the two-dimensional bar or the ordinary numbers security code on printed label surface; And the relevant information that gets access to compared through the information in internet and the central database server, confirm the true and false of article and obtain the tracking and the production information of these article; Perhaps relevant information that gets access to and the anti-counterfeiting information that obtains in the chip through common interface module are compared, to realize intersecting comparison.

The chip that the utility model proposes, wherein, the terminal user is at the inquiry commodity true and false or obtain and follow the trail of and during production information, and the short message prompt terminal user prompting of deducting fees after successful query-related information, withholds the relevant inquiring expense by the communication operator.

The chip that the utility model proposes, wherein, said ordinary numbers security code is generated by computing machine, and transforms the corresponding two-dimensional bar of generation through the digital anti-counterfeiting sign indicating number.

Description of drawings

Fig. 1 be the chip that proposes of the utility model inner structure and with the interface synoptic diagram of special chip read write line, mobile phone;

Fig. 2 is the synoptic diagram of microprocessor module;

Fig. 3 is the synoptic diagram of the temporary module of information input in the microprocessor module;

Fig. 4 is the synoptic diagram that information is read in module in the microprocessor module;

Fig. 5 is the synoptic diagram that information is write out module in the microprocessor module;

Fig. 6 is the synoptic diagram of message output module in the microprocessor module;

Fig. 7 is the synoptic diagram of invading detection module in the microprocessor module;

Fig. 8 utilizes the schematic diagram of chip identification article to realize that the orientation is followed the trail of;

Fig. 9 is the synoptic diagram that generates chip and printing decals;

Figure 10 is the synoptic diagram of terminal dot generation item tracing information;

Figure 11 is with chip and prints the synoptic diagram that decals is fixed on body surface.

Embodiment

The following stated is the preferred embodiment of the utility model, does not therefore limit the protection domain of the utility model.

Fig. 1 be the chip that proposes of the utility model internal structure and with the interface synoptic diagram of special chip read write line, mobile phone.As shown in Figure 1; The chip that is used for identify objects that the utility model proposes comprises three parts, is respectively microprocessor, common interface module and internal storage, and this common interface module supports various types of signal such as GSM to realize and the communicating by letter of mobile phone; This internal storage can be disposable programmable read only memory OTP ROM); Wherein, the common interface module of various types of signal such as support GSM is used for the mobile phone realization mutual, particularly; This common interface module receives the checking solicited message of mobile phone transmission and transfers to microprocessor processes, receives the anti-counterfeiting information of microprocessor transmission and sends this anti-counterfeiting information to mobile phone; Microprocessor is used to receive the checking solicited message that comes from common interface module, and based on this checking solicited message, from disposable programmable read only memory, reads anti-counterfeiting information, and this anti-counterfeiting information is sent to common interface module; Disposable programmable read only memory is stored said anti-counterfeiting information.Microprocessor also can be realized communicating by letter with the special chip read write line, and particularly, microprocessor receives and comes from the initialization anti-counterfeiting information of special chip read write line, and in disposable programmable read only memory, writes anti-counterfeiting information.To introduce the inner structure of said chip hereinafter particularly.

The input port of the common interface module of various types of signal such as support GSM has 104,105,109; The output port of the common interface module of various types of signal such as support GSM has 106,107,108; Port one 04 is set up communication with outside port one 01 and is connected, and is used for transmission checking request A1 [7:0], and port one 05 is set up communication with outside port one 02 and is connected, and is used for receive clock 1; Port one 06 is set up communication with outside port one 03 and is connected, and is used for sending outside anti-counterfeiting information B1 [7:0] to the outside; Port one 07 links to each other with the port one 10 of microprocessor, is used to transmit the checking solicited message A [7:0] of input; Port one 08 links to each other with the port one 11 of microprocessor, is used for clock 1 is sent into microprocessor; Port one 09 links to each other with the port one 12 of microprocessor, is used to receive the output anti-counterfeiting information B [7:0] that microprocessor sends.

The disposable programmable read only memory input port has 116,117; Output port is 118; Input port 116 links to each other with the port one 13 of microprocessor; The anti-counterfeiting information J [7:0] that writes is write in the disposable programmable read only memory; The zone to be written of disposable programmable read only memory can only be written into primary information under the control of microprocessor, information can not be modified thereafter; If will append information, then under the control of microprocessor, the information of appending is write other zones to be written of disposable programmable read only memory; Zone to be written then can't be revised once the information of being written into; The area size to be written of disposable programmable read only memory is by the memory capacity decision of disposable programmable read only memory; Input port 117 links to each other with the port one 14 of microprocessor, is used for address Addr [10:0] is sent into the address end of disposable programmable read only memory; Output port 118 links to each other with the port one 15 of microprocessor, is used for the anti-counterfeiting information L [7:0] of address Addr [10:0] appointment is sent into microprocessor.

The input port of microprocessor is 110,111,115,122,123,124; The output port of microprocessor is 112,113,114; Input port 122 links to each other with the port one 19 of the special chip read write line of outside, is used to receive initialization Authority Verification information D; The port one 20 of port one 23 and special chip read write line links to each other, and is used for receive clock 2; The port one 21 of port one 24 and special chip read write line links to each other, and is used to receive initialization anti-counterfeiting information E; The communication mode of initialization anti-counterfeiting information E is a serial communication, and communication protocol meets I ²The C bus protocol; Line between port one 21 and the port one 24 is as I ²The data line SDA of C bus; Line between port one 20 and the port one 23 is I ²The clock SCL of C bus; The communication mode of initialization Authority Verification information D is a serial communication, and communication protocol meets I ²The C bus protocol; Line between port one 19 and the port one 22 is as I ²The data line SDA of C bus; Line between port one 20 and the port one 23 is I ²The clock SCL of C bus; The content of initialization Authority Verification information D is 512 Authority Verification sign indicating numbers, 512 Authority Verification check codes, and 512 authorization codes are authorized check code for 512.

512 its verification modes of Authority Verification check code are 512 Authority Verification sign indicating numbers to be divided into 8 groups 64 message block, are respectively D0 [63:0], D1 [63:0], D2 [63:0], D3 [63:0], D4 [63:0], D5 [63:0], D6 [63:0], D7 [63:0]; With D0 [63:0] is example, and 64 message block D0 [63:0] adopt CRC-32 to generate 32 Cyclic Redundancy Code C0 [31:0], and generator polynomial brief note formula is 04C11DB7 or other feasible generator polynomials; Message block D0 [0:63] is adopting CRC-32 to generate 32 Cyclic Redundancy Code C0 [63:32], and generator polynomial brief note formula is 1EDC6F41 or other feasible generator polynomials, and the check code of forming at last is { C0 [63:0]; C1 [63:0], C2 [63:0], C3 [63:0]; C4 [63:0]; C5 [63:0], C6 [63:0], C7 [63:0] } be 512 Authority Verification check codes.

512 are authorized its verification mode of check code is 512 authorization codes to be divided into 8 groups 64 message block, is respectively D10 [63:0], D11 [63:0], D12 [63:0], D13 [63:0], D14 [63:0], D15 [63:0], D16 [63:0], D17 [63:0]; With D10 [63:0] is example, and 64 message block D10 [63:0] adopt CRC-32 to generate 32 Cyclic Redundancy Code C10 [31:0], and generator polynomial brief note formula is 04C11DB7 or other feasible generator polynomials; Message block D10 [0:63] is adopting CRC-32 to generate 32 Cyclic Redundancy Code C10 [63:32], and generator polynomial brief note formula is 1EDC6F41 or other feasible generator polynomials, and the check code of forming at last is { C10 [63:0]; C11 [63:0], C12 [63:0], C13 [63:0]; C14 [63:0]; C15 [63:0], C16 [63:0], C17 [63:0] } be 512 mandate check codes.

Fig. 2 is the synoptic diagram of microprocessor module.As shown in Figure 2, microprocessor module comprises serial communication controller 1, serial communication controller 2, and the temporary module of information input is invaded detection module, and information is read in module, and information is write out module and message output module.Fig. 3 is the synoptic diagram of the temporary module of information input in the microprocessor module; Fig. 4 is the synoptic diagram that information is read in module in the microprocessor module; Fig. 5 is the synoptic diagram that information is write out module in the microprocessor module; Fig. 6 is the synoptic diagram of message output module in the microprocessor module; Fig. 7 is the synoptic diagram of invading detection module in the microprocessor module.Below, with reference to figure 2-Fig. 7 microprocessor module and each composition module thereof are described.

Serial communication controller 1 meets I with serial communication controller 2 ²The C bus communication protocol; The input port of serial communication controller 1 is 230,231; Serial communication controller 1 output port is 228,229; Port 230 links to each other with the port one 22 of microprocessor, is used to receive initialization authority information D; Port 231 links to each other with microprocessor port one 23, is used for receive clock 2; Port 229 links to each other with the port 220 of invading detection module, is used for sending permission authorization information D1 to the port of invading detection module 220; Port 228 links to each other with the port 221 of invading detection module, and port 228 is direct-connected with port 231, so port 228 is sent to clock 2 port 221 of invading detection module; The input port of serial communication controller 2 is 234,235; Serial communication controller 2 output ports are 232,233; Port 235 links to each other with the port one 24 of microprocessor, is used to receive initialization anti-counterfeiting information E; Port 234 links to each other with microprocessor port one 23, is used for receive clock 2; Port 232 links to each other with the port 207 of the temporary module of information input, is used to send the port 207 of anti-counterfeiting information E1 to the temporary module of information input; Port 233 links to each other with the port 206 of the temporary module of information input, and port 233 is direct-connected with port 234, so port 233 is sent to clock 2 port 206 of the temporary module of information input.

The input port of the temporary module of information input is 201,202,204,206; The output port of the temporary module of information input is 203,205; Port 201 is one eight a bit parallel port, links to each other with eight buses of the port one 10 of microprocessor are corresponding one by one, is used to receive the checking solicited message A [7:0] of input; Port 202 links to each other with the port one 11 of microprocessor, is used for receive clock 1; Port 204 links to each other with the port 212 of invading detection module, is used to receive signal mode control; Port 203 links to each other with two ports 213 of invading detection module, is used for the output system clock; Port 205 links to each other with the port 211 of invading detection module, is used to send input information F to invading detection module.The temporary module of information input is 1 by a width, and the degree of depth is 512 push-up storage, 1 MUX, and 1 parallel-serial converter, one and string signal maker, a system clock maker constitutes; The input end of system clock maker is the clock 1 of port 202 inputs, the clock 2 of port 206 inputs, and the pattern control of port 204 inputs is output as the system clock that port 203 is exported; When the pattern of port 204 inputs is controlled to be high level; The clock 1 of port 202 inputs is from port 203 outputs and as system clock; When the pattern of port 204 inputs was controlled to be low level, the clock 2 of port 206 inputs was from port 203 outputs and as system clock; And the string signal maker is made up of one two input and door and mould 9 counters 1; With the input end of door be the clock 1 of port 202 inputs and two signals of pattern control of port 204 inputs, with the output terminal of door clock trigger end as mould 9 counters 1; Mould 9 counters 1 count value be 9 o'clock output signal also-the string switching signal is a high level, during its remainder values also-the string switching signal is a low level; Parallel-serial converter is when the system clock rising edge of port 203 output, and also-when the string switching signal is high level, be written into the parallel data fake certification information A [7:0] of port 201 inputs, otherwise an input end of SOD serial output data to multichannel selector switch; When MUX is controlled to be high level in the pattern of port 204 inputs; The output terminal of output valve to the push-up storage of output parallel-serial converter; When the pattern of port 204 inputs was controlled to be low level, output anti-counterfeiting information E1 was to the output terminal of push-up storage; Push-up storage is made up of 512 d type flip flops, and the data input pin and the data output end of 512 triggers join end to end, and data output end is the input information F of port 205 outputs.

The input port that information is read in module is 224,223; The output port that information is read in module is 222; Port 224 links to each other with the port one 15 of microprocessor, is used to receive the anti-counterfeiting information L [7:0] of disposable programmable read only memory output; Port 223 links to each other with the port 215 of invading detection module, is used for the receiving system clock; Port 222 links to each other with the port 216 of invading detection module, is used to export anti-counterfeiting information H to invading detection module; It is 8 by a width that information is read in module, the degree of depth be 1 also-string transition trigger device group and mould 9 counters 2 formations; Mould 9 counters 2 the system clock rising edge of port 223 input trigger down counting and output signal also-go here and there switching signal 1; Count value be 9 o'clock also-string switching signal 1 is high level, during its remainder values also-string switching signal 1 is a low level; Parallel-serial converter is when the system clock rising edge of port 223 inputs; And also-when string switching signal 1 is high level; Be written into the anti-counterfeiting information L [7:0] of parallel data port 224 inputs, otherwise SOD serial output data to port 222 is invaded detection module as anti-counterfeiting information H output valve.

The input port that information is write out module is 225,226; The output port that information is write out module is 113; Port 225 links to each other with the port 219 of invading detection module, is used to receive the anti-counterfeiting information I that writes; Port 226 links to each other with the port 218 of invading detection module, is used for the receiving system clock; Port 227 links to each other with the port one 13 of microprocessor, is used to export the anti-counterfeiting information J [7:0] that writes; It is 8 by a width that information is write out module, the degree of depth be 1 string-and transition trigger device group constitute; This string-and the input end of transition trigger device be the anti-counterfeiting information I that writes of port 225 inputs, trigger down at the system clock rising edge of port 226 inputs, export the anti-counterfeiting information J [7:0] that parallel datas write through port 227.

The input port of message output module is 209,236; The output port of message output module is 208; Port 209 links to each other with the port 214 of invading detection module, is used to receive anti-counterfeiting information G to be exported; Port 208 links to each other with the port one 12 of microprocessor, is used for sending output anti-counterfeiting information B [7:0]; Port 236 links to each other with the port 203 of the temporary module of information input, is used for the receiving system clock; Message output module is 8 by a width, the degree of depth be 1 string-and transition trigger device group constitute; This string-and the input end of transition trigger device be the anti-counterfeiting information G to be exported that port 209 receives, trigger down the output anti-counterfeiting information B [7:0] that walks abreast through port 208 outputs at the system clock rising edge of port 236 inputs.

The input port of invading detection module is 211,213,216,220,221; The output port of invading detection module is 212,214,215,217,218,219; Input port 213 is direct-connected with output port 215,218, and port 215,218 is used for direct output system clock; Input port 216 links to each other with output port 214, is used for anti-counterfeiting information H directly is sent to the input port 209 of message output module; The output port 114 of port 217 and microprocessor links to each other, and is used for to disposable programmable read only memory OPADD Addr [10:0].Invade detection module and comprise the mode control signal maker, address generation module, anti-counterfeiting information programming module.

The mode control signal maker is by three d type flip flops, and the rejection gate of one three input one output is formed; Joining end to end of three d type flip flops, input end are the Authority Verification information D 1 of port 220 inputs; The clock end of three d type flip flops all links to each other with clock 2; The output terminal of three a d type flip flops input end of AND respectively links to each other; The output terminal of rejection gate is the pattern control of port 212 outputs.

The address generation module is formed with door and address generator by one; Address generator is counting under the rising edge with door output triggers, and count value is exported through port 217 as 11 address Addr [10:0].

Anti-counterfeiting information programming module is 1 by two width, and the degree of depth is 512 push-up storage, XOR gate, and two and door, mould 1024 frequency dividers, a d type flip flop, a CRC maker is formed; Push-up storage 1 is made up of 512 d type flip flops; The data input pin and the data output end of 512 triggers join end to end; Push-up storage 1 data output end is the Authority Verification information D 1 of port 220 inputs, and input end of data output end and XOR gate links to each other; The clock end of push-up storage 1 is the system clock of port 213 inputs; Push-up storage 2 is made up of 512 d type flip flops, and the data input pin and the data output end of 512 triggers join end to end, and push-up storage 2 data output ends are the check code of CRC maker output, and input end of output terminal and XOR gate links to each other; The clock end of push-up storage 2 is the system clock of port 213 inputs; Mould 1024 frequency dividers carry out frequency division to the system clock of port 213 input, and divide ratio is 1024, output terminal with link to each other with an input end of door 1; Mould 1024 frequency dividers carry out frequency division to the system clock of port 213 inputs; The output terminal of XOR gate with link to each other with another output terminal of door 1; Link to each other with the clock end of d type flip flop with the output terminal of door 1; The data terminal of d type flip flop links to each other with power supply, and the oppisite phase data end of d type flip flop links to each other with the data input pin with door 2; The input information F of port 211 inputs links to each other with another data input pin of door 2; Be the anti-counterfeiting information I that writes and pass through port 219 outputs with the data output end of door 2.

Microprocessor has the writing information pattern, and two mode of operations of information contrastive pattern are by the mode of operation of invading the control module control microprocessor.

Special-purpose chip read write line is down synchronous clock 2, through port one 24 initialization anti-counterfeiting information E is write in the serial communication controller 2, and serial communication controller 2 is according to I ²The C bus protocol reverts to anti-counterfeiting information E1 with initialization anti-counterfeiting information E, and anti-counterfeiting information E1 is sent into the information temporary storage module; Special-purpose chip read write line is down synchronous clock 2, through port one 22 initialization Authority Verification information D is write in the serial communication controller 1, and serial communication controller 1 is according to I ²The C bus protocol reverts to serial data Authority Verification information D 1 with initialization Authority Verification information D, and Authority Verification information D 1 is sent into the intrusion detection module; The intrusion detection module is sent the anti-counterfeiting information I that writes into information and is write out module when detecting Authority Verification information D 1 for after the legal information; Information is write out module and under the triggering of system clock, the anti-counterfeiting information J [7:0] that writes is write disposable programmable read only memory; Disposable programmable read only memory writes assigned address with the anti-counterfeiting information J [7:0] that writes under the control of address Addr [10:0].

The general-purpose interface of mobile phone through supporting various types of signal such as GSM clock 1 synchronously down, the checking solicited message A [7:0] of input is sent into the temporary module of information input; Trigger down with the rising edge of signal at system clock and input information F, intrusion detection module calculated address Addr [10:0] sends into disposable programmable read only memory; Information is read in the anti-counterfeiting information L [7:0] that module is read in disposable programmable read only memory output; The anti-counterfeiting information H that the intrusion detection module reads in information in the module directly sends into message output module as anti-counterfeiting information G to be exported; Last under the triggering of clock, message output module will be exported anti-counterfeiting information B [7:0] and send to mobile phone through common interface module.

Fig. 8 utilizes the schematic diagram of chip identification article to realize that the orientation is followed the trail of.Description by preceding text can be known; Mobile phone can read the anti-counterfeiting information of disposable programmable read only memory stored in the chip through said common interface module, in Fig. 8, this azimuth information is called article identification information; Be used for article are discerned; Comprise identification information in the said article identification information, and said chip be fixed in article surface that canned data is associated with the information of printing decals on its internal storage; Comprise the two-dimensional bar and the ordinary numbers security code of traceable identify objects on the printing decals, the ordinary numbers security code is generated by computing machine, and transforms the corresponding two-dimensional bar of generation through the digital anti-counterfeiting sign indicating number, is printed in the decals surface; Item information data storehouse server generates said two-dimensional bar, ordinary numbers security code and corresponding article identification information; And in the process of producing printing decals and chip; Two-dimensional bar, ordinary numbers security code are printed in the decals surface; Article identification information is write chip internal, and concrete ablation process is as indicated above, and the relevant information with said article is transferred on the central database server through computer network simultaneously; Central database server is stored the relevant information of said article, links to each other with item information data storehouse server through network, stores the relevant information of said article, receives the identification information that sent by mobile phone and the authorization information of respective articles is sent to mobile phone; Mobile phone links to each other with chip through common interface module, reads the article identification information of preserving in the internal storage in the chip.

Fig. 9 is the synoptic diagram that generates chip and printing decals.As shown in Figure 9; Item information data storehouse server writes article identification information in the storer of said chip through the special chip read write line; And print the printing decals, simultaneously, the information relevant with article is transferred to central database server through computer network.

Figure 10 is the synoptic diagram of terminal dot generation item tracing information.Shown in figure 10; The transfer website writes item tracing information through the special chip read write line; Each transfer website have corresponding numbering and with the binding of special chip read write line; The terminal data in real time relevant with said tracked information of naming a person for a particular job is sent to central database server, and on the server of item information data storehouse, upgrades.

The terminal user can be on central database server download terminal software, through the mobile phone read write tag, and relevant information compared through the information of internet and central database, confirm the true and false and tracking, the production information of article; Can also select to confirm the true and false and the tracked information of article through the printing decals; The terminal user is through the mobile phone of band camera; Read the two-dimensional bar on printed label surface; And relevant information compared through internet and central database, confirm the true and false and tracking, the production information of article.

The terminal user is when inquiry commodity true and false and tracking, production information, and the short message prompt terminal user prompting of deducting fees after successful query-related information, withholds the relevant inquiring expense by the communication operator.

Figure 11 is with chip and prints the synoptic diagram that decals is fixed on body surface.Shown in figure 11, can the form of chip with trade mark or bottle cap be fixed on article surface; Also can the printing decals relevant with the chip stored information be fixed in body surface in the lump.The user can read out the canned data in the chip tag through mobile phone; And through network connection central server; Obtaining the information and the comparison of corresponding sequence number commodity tells truth from falsehood; That is, the article mark information in the chip tag is sent to central database, whether central database returns according to the identification information of these article is true and false product; The user can carry out authenticity verification and tracking and managing through the two-dimension code and the digital anti-counterfeiting sign indicating number on printing decals surface simultaneously.

In the specific implementation, can Chip Packaging within bottle cap, be stamped the information of these article simultaneously and reserve the two-dimension code print area and digital anti-counterfeiting code printing zone on the printing decals according to user's request; PC is according to the numbering of these article, production time, the term of validity, packaged form etc.; Go out the digital anti-counterfeiting sign indicating number of these article through computed in software; And generate corresponding two-dimensional bar according to this digital anti-counterfeiting sign indicating number, be printed to the assigned address of printing decals, and paste and specify on the article; After having generated the printing decals; According to corresponding information; Generate the chip writing information, utilize proprietary application software that two-dimension code data, digital anti-counterfeiting code data, Item Number, lot number, production time, the term of validity of gathering are carried out the encryption association calculation process, and cleartext information is converted into cipher-text information; Through the special chip read write line corresponding information is write the appointment chip, and the bottle cap that will comprise this chip is fixed on the article; Article warehouse-ins is during with outbound, through read-and-write device, easily statistics put in storage, information such as the kind of outbound article, quantity, time, handler, and deposit these information in database, for the usefulness of data examination; After article got into the transfer website, the flow direction of these article is in time understood and monitored to the information that the manufacturer of these article can upload through each transfer website; The transfer websites at different levels of these article can be through the visit central database server, and the relevant information of inquiring about these article also can write the information of transfer website according to individual demand, to enrich the tracked information of these article in the RFID label; The user inquires about the true and false, date of expiration and other relevant informations of product through the visit central database server, thereby satisfies user's right to know well, and differentiates the true and false of these article.

Traditional false proof method for tracing based on the RFID RF identification must use specialized equipment, is not easy to end user query and use, uses the chip that is used for identify objects of the utility model then fundamentally to solve this problem.The terminal user only need have the mobile phone that possesses the general-purpose interface of supporting various types of signal such as GSM can carry out true-false inquiring and commodity circulation information, and the mobile phone that part does not possess the general-purpose interface of supporting various types of signal such as GSM then can carry out the identification of two-dimension code anti-counterfeit identification XOR digital anti-counterfeiting sign indicating number through the printing decals.Therefore, use the chip of the utility model, have very strong extensibility and compatibility; Can realize the mutual of data message and share; And the function that article genuine-fake is differentiated and article are followed the trail of is provided, thereby this chip can be used for buyer the distinguishing this authenticity of products of manufacturer to institute's production products in circulation, the monitoring of selling each link and this product; In central database server, comprise label generation module, logistics and storage module, enquiry module; In the server of item information data storehouse, comprise logistics and storage module, enquiry module, production management module; The transfer website can be product distribution merchant or transfer merchant; At this moment, use the chip of the utility model, can make things convenient for Inner Logistics Management; Based on the chip identification article, realize the materials circulation automatic management; Retail trader or terminal have the right chip is appended operation, can inquire the circulation status of article easily, prevent the risk of string goods simultaneously.The terminal user can be through the general-purpose interface of various types of signal such as mobile phone support GSM; Carrying out the chip read-write sets; Support the common interface module coupling of various types of signal such as GSM in this general-purpose interface and the chip; The various types of signal that those skilled in the art can select the common interface module in the chip to support according to the mobile phone kind, here the GSM signal just as an example, as restriction to the utility model; Perhaps carry out two-dimension code or the identification of digital anti-counterfeiting sign indicating number through the printing paster through SMS platform.Therefore, concerning the user, this chip is convenient and simple, and the terminal user does not produce any cost.Simultaneously; The chip that the utility model proposes can pass through portable battery or solar cell or external electromagnetic energy to chip power supply; But these concrete power supply modes are not as the restriction to the application's protection domain; To those skilled in the art, can use the power supply of any existing techniques in realizing chip.

Should note; Embodiment that the utility model proposed and application are merely illustrative purposes; Not as to the restriction of the utility model protection domain, those skilled in the art can make amendment and are applied in the various practical applications of certain article being carried out anti-counterfeit recognition or tracking the embodiment of the utility model.

Claims

1. one kind is used for identify objects to realize the chip of false proof tracking, it is characterized in that:

Said chip comprises microprocessor, common interface module and internal storage, and said common interface module is connected with said microprocessor, and said microprocessor is connected with said internal storage, wherein:

Said common interface module receives the checking solicited message that mobile phone sends, and should verify that solicited message transferred to microprocessor processes, receives the anti-counterfeiting information of microprocessor transmission and to this anti-counterfeiting information of mobile phone transmission;

Said microprocessor receives the checking solicited message that comes from said common interface module, based on this checking solicited message, from said internal storage, reads said anti-counterfeiting information, and said anti-counterfeiting information is sent to common interface module;

Said internal storage is stored said anti-counterfeiting information.

2. chip according to claim 1 is characterized in that:

Said common interface module supports the GSM signal to communicate with mobile phone, and said internal storage can be disposable programmable read only memory (OTP ROM).

3. chip according to claim 2 is characterized in that:

Said microprocessor also receives the initialization anti-counterfeiting information that comes from the special chip read write line, and in said internal storage, writes anti-counterfeiting information.

4. chip according to claim 2 is characterized in that: the input port of said common interface module is port (104), port (105) and port (109); Output port is port (106), port (107) and port (108); Port (104) is set up communication with outside port (101) and is connected, and is used for transmission checking solicited message A1 [7:0], and port (105) is set up communication with outside port (102) and is connected, and is used for receive clock 1; Port (106) is set up communication with outside port (103) and is connected, and is used for sending outside anti-counterfeiting information B1 [7:0] to the outside; Port (107) links to each other with the port (110) of microprocessor, is used to transmit the checking solicited message A [7:0] of input; Port (108) links to each other with the port (111) of microprocessor, is used for clock 1 is sent into microprocessor; Port (109) links to each other with (112) port of microprocessor, is used to receive the output anti-counterfeiting information B [7:0] that microprocessor sends.

5. chip according to claim 2 is characterized in that: said disposable programmable read only memory input port ports having (116) and port (117); Output port is port (118); Input port (116) links to each other with the port (113) of microprocessor; The anti-counterfeiting information J [7:0] that writes is write in the disposable programmable read only memory; The zone to be written of disposable programmable read only memory can only be written into primary information under the control of microprocessor, information can not be modified thereafter; If will append information, then under the control of microprocessor, the information of appending is write other zones to be written of disposable programmable read only memory; Zone to be written then can't be revised once the information of being written into; The area size to be written of disposable programmable read only memory is by the memory capacity decision of disposable programmable read only memory; Input port (117) links to each other with the port (114) of microprocessor, is used for address Addr [10:0] is sent into the address end of disposable programmable read only memory; Output port (118) links to each other with the port (115) of microprocessor, is used for the anti-counterfeiting information L [7:0] of address Addr [10:0] appointment is sent into microprocessor.

6. chip according to claim 3 is characterized in that: the input port of microprocessor is port (110), port (111), port (115), port (122), port (123) and port (124); The input port of microprocessor is port (112), port (113) and port (114); Input port (122) links to each other with the port (119) of the special chip read write line of outside, is used to receive initialization Authority Verification information D; The port (120) of port (123) and special chip read write line links to each other, and is used for receive clock 2; The port (121) of port (124) and special chip read write line links to each other, and is used to receive initialization anti-counterfeiting information E.

7. chip according to claim 6 is characterized in that: the communication mode of said initialization anti-counterfeiting information E is a serial communication, and communication protocol meets I ²The C bus protocol; Line between port (121) and the port (124) is as I ²The data line SDA of C bus; Line between port (120) and the port (123) is I ²The clock SCL of C bus; The communication mode of initialization Authority Verification information D is a serial communication, and communication protocol meets I ²The C bus protocol; Line between port (119) and the port (122) is as I ²The data line SDA of C bus; Line between port (120) and the port (123) is I ²The clock SCL of C bus; The content of initialization Authority Verification information D is 512 Authority Verification sign indicating numbers, 512 Authority Verification check codes, and 512 authorization codes are authorized check code for 512.

8. chip according to claim 3 is characterized in that: microprocessor comprises that serial communication controller (1), serial communication controller (2), the temporary module of information input, intrusion detection module, information are read in module, information is write out module and message output module.

9. chip according to claim 8 is characterized in that: serial communication controller (1) and serial communication controller (2) meet I ²The C bus communication protocol; The input port of serial communication controller (1) is port (230), port (231); Serial communication controller (1) output port is port (228), port (229); Port (230) links to each other with the port (122) of microprocessor, is used to receive initialization authority information D; Port (231) links to each other with microprocessor port (123), is used for receive clock 2; Port (229) links to each other with the port (220) of invading detection module, is used for sending permission authorization information D1 to the port of invading detection module (220); Port (228) links to each other with the port (221) of invading detection module, and port (228) and port (231) are direct-connected, so port (228) is sent to clock 2 port (221) of invading detection module; The input port of serial communication controller (2) is port (234), port (235); Serial communication controller (2) output port is port (232), port (233); Port (235) links to each other with the port (124) of microprocessor, is used to receive initialization anti-counterfeiting information E; Port (234) links to each other with microprocessor port (123), is used for receive clock 2; Port (232) links to each other with the port (207) of the temporary module of information input, is used to send the port (207) of anti-counterfeiting information E1 to the temporary module of information input; Port (233) links to each other with the port (206) of the temporary module of information input, and port (233) and port (234) are direct-connected, so port (233) is sent to clock 2 port (206) of the temporary module of information input.

10. chip according to claim 8 is characterized in that: the input port of the temporary module of information input is port (201), port (202), port (204), port (206); The output port of the temporary module of information input is port (203), port (205); Port (201) is one eight a bit parallel port, links to each other with eight buses of the port (110) of microprocessor are corresponding one by one, is used to receive the checking solicited message A [7:0] of input; Port (202) links to each other with the port (111) of microprocessor, is used for receive clock 1; Port (204) links to each other with the port (212) of invading detection module, is used to receive signal mode control; Port (203) links to each other with two ports (213) of invading detection module, is used for the output system clock; Port (205) links to each other with the port (211) of invading detection module, is used to send input information F to invading detection module; The temporary module of information input is 1 by a width, and the degree of depth is 512 push-up storage, 1 MUX, and 1 parallel-serial converter, one and string signal maker, a system clock maker constitutes; The input end of system clock maker is the clock 1 of port (202) input, the clock 2 of port (206) input, and the pattern control of port (204) input is output as the system clock that port (203) is exported; When the pattern of port (204) input is controlled to be high level; The clock 1 of port (202) input is from port (203) output and as system clock; When the pattern of port (204) input was controlled to be low level, the clock 2 of port (206) input was from port (203) output and as system clock; And the string signal maker is made up of one two input and door and mould 9 counters 1; With the input end of door be that the clock 1 of port (202) input is controlled two signals with the pattern of port (204) input, with the output terminal of door clock trigger end as mould 9 counters 1; Mould 9 counters 1 count value be 9 o'clock output signal also-the string switching signal is a high level, during its remainder values also-the string switching signal is a low level; Parallel-serial converter is when the system clock rising edge of port (203) output, and also-when the string switching signal is high level, be written into the parallel data fake certification information A [7:0] of port (201) input, otherwise an input end of SOD serial output data to multichannel selector switch; When MUX is controlled to be high level in the pattern of port (204) input; The output terminal of output valve to the push-up storage of output parallel-serial converter; When the pattern of port (204) input was controlled to be low level, output anti-counterfeiting information E1 was to the output terminal of push-up storage; Push-up storage is made up of 512 d type flip flops, and the data input pin and the data output end of 512 triggers join end to end, and data output end is the input information F of port (205) output.

11. chip according to claim 8 is characterized in that: the input port that information is read in module is (224), (223); The output port that information is read in module is (222); Port (224) links to each other with the port (115) of microprocessor, is used to receive the anti-counterfeiting information L [7:0] of disposable programmable read only memory output; Port (223) links to each other with the port (215) of invading detection module, is used for the receiving system clock; Port (222) links to each other with the port (216) of invading detection module, is used to export anti-counterfeiting information H to invading detection module; It is 8 by a width that information is read in module, the degree of depth be 1 also-string transition trigger device group and mould 9 counters 2 formations; Mould 9 counters 2 the system clock rising edge of port (223) input trigger down counting and output signal also-go here and there switching signal 1; Count value be 9 o'clock also-string switching signal 1 is high level, during its remainder values also-string switching signal 1 is a low level; Parallel-serial converter is when the system clock rising edge of port (223) input; And also-when string switching signal 1 is high level; Be written into the anti-counterfeiting information L [7:0] of parallel data port (224) input, otherwise SOD serial output data to port (222) is invaded detection module as anti-counterfeiting information H output valve.

12. chip according to claim 8 is characterized in that: the input port that information is write out module is port (225), port (226); The output port that information is write out module is port (113); Port (225) links to each other with the port (219) of invading detection module, is used to receive the anti-counterfeiting information I that writes; Port (226) links to each other with the port (218) of invading detection module, is used for the receiving system clock; Port (227) links to each other with the port (113) of microprocessor, is used to export the anti-counterfeiting information J [7:0] that writes; It is 8 by a width that information is write out module, the degree of depth be 1 string-and transition trigger device group constitute; This string-and the input end of transition trigger device be the anti-counterfeiting information I that writes of port (225) input, trigger down at the system clock rising edge of port (226) input, export the anti-counterfeiting information J [7:0] that parallel data writes through port (227).

13. chip according to claim 8 is characterized in that: the input port of message output module is (209), (236); The output port of message output module is (208); Port (209) links to each other with the port (214) of invading detection module, is used to receive anti-counterfeiting information G to be exported; Port (208) links to each other with the port (112) of microprocessor, is used for sending output anti-counterfeiting information B [7:0]; Port (236) links to each other with the port (203) of the temporary module of information input, is used for the receiving system clock; Message output module is 8 by a width, the degree of depth be 1 string-and transition trigger device group constitute; This string-and the input end of transition trigger device be the anti-counterfeiting information G to be exported that port (209) receives, trigger down the output anti-counterfeiting information B [7:0] that walks abreast through port (208) output at the system clock rising edge of port (236) input.

14. chip according to claim 8 is characterized in that: the input port of invading detection module is port (211), port (213), port (216), port (220), port (221); The output port of invading detection module is port (212), port (214), port (215), port (217), port (218), port (219); Input port (213) and output port (215), port (218) is direct-connected, port (215), port (218) is used for direct output system clock; Input port (216) links to each other with output port (214), is used for anti-counterfeiting information H directly is sent to the input port (209) of message output module; The output port (114) of port (217) and microprocessor links to each other, and is used for to disposable programmable read only memory OPADD Addr [10:0]; Invade detection module and form mode control signal maker, address generation module, anti-counterfeiting information programming module by following module.

15. chip according to claim 14 is characterized in that: the mode control signal maker is by three d type flip flops, and the rejection gate of one three input one output is formed; Joining end to end of three d type flip flops, input end are the Authority Verification information D 1 of port (220) input; The clock end of three d type flip flops all links to each other with clock 2; The output terminal of three a d type flip flops input end of AND respectively links to each other; The output terminal of rejection gate is the pattern control of port (212) output.

16. chip according to claim 14 is characterized in that: the address generation module is formed with door and address generator by one; Address generator is counting under the rising edge with door output triggers, and count value is exported through port (217) as 11 address Addr [10:0].

17. chip according to claim 14 is characterized in that: anti-counterfeiting information programming module is 1 by two width, and the degree of depth is 512 push-up storage, XOR gate, and two and door, mould 1024 frequency dividers, a d type flip flop, a CRC maker is formed; Push-up storage 1 is made up of 512 d type flip flops; The data input pin and the data output end of 512 triggers join end to end; Push-up storage 1 data output end is the Authority Verification information D 1 of port (220) input, and input end of data output end and XOR gate links to each other; The clock end of push-up storage 1 is the system clock of port (213) input; Push-up storage 2 is made up of 512 d type flip flops, and the data input pin and the data output end of 512 triggers join end to end, and push-up storage 2 data output ends are the check code of CRC maker output, and input end of output terminal and XOR gate links to each other; The clock end of push-up storage 2 is the system clock of port (213) input; Mould 1024 frequency dividers carry out frequency division to the system clock of port (213) input, and divide ratio is 1024, output terminal with link to each other with an input end of door 1; Mould 1024 frequency dividers carry out frequency division to the system clock of port (213) input; The output terminal of XOR gate with link to each other with another output terminal of door 1; Link to each other with the clock end of d type flip flop with the output terminal of door 1; The data terminal of d type flip flop links to each other with power supply, and the oppisite phase data end of d type flip flop links to each other with the data input pin with door 2; The input information F of port 211 inputs links to each other with another data input pin of door 2; Be the anti-counterfeiting information I that writes and pass through port (219 outputs with the data output end of door 2.

18. chip according to claim 8 is characterized in that: microprocessor has the writing information pattern, and two mode of operations of information contrastive pattern are by the mode of operation of invading the control module control microprocessor.

19. chip according to claim 18; It is characterized in that: special-purpose chip read write line is down synchronous clock 2; Through port (124) initialization anti-counterfeiting information E is write in the serial communication controller 2; Serial communication controller 2 reverts to anti-counterfeiting information E1 according to the 12C bus protocol with initialization anti-counterfeiting information E, and anti-counterfeiting information E1 is sent into the information temporary storage module; Special-purpose chip read write line is down synchronous clock 2, through port (122) initialization Authority Verification information D is write in the serial communication controller 1, and serial communication controller 1 is according to I ²The C bus protocol reverts to serial data Authority Verification information D 1 with initialization Authority Verification information D, and Authority Verification information D 1 is sent into the intrusion detection module; The intrusion detection module is sent the anti-counterfeiting information I that writes into information and is write out module when detecting Authority Verification information D 1 for after the legal information; Information is write out module and under the triggering of system clock, the anti-counterfeiting information J [7:0] that writes is write disposable programmable read only memory; Disposable programmable read only memory writes assigned address with the anti-counterfeiting information J [7:0] that writes under the control of address Addr [10:0].

20. chip according to claim 18 is characterized in that: mobile phone through common interface module clock 1 synchronously down, the fake certification information A [7:0] of input is sent into the temporary module of information input; Trigger down with the rising edge of signal at system clock and input information F, intrusion detection module calculated address Addr [10:0] sends into disposable programmable read only memory; Information is read in the anti-counterfeiting information L [7:0] that module is read in disposable programmable read only memory output; The anti-counterfeiting information H that the intrusion detection module reads in information in the module directly sends into message output module as anti-counterfeiting information G to be exported; Last under the triggering of clock, message output module will be exported anti-counterfeiting information B [7:0] and send to mobile phone through common interface module.