CN102262742B - Item identification chip for implementing anti-counterfeiting tracking - Google Patents

Item identification chip for implementing anti-counterfeiting tracking Download PDF

Info

Publication number
CN102262742B
CN102262742B CN201110153664.8A CN201110153664A CN102262742B CN 102262742 B CN102262742 B CN 102262742B CN 201110153664 A CN201110153664 A CN 201110153664A CN 102262742 B CN102262742 B CN 102262742B
Authority
CN
China
Prior art keywords
port
information
input
module
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201110153664.8A
Other languages
Chinese (zh)
Other versions
CN102262742A (en
Inventor
林加缪
徐良雨
周华
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HANGZHOU BOLIAN ZHIXIN TECHNOLOGY CO., LTD.
Original Assignee
HANGZHOU BOLIAN ZHIXIN TECHNOLOGY Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HANGZHOU BOLIAN ZHIXIN TECHNOLOGY Co Ltd filed Critical HANGZHOU BOLIAN ZHIXIN TECHNOLOGY Co Ltd
Priority to CN201110153664.8A priority Critical patent/CN102262742B/en
Publication of CN102262742A publication Critical patent/CN102262742A/en
Application granted granted Critical
Publication of CN102262742B publication Critical patent/CN102262742B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Storage Device Security (AREA)

Abstract

The invention provides an item identification chip for implementing anti-counterfeiting tracking, belongs to the technical field of anti-counterfeiting tracking. The chip comprises a microprocessor, a general-purpose interface module and an internal memory, wherein the general-purpose interface module is connected with the microprocessor; the microprocessor is connected with the internal storage; the general-purpose interface module receives a verification request message transmitted by a mobile phone, transfers the verification request message to the microprocessor so as to process the verification request message, receives an anti-counterfeiting message transmitted by the microprocessor and transmits the anti-counterfeiting message to the mobile phone; the microprocessor receives the verification request message from the general-purpose interface module, reads the anti-counterfeiting message from the internal memory according to the verification request message, and transmits the anti-counterfeiting message to the general-purpose interface module; and the internal memory stores the anti-counterfeiting message. The invention solves the problems of inconvenience, high cost and the like in the existing anti-counterfeiting tracking technology, and has the advantages of physical uniqueness, high security, high tracking performance, favorable contamination resistance and the like, and is convenient for users.

Description

Be used for identify objects to realize the chip of anti-counterfeit tracking
Technical field
The invention belongs to anti-counterfeit tracking technical field, relate in particular to a kind of for identify objects to realize the chip of anti-counterfeit tracking.
Background technology
Anti-counterfeiting technology refers to the measure of taking in order to reach false proof object, and it is accurately to discern the false from the genuine within the specific limits, and is difficult for the technology that is imitated and copies.Be exactly briefly to prevent from copying, counterfeit technology.
Existing anti-counterfeit tracking product, from technical characterictic and function evolution angular divisions, roughly can be divided into four classes: laser anti-counterfeit, digital code anti-false, bar code anti-counterfeit tracking, RFID identification anti-counterfeit tracking technology.For laser antifalsification technology, because user does not recognize the ability that label is true and false, and label is also easy to forge, and therefore lacking contrast property in the situation that, and 60% counterfeit and 100% genuine piece are difficult to confirmation; Next is that temperature becomes label, is also easy to forge although user is easy to identification; Query formulation numerical code anti-fake label, user can pass through the true and false of phone, note, internet checking digital label.But because the false proof essence of this class is all to need user's Self-operating, comparatively loaded down with trivial details in program, therefore some users that are unfamiliar with note and online may abandon.
Two-Dimensional Bar-Code Technologies is the increasing anti-counterfeiting technology using in recent years, but because two-dimensional bar itself does not possess too many information and value, and its value only has by networking and undertaken after data query checks, just seeming meaningful.Existing two-dimensional bar anti-counterfeiting technology rests on easy single cognitive phase mostly, does not possess online query function.Help Center's server also majority rests on the self-built stage of company, does not possess large-scale networked query capability.
RFID is a kind of new life's anti-counterfeit tracking technology, in logistics management, is widely used.But existing rfid system need adopt special read-write equipment and expensive, be unwell to terminal client buying.
Summary of the invention
Use in order to solve the inconvenient user who runs in the time that article are realized to anti-counterfeit tracking, high in cost of production problem, the present invention proposes a kind of for identify objects to realize the chip of anti-counterfeit tracking, described chip comprises microprocessor, common interface module and internal storage, described common interface module is connected with described microprocessor, described microprocessor is connected with described internal storage, wherein: described common interface module receives the checking solicited message that mobile phone sends, this checking solicited message is transferred to microprocessor processes, receive the anti-counterfeiting information of microprocessor transmission and send this anti-counterfeiting information to mobile phone, described microprocessor receives the checking solicited message that comes from described common interface module, based on this checking solicited message, reads described anti-counterfeiting information from described internal storage, and described anti-counterfeiting information is sent to common interface module, described internal storage is stored described anti-counterfeiting information.
The chip that the present invention proposes, wherein, described common interface module supports GSM signal to communicate with mobile phone, described internal storage can be disposable programmable read only memory (OTP ROM).
The chip that the present invention proposes, wherein, described microprocessor also receives the initialization anti-counterfeiting information that comes from special chip read write line, and writes anti-counterfeiting information in described internal storage.
The chip that the present invention proposes, wherein, the input port of described common interface module is port one 04, port one 05 and port one 09; Output port is port one 06, port one 07 and port one 08; Port one 04 is set up communication with outside port one 01 and is connected, for transmitting checking solicited message A1[7:0], port one 05 is set up communication with outside port one 02 and is connected, for receive clock 1; Port one 06 is set up communication with outside port one 03 and is connected, for send outside anti-counterfeiting information B1[7:0 to outside]; Port one 07 is connected with the port one 10 of microprocessor, for transmitting the checking solicited message A[7:0 of input]; Port one 08 is connected with the port one 11 of microprocessor, for clock 1 is sent into microprocessor; Port one 09 is connected with 112 ports of microprocessor, the output anti-counterfeiting information B[7:0 sending for receiving microprocessor].
The chip that the present invention proposes, wherein, the ports having 116 of described disposable programmable read only memory input port and port one 17; Output port is port one 18; Input port 116 is connected with the port one 13 of microprocessor, by the anti-counterfeiting information J[7:0 writing] write in disposable programmable read only memory, the region to be written of disposable programmable read only memory can only be written into primary information under the control of microprocessor, and information can not be modified thereafter; If want supplement information,, under the control of microprocessor, supplement information is write to other regions to be written of disposable programmable read only memory; Region to be written, once being written into information, cannot be revised; The area size to be written of disposable programmable read only memory is determined by the memory capacity of disposable programmable read only memory; Input port 117 is connected with the port one 14 of microprocessor, for by address Addr[10:0] send into the address end of disposable programmable read only memory; Output port 118 is connected with the port one 15 of microprocessor, for by address Addr[10:0] the anti-counterfeiting information L[7:0 that specifies] send into microprocessor.
The chip that the present invention proposes, wherein, the input port of microprocessor is port one 10, port one 11, port one 15, port one 22, port one 23 and port one 24; The input port of microprocessor is port one 12, port one 13 and port one 14; The port one 19 of input port 122 and outside special chip read write line is connected, for receiving initialization Authority Verification information D; The port one 20 of port one 23 and special chip read write line is connected, for receive clock 2; The port one 21 of port one 24 and special chip read write line is connected, for receiving initialization anti-counterfeiting information E.
The chip that the present invention proposes, wherein, the communication mode of described initialization anti-counterfeiting information E is serial communication, communication protocol meets I 2c bus protocol; Line between port one 21 and port one 24 is as I 2the data line SDA of C bus; Line between port one 20 and port one 23 is I 2the clock SCL of C bus; The communication mode of initialization Authority Verification information D is serial communication, and communication protocol meets I 2c bus protocol; Line between port one 19 and port one 22 is as I 2the data line SDA of C bus; Line between port one 20 and port one 23 is I 2the clock SCL of C bus; The content of initialization Authority Verification information D is 512 Authority Verification codes, 512 Authority Verification check codes, and 512 authorization codes, authorize check code for 512.
The chip that the present invention proposes, wherein, described 512 its verification modes of Authority Verification check code are 512 Authority Verification codes to be divided into the message block of 8 groups 64, are respectively D0[63:0], D1[63:0], D2[63:0], D3[63:0] and, D4[63:0], D5[63:0], D6[63:0], D7[63:0]; Taking D0[63:0] be example, 64 message block D0[63:0] adopt CRC-32 to generate 32 Cyclic Redundancy Code C0[31:0], generator polynomial brief note formula is 04C11DB7 or other feasible generator polynomials, message block D0[0:63] adopting CRC-32 to generate 32 Cyclic Redundancy Code C0[63:32], generator polynomial brief note formula is 1EDC6F41 or other feasible generator polynomials, finally composition check code be C0[63:0], C1[63:0], C2[63:0], C3[63:0], C4[63:0], C5[63:0], C6[63:0], C7[63:0] be 512 Authority Verification check codes.
The chip that the present invention proposes, wherein, described 512 its verification modes of mandate check code are 512 authorization codes to be divided into the message block of 8 groups 64, are respectively D10[63:0], D11[63:0], D12[63:0], D13[63:0] and, D14[63:0], D15[63:0], D16[63:0], D17[63:0], taking D10[63:0] be example, 64 message block D10[63:0] adopt CRC-32 to generate 32 Cyclic Redundancy Code C10[31:0], generator polynomial brief note formula is 04C11DB7 or other feasible generator polynomials, message block D10[0:63] adopting CRC-32 to generate 32 Cyclic Redundancy Code C10[63:32], generator polynomial brief note formula is 1EDC6F41 or other feasible generator polynomials, finally composition check code be C10[63:0], C11[63:0], C12[63:0], C13[63:0], C14[63:0], C15[63:0], C16[63:0], C17[63:0] } be 512 mandate check codes.
The chip that the present invention proposes, wherein, microprocessor comprises that serial communication controller 1, serial communication controller 2, the temporary module of input information, intrusion detection module, information are read in module, information is write out module and message output module.
The chip that the present invention proposes, wherein, serial communication controller 1 and serial communication controller 2 meet I 2c bus communication protocol; The input port of serial communication controller 1 is port 230, port 231; Serial communication controller 1 output port is port 228, port 229; Port 230 is connected with the port one 22 of microprocessor, for receiving initialization authority information D; Port 231 is connected with microprocessor port one 23, for receive clock 2; Port 229 with invade the port 220 of detection module and be connected, for sending permission authorization information D1 to the port 220 of invading detection module; Port 228 is connected with the port 221 of invading detection module, and port 228 and port 231 are direct-connected, and therefore port 228 is sent to clock 2 port 221 of invading detection module; The input port of serial communication controller 2 is port 234, port 235; Serial communication controller 2 output ports are port 232, port 233; Port 235 is connected with the port one 24 of microprocessor, for receiving initialization anti-counterfeiting information E; Port 234 is connected with microprocessor port one 23, for receive clock 2; Port 232 is connected with the port 207 of the temporary module of input information, for sending the port 207 of anti-counterfeiting information E1 to the temporary module of input information; Port 233 is connected with the port 206 of the temporary module of input information, and port 233 and port 234 are direct-connected, and therefore port 233 is sent to clock 2 port 206 of the temporary module of input information.
The chip that the present invention proposes, wherein, the input port of the temporary module of input information is port 201, port 202, port 204, port 206; The output port of the temporary module of input information is port 203, port 205; Port 201 is eight bit parallel ports, with eight buses corresponding being connected one by one of the port one 10 of microprocessor, for receiving the checking solicited message A[7:0 of input]; Port 202 is connected with the port one 11 of microprocessor, for receive clock 1; Port 204 is connected with the port 212 of invading detection module, for receiving signal mode control; Port 203 is connected with two ports 213 of invading detection module, for output system clock; Port 205 is connected with the port 211 of invading detection module, for sending input message F to invading detection module; The temporary module of input information is 1 by a width, the push-up storage that the degree of depth is 512, and 1 MUX, 1 parallel-serial converter, one and string signal maker, a system clock maker forms; The input end of system clock maker is the clock 1 that port 202 is inputted, the clock 2 that port 206 is inputted, and the pattern control that port 204 is inputted, is output as the system clock that port 203 is exported; When the pattern control of inputting when port 204 is high level, the clock 1 that port 202 is inputted is exported and as system clock from port 203, when the pattern control of inputting when port 204 is low level, the clock 2 that port 206 is inputted is exported and as system clock from port 203; And string signal maker is made up of one two input and door and mould 9 counters 1; With the input end of door be two signals of pattern control that the clock 1 inputted of port 202 and port 204 are inputted, with the output terminal of the door clock trigger end as mould 9 counters 1; Mould 9 counters 1 count value be 9 o'clock output signals also-string switching signal is high level, when its remainder values, also-string switching signal is low level; When system clock rising edge that parallel-serial converter is exported at port 203, and also-string switching signal is while being high level, is written into the parallel data fake certification information A[7:0 that port 201 is inputted], otherwise serial output data is to an input end of MUX; When the pattern control that MUX is inputted at port 204 is high level, the output valve of output parallel-serial converter is to the output terminal of push-up storage, when the pattern control of inputting at port 204 is low level, output anti-counterfeiting information E1 is to the output terminal of push-up storage; Push-up storage is made up of 512 d type flip flops, and data input pin and the data output end of 512 triggers join end to end, and data output end is the input message F that port 205 is exported.
The chip that the present invention proposes, wherein, the input port that information is read in module is 224,223; The output port that information is read in module is 222; Port 224 is connected with the port one 15 of microprocessor, for receiving the anti-counterfeiting information L[7:0 of disposable programmable read only memory output]; Port 223 is connected with the port 215 of invading detection module, for receiving system clock; Port 222 is connected with the port 216 of invading detection module, for exporting anti-counterfeiting information H to invading detection module; It is 8 by a width that information is read in module, and the degree of depth is 1 also-and string transition trigger device group and mould 9 counters 2 form; Under system clock rising edge that mould 9 counters 2 are inputted at port 223 triggers counting output signal also-string switching signal 1; Be that 9 o'clock also-string switching signals 1 are high level in count value, when its remainder values, also-string switching signal 1 is low level; When system clock rising edge that parallel-serial converter is inputted at port 223, and when also-string switching signal 1 is high level, be written into the anti-counterfeiting information L[7:0 that parallel data port 224 is inputted], otherwise serial output data to port 222 is invaded detection module as anti-counterfeiting information H output valve.
The chip that the present invention proposes, wherein, the input port that information is write out module is port 225, port 226; The output port that information is write out module is port one 13; Port 225 is connected with the port 219 of invading detection module, for receiving the anti-counterfeiting information I writing; Port 226 is connected with the port 218 of invading detection module, for receiving system clock; Port 227 is connected with the port one 13 of microprocessor, for exporting the anti-counterfeiting information J[7:0 writing]; It is 8 by a width that information is write out module, string that the degree of depth is 1-and transition trigger device group form; This string-and the input end of transition trigger device be the anti-counterfeiting information I writing that port 225 is inputted, the system clock rising edge of inputting at port 226 trigger under, export by port 227 the anti-counterfeiting information J[7:0 that parallel data writes].
The chip that the present invention proposes, wherein, the input port of message output module is 209,236; The output port of message output module is 208; Port 209 is connected with the port 214 of invading detection module, for receiving anti-counterfeiting information G to be exported; Port 208 is connected with the port one 12 of microprocessor, for sending output anti-counterfeiting information B[7:0]; Port 236 is connected with the port 203 of the temporary module of input information, for receiving system clock; Message output module is 8 by a width, string that the degree of depth is 1-and transition trigger device group form; This string-and the input end of transition trigger device be the anti-counterfeiting information G to be exported that port 209 receives, the system clock rising edge of inputting at port 236 trigger under, export parallel output anti-counterfeiting information B[7:0 by port 208].
The chip that the present invention proposes, wherein, the input port of invading detection module is port 211, port 213, port 216, port 220, port 221; The output port of invading detection module is port 212, port 214, port 215, port 217, port 218, port 219; Input port 213 and output port 215, port 218 is direct-connected, port 215, port 218 is for direct output system clock; Input port 216 is connected with output port 214, for anti-counterfeiting information H being directly sent to the input port 209 of message output module; The output port 114 of port 217 and microprocessor is connected, for to disposable programmable read only memory OPADD Addr[10:0]; Invade detection module by forming as lower module, mode control signal maker, address generation module, anti-counterfeiting information programming module.
The chip that the present invention proposes, wherein, mode control signal maker is by three d type flip flops, and the rejection gate of one three input one output forms; Joining end to end of three d type flip flops, input end is the Authority Verification information D1 that port 220 is inputted; The clock end of three d type flip flops is all connected with clock 2; The output terminal of a three d type flip flops respectively input end of AND OR NOT gate is connected; The output terminal of rejection gate is the pattern control that port 212 is exported.
The chip that the present invention proposes, wherein, address generation module forms with door and address generator by one; Address generator is counting under triggering with the rising edge of door output, and count value is as the address Addr[10:0 of 11] export by port 217.
The chip that the present invention proposes, wherein, anti-counterfeiting information programming module is 1 by two width, the push-up storage that the degree of depth is 512, XOR gate, two and door, mould 1024 frequency dividers, a d type flip flop, a CRC maker composition; Push-up storage 1 is made up of 512 d type flip flops, data input pin and the data output end of 512 triggers join end to end, push-up storage 1 data output end is the Authority Verification information D1 that port 220 is inputted, and input end of data output end and XOR gate is connected; The clock end of push-up storage 1 is the system clock that port 213 is inputted; Push-up storage 2 is made up of 512 d type flip flops, and data input pin and the data output end of 512 triggers join end to end, and push-up storage 2 data output ends are the check code of CRC maker output, and input end of output terminal and XOR gate is connected; The clock end of push-up storage 2 is the system clock that port 213 is inputted; The system clock that mould 1024 frequency dividers are inputted port 213 carries out frequency division, and divide ratio is 1024, output terminal be connected with an input end of door 1; The system clock that mould 1024 frequency dividers are inputted port 213 carries out frequency division; The output terminal of XOR gate be connected with another output terminal of door 1; Be connected with the output terminal of door 1 and the clock end of d type flip flop; The data terminal of d type flip flop is connected with power supply, the oppisite phase data end of d type flip flop be connected with the data input pin of door 2; The input message F that port 211 is inputted is connected with another data input pin of door 2; Be the anti-counterfeiting information I writing and export by port 219 with the data output end of door 2.
The chip that the present invention proposes, wherein, microprocessor has writing information pattern, and two mode of operations of information contrastive pattern, by the mode of operation of invading control module control microprocessor.
The chip that the present invention proposes, wherein, special Flash-writer, under clock 2 synchronous, writes initialization anti-counterfeiting information E in serial communication controller 2 by port one 24, and serial communication controller 2 is according to I 2initialization anti-counterfeiting information E is reverted to anti-counterfeiting information E1 by C bus protocol, and anti-counterfeiting information E1 is sent into information temporary storage module; Special Flash-writer, under clock 2 synchronous, writes initialization Authority Verification information D in serial communication controller 1 by port one 22, and serial communication controller 1 is according to I 2initialization Authority Verification information D is reverted to serial data Authority Verification information D1 by C bus protocol, and Authority Verification information D1 is sent into intrusion detection module; Invade detection module after detecting that Authority Verification information D1 is legal information, the anti-counterfeiting information I writing is sent into information and write out module; Information write out module under the triggering of system clock by the anti-counterfeiting information J[7:0 writing] write disposable programmable read only memory; Disposable programmable read only memory is at address Addr[10:0] control under by the anti-counterfeiting information J[7:0 writing] write assigned address.
The chip that the present invention proposes, wherein, mobile phone by common interface module under clock 1 synchronous, by the fake certification information A[7:0 of input] send into the temporary module of input information; Under the rising edge of system clock and input message F phase and signal triggers, invade detection module calculated address Addr[10:0] send into disposable programmable read only memory; Information is read in module and is read in the anti-counterfeiting information L[7:0 that disposable programmable read only memory is exported]; The anti-counterfeiting information H that intrusion detection module reads in information in module directly sends into message output module as anti-counterfeiting information G to be exported; Last under the triggering of clock, message output module will be exported anti-counterfeiting information B[7:0] send to mobile phone by common interface module.
The chip that the present invention proposes, wherein, described chip is fixed on article surface, the anti-counterfeiting information of storing in described internal storage is for identifying described article, described anti-counterfeiting information is associated with the information of the same printing labeling that is fixed on article surface, on described printing labeling, be printed with two-dimensional bar and the ordinary numbers security code of traceable identify objects, described two-dimensional bar, ordinary numbers security code and corresponding anti-counterfeiting information are generated by item information data storehouse server, described anti-counterfeiting information is write in described chip, and the relevant information of described article is arrived to central database server by Internet Transmission, described central database server is connected with item information data storehouse server by network, stores the relevant information of described article, receives the anti-counterfeiting information being sent by mobile phone and the authorization information of respective articles is sent to mobile phone.
The chip that the present invention proposes, wherein, in the internal storage of described chip, also store item tracing information, described item tracing information is write by special chip read write line separately by transfer website, wherein each transfer website has corresponding numbering and binds with special chip read write line separately, the described terminal data relevant to described tracked information of naming a person for a particular job are sent to central database server in real time, and upgrade on the server of item information data storehouse, terminal user uses mobile phone to send described anti-counterfeiting information to central database server, and obtain from the central database the tracked information of respective articles in server.
The chip that the present invention proposes, wherein, terminal user downloads reading software on center service database, read the described anti-counterfeiting information of chip-stored by mobile phone, and by internet, described anti-counterfeiting information is sent to central database server, determine the true and false of article or obtain tracking and the production information of these article.
The chip that the present invention proposes, wherein, mobile phone also can obtain two-dimensional bar or the ordinary numbers security code on printed label surface, and the relevant information getting is compared by the information in internet and central database server, determine the true and false of article and obtain tracking and the production information of these article; Or by the relevant information getting with compare from the anti-counterfeiting information obtaining in chip by common interface module, intersect comparison to realize.
The chip that the present invention proposes, wherein, terminal user is at inquiry commodity true and false or obtain and follow the trail of and when production information, and the short message prompt terminal user prompting of deducting fees, after successful query-related information, withholds relevant inquiring expense by communication operator.
The chip that the present invention proposes, wherein, described ordinary numbers security code is generated by computing machine, and is transformed and generated corresponding two-dimensional bar by digital anti-counterfeiting code.
Brief description of the drawings
Fig. 1 is the inner structure of the chip that proposes of the present invention and the interface schematic diagram with special chip read write line, mobile phone;
Fig. 2 is the schematic diagram of microprocessor module;
Fig. 3 is the schematic diagram of the temporary module of input information in microprocessor module;
Fig. 4 is the schematic diagram that in microprocessor module, information is read in module;
Fig. 5 is the schematic diagram that in microprocessor module, information is write out module;
Fig. 6 is the schematic diagram of message output module in microprocessor module;
Fig. 7 is the schematic diagram of invading detection module in microprocessor module;
Fig. 8 is the schematic diagram that utilizes chip identification article to follow the trail of to realize orientation;
Fig. 9 is the schematic diagram of generating chip and printing labeling;
Figure 10 is the schematic diagram of terminal dot generation item tracing information;
Chip and printing labeling are fixed on the schematic diagram of body surface by Figure 11.
Embodiment
The following stated is better embodiment of the present invention, does not therefore limit protection scope of the present invention.
Fig. 1 is the internal structure of the chip that proposes of the present invention and the interface schematic diagram with special chip read write line, mobile phone.As shown in Figure 1, the chip for identify objects that the present invention proposes comprises three parts, be respectively microprocessor, common interface module and internal storage, this common interface module supports the various types of signal such as GSM to realize and the communicating by letter of mobile phone, this internal storage can be disposable programmable read only memory OTP ROM), wherein, support the common interface module of the various types of signal such as GSM for realizing mutual with mobile phone, particularly, this common interface module receives the checking solicited message of mobile phone transmission and transfers to microprocessor processes, receive the anti-counterfeiting information of microprocessor transmission and send this anti-counterfeiting information to mobile phone, microprocessor is used for receiving the checking solicited message that comes from common interface module, and based on this checking solicited message, reads anti-counterfeiting information from disposable programmable read only memory, and this anti-counterfeiting information is sent to common interface module, disposable programmable read only memory is stored described anti-counterfeiting information.Microprocessor also can be realized and communicating by letter with special chip read write line, and particularly, microprocessor receives and comes from the initialization anti-counterfeiting information of special chip read write line, and writes anti-counterfeiting information in disposable programmable read only memory.The inner structure of described chip will be introduced particularly hereinafter.
Support the input port of the common interface module of the various types of signal such as GSM to have 104,105,109; Support the output port of the common interface module of the various types of signal such as GSM to have 106,107,108; Port one 04 is set up communication with outside port one 01 and is connected, for transmitting checking request A1[7:0], port one 05 is set up communication with outside port one 02 and is connected, for receive clock 1; Port one 06 is set up communication with outside port one 03 and is connected, for send outside anti-counterfeiting information B1[7:0 to outside]; Port one 07 is connected with the port one 10 of microprocessor, for transmitting the checking solicited message A[7:0 of input]; Port one 08 is connected with the port one 11 of microprocessor, for clock 1 is sent into microprocessor; Port one 09 is connected with the port one 12 of microprocessor, the output anti-counterfeiting information B[7:0 sending for receiving microprocessor].
Disposable programmable read only memory input port has 116,117; Output port is 118; Input port 116 is connected with the port one 13 of microprocessor, by the anti-counterfeiting information J[7:0 writing] write in disposable programmable read only memory, the region to be written of disposable programmable read only memory can only be written into primary information under the control of microprocessor, and information can not be modified thereafter; If want supplement information,, under the control of microprocessor, supplement information is write to other regions to be written of disposable programmable read only memory; Region to be written, once being written into information, cannot be revised; The area size to be written of disposable programmable read only memory is determined by the memory capacity of disposable programmable read only memory; Input port 117 is connected with the port one 14 of microprocessor, for by address Addr[10:0] send into the address end of disposable programmable read only memory; Output port 118 is connected with the port one 15 of microprocessor, for by address Addr[10:0] the anti-counterfeiting information L[7:0 that specifies] send into microprocessor.
The input port of microprocessor is 110,111,115,122,123,124; The output port of microprocessor is 112,113,114; The port one 19 of input port 122 and outside special chip read write line is connected, for receiving initialization Authority Verification information D; The port one 20 of port one 23 and special chip read write line is connected, for receive clock 2; The port one 21 of port one 24 and special chip read write line is connected, for receiving initialization anti-counterfeiting information E; The communication mode of initialization anti-counterfeiting information E is serial communication, and communication protocol meets I 2c bus protocol; Line between port one 21 and port one 24 is as I 2the data line SDA of C bus; Line between port one 20 and port one 23 is I 2the clock SCL of C bus; The communication mode of initialization Authority Verification information D is serial communication, and communication protocol meets I 2c bus protocol; Line between port one 19 and port one 22 is as I 2the data line SDA of C bus; Line between port one 20 and port one 23 is I 2the clock SCL of C bus; The content of initialization Authority Verification information D is 512 Authority Verification codes, 512 Authority Verification check codes, and 512 authorization codes, authorize check code for 512.
512 its verification modes of Authority Verification check code are 512 Authority Verification codes to be divided into the message block of 8 groups 64, are respectively D0[63:0], D1[63:0], D2[63:0] and, D3[63:0], D4[63:0] and, D5[63:0], D6[63:0] and, D7[63:0]; Taking D0[63:0] be example, 64 message block D0[63:0] adopt CRC-32 to generate 32 Cyclic Redundancy Code C0[31:0], generator polynomial brief note formula is 04C11DB7 or other feasible generator polynomials, message block D0[0:63] adopting CRC-32 to generate 32 Cyclic Redundancy Code C0[63:32], generator polynomial brief note formula is 1EDC6F41 or other feasible generator polynomials, finally composition check code be C0[63:0], C1[63:0], C2[63:0], C3[63:0], C4[63:0], C5[63:0], C6[63:0], C7[63:0] be 512 Authority Verification check codes.
512 are authorized its verification mode of check code is 512 authorization codes to be divided into the message block of 8 groups 64, is respectively D10[63:0], D11[63:0], D12[63:0] and, D13[63:0], D14[63:0] and, D15[63:0], D16[63:0] and, D17[63:0], taking D10[63:0] be example, 64 message block D10[63:0] adopt CRC-32 to generate 32 Cyclic Redundancy Code C10[31:0], generator polynomial brief note formula is 04C11DB7 or other feasible generator polynomials, message block D10[0:63] adopting CRC-32 to generate 32 Cyclic Redundancy Code C10[63:32], generator polynomial brief note formula is 1EDC6F41 or other feasible generator polynomials, finally composition check code be C10[63:0], C11[63:0], C12[63:0], C13[63:0], C14[63:0], C15[63:0], C16[63:0], C17[63:0] } be 512 mandate check codes.
Fig. 2 is the schematic diagram of microprocessor module.As shown in Figure 2, microprocessor module comprises serial communication controller 1, serial communication controller 2, and input information is kept in module, invades detection module, and information is read in module, and information is write out module and message output module.Fig. 3 is the schematic diagram of the temporary module of input information in microprocessor module; Fig. 4 is the schematic diagram that in microprocessor module, information is read in module; Fig. 5 is the schematic diagram that in microprocessor module, information is write out module; Fig. 6 is the schematic diagram of message output module in microprocessor module; Fig. 7 is the schematic diagram of invading detection module in microprocessor module.Below, with reference to figure 2-Fig. 7, microprocessor module and all modules thereof are described.
Serial communication controller 1 and serial communication controller 2 meet I 2c bus communication protocol; The input port of serial communication controller 1 is 230,231; Serial communication controller 1 output port is 228,229; Port 230 is connected with the port one 22 of microprocessor, for receiving initialization authority information D; Port 231 is connected with microprocessor port one 23, for receive clock 2; Port 229 with invade the port 220 of detection module and be connected, for sending permission authorization information D1 to the port 220 of invading detection module; Port 228 is connected with the port 221 of invading detection module, and port 228 and port 231 are direct-connected, and therefore port 228 is sent to clock 2 port 221 of invading detection module; The input port of serial communication controller 2 is 234,235; Serial communication controller 2 output ports are 232,233; Port 235 is connected with the port one 24 of microprocessor, for receiving initialization anti-counterfeiting information E; Port 234 is connected with microprocessor port one 23, for receive clock 2; Port 232 is connected with the port 207 of the temporary module of input information, for sending the port 207 of anti-counterfeiting information E1 to the temporary module of input information; Port 233 is connected with the port 206 of the temporary module of input information, and port 233 and port 234 are direct-connected, and therefore port 233 is sent to clock 2 port 206 of the temporary module of input information.
The input port of the temporary module of input information is 201,202,204,206; The output port of the temporary module of input information is 203,205; Port 201 is eight bit parallel ports, with eight buses corresponding being connected one by one of the port one 10 of microprocessor, for receiving the checking solicited message A[7:0 of input]; Port 202 is connected with the port one 11 of microprocessor, for receive clock 1; Port 204 is connected with the port 212 of invading detection module, for receiving signal mode control; Port 203 is connected with two ports 213 of invading detection module, for output system clock; Port 205 is connected with the port 211 of invading detection module, for sending input message F to invading detection module.The temporary module of input information is 1 by a width, the push-up storage that the degree of depth is 512, and 1 MUX, 1 parallel-serial converter, one and string signal maker, a system clock maker forms; The input end of system clock maker is the clock 1 that port 202 is inputted, the clock 2 that port 206 is inputted, and the pattern control that port 204 is inputted, is output as the system clock that port 203 is exported; When the pattern control of inputting when port 204 is high level, the clock 1 that port 202 is inputted is exported and as system clock from port 203, when the pattern control of inputting when port 204 is low level, the clock 2 that port 206 is inputted is exported and as system clock from port 203; And string signal maker is made up of one two input and door and mould 9 counters 1; With the input end of door be two signals of pattern control that the clock 1 inputted of port 202 and port 204 are inputted, with the output terminal of the door clock trigger end as mould 9 counters 1; Mould 9 counters 1 count value be 9 o'clock output signals also-string switching signal is high level, when its remainder values, also-string switching signal is low level; When system clock rising edge that parallel-serial converter is exported at port 203, and also-string switching signal is while being high level, is written into the parallel data fake certification information A[7:0 that port 201 is inputted], otherwise serial output data is to an input end of MUX; When the pattern control that MUX is inputted at port 204 is high level, the output valve of output parallel-serial converter is to the output terminal of push-up storage, when the pattern control of inputting at port 204 is low level, output anti-counterfeiting information E1 is to the output terminal of push-up storage; Push-up storage is made up of 512 d type flip flops, and data input pin and the data output end of 512 triggers join end to end, and data output end is the input message F that port 205 is exported.
The input port that information is read in module is 224,223; The output port that information is read in module is 222; Port 224 is connected with the port one 15 of microprocessor, for receiving the anti-counterfeiting information L[7:0 of disposable programmable read only memory output]; Port 223 is connected with the port 215 of invading detection module, for receiving system clock; Port 222 is connected with the port 216 of invading detection module, for exporting anti-counterfeiting information H to invading detection module; It is 8 by a width that information is read in module, and the degree of depth is 1 also-and string transition trigger device group and mould 9 counters 2 form; Under system clock rising edge that mould 9 counters 2 are inputted at port 223 triggers counting output signal also-string switching signal 1; Be that 9 o'clock also-string switching signals 1 are high level in count value, when its remainder values, also-string switching signal 1 is low level; When system clock rising edge that parallel-serial converter is inputted at port 223, and when also-string switching signal 1 is high level, be written into the anti-counterfeiting information L[7:0 that parallel data port 224 is inputted], otherwise serial output data to port 222 is invaded detection module as anti-counterfeiting information H output valve.
The input port that information is write out module is 225,226; The output port that information is write out module is 113; Port 225 is connected with the port 219 of invading detection module, for receiving the anti-counterfeiting information I writing; Port 226 is connected with the port 218 of invading detection module, for receiving system clock; Port 227 is connected with the port one 13 of microprocessor, for exporting the anti-counterfeiting information J[7:0 writing]; It is 8 by a width that information is write out module, string that the degree of depth is 1-and transition trigger device group form; This string-and the input end of transition trigger device be the anti-counterfeiting information I writing that port 225 is inputted, the system clock rising edge of inputting at port 226 trigger under, export by port 227 the anti-counterfeiting information J[7:0 that parallel data writes].
The input port of message output module is 209,236; The output port of message output module is 208; Port 209 is connected with the port 214 of invading detection module, for receiving anti-counterfeiting information G to be exported; Port 208 is connected with the port one 12 of microprocessor, for sending output anti-counterfeiting information B[7:0]; Port 236 is connected with the port 203 of the temporary module of input information, for receiving system clock; Message output module is 8 by a width, string that the degree of depth is 1-and transition trigger device group form; This string-and the input end of transition trigger device be the anti-counterfeiting information G to be exported that port 209 receives, the system clock rising edge of inputting at port 236 trigger under, export parallel output anti-counterfeiting information B[7:0 by port 208].
The input port of invading detection module is 211,213,216,220,221; The output port of invading detection module is 212,214,215,217,218,219; Input port 213 is direct-connected with output port 215,218, and port 215,218 is for direct output system clock; Input port 216 is connected with output port 214, for anti-counterfeiting information H being directly sent to the input port 209 of message output module; The output port 114 of port 217 and microprocessor is connected, for to disposable programmable read only memory OPADD Addr[10:0].Invade detection module and comprise mode control signal maker, address generation module, anti-counterfeiting information programming module.
Mode control signal maker is by three d type flip flops, and the rejection gate of one three input one output forms; Joining end to end of three d type flip flops, input end is the Authority Verification information D1 that port 220 is inputted; The clock end of three d type flip flops is all connected with clock 2; The output terminal of a three d type flip flops respectively input end of AND OR NOT gate is connected; The output terminal of rejection gate is the pattern control that port 212 is exported.
Address generation module forms with door and address generator by one; Address generator is counting under triggering with the rising edge of door output, and count value is as the address Addr[10:0 of 11] export by port 217.
Anti-counterfeiting information programming module is 1 by two width, the push-up storage that the degree of depth is 512, XOR gate, two and door, mould 1024 frequency dividers, a d type flip flop, a CRC maker composition; Push-up storage 1 is made up of 512 d type flip flops, data input pin and the data output end of 512 triggers join end to end, push-up storage 1 data output end is the Authority Verification information D1 that port 220 is inputted, and input end of data output end and XOR gate is connected; The clock end of push-up storage 1 is the system clock that port 213 is inputted; Push-up storage 2 is made up of 512 d type flip flops, and data input pin and the data output end of 512 triggers join end to end, and push-up storage 2 data output ends are the check code of CRC maker output, and input end of output terminal and XOR gate is connected; The clock end of push-up storage 2 is the system clock that port 213 is inputted; The system clock that mould 1024 frequency dividers are inputted port 213 carries out frequency division, and divide ratio is 1024, output terminal be connected with an input end of door 1; The system clock that mould 1024 frequency dividers are inputted port 213 carries out frequency division; The output terminal of XOR gate be connected with another output terminal of door 1; Be connected with the output terminal of door 1 and the clock end of d type flip flop; The data terminal of d type flip flop is connected with power supply, the oppisite phase data end of d type flip flop be connected with the data input pin of door 2; The input message F that port 211 is inputted is connected with another data input pin of door 2; Be the anti-counterfeiting information I writing and export by port 219 with the data output end of door 2.
Microprocessor has writing information pattern, and two mode of operations of information contrastive pattern, by the mode of operation of invading control module control microprocessor.
Special Flash-writer, under clock 2 synchronous, writes initialization anti-counterfeiting information E in serial communication controller 2 by port one 24, and serial communication controller 2 is according to I 2initialization anti-counterfeiting information E is reverted to anti-counterfeiting information E1 by C bus protocol, and anti-counterfeiting information E1 is sent into information temporary storage module; Special Flash-writer, under clock 2 synchronous, writes initialization Authority Verification information D in serial communication controller 1 by port one 22, and serial communication controller 1 is according to I 2initialization Authority Verification information D is reverted to serial data Authority Verification information D1 by C bus protocol, and Authority Verification information D1 is sent into intrusion detection module; Invade detection module after detecting that Authority Verification information D1 is legal information, the anti-counterfeiting information I writing is sent into information and write out module; Information write out module under the triggering of system clock by the anti-counterfeiting information J[7:0 writing] write disposable programmable read only memory; Disposable programmable read only memory is at address Addr[10:0] control under by the anti-counterfeiting information J[7:0 writing] write assigned address.
The general-purpose interface of mobile phone by supporting the various types of signal such as GSM is under clock 1 synchronous, by the checking solicited message A[7:0 of input] send into the temporary module of input information; Under the rising edge of system clock and input message F phase and signal triggers, invade detection module calculated address Addr[10:0] send into disposable programmable read only memory; Information is read in module and is read in the anti-counterfeiting information L[7:0 that disposable programmable read only memory is exported]; The anti-counterfeiting information H that intrusion detection module reads in information in module directly sends into message output module as anti-counterfeiting information G to be exported; Last under the triggering of clock, message output module will be exported anti-counterfeiting information B[7:0] send to mobile phone by common interface module.
Fig. 8 is the schematic diagram that utilizes chip identification article to follow the trail of to realize orientation.From description above, mobile phone can read the anti-counterfeiting information of storing in disposable programmable read only memory in chip by described common interface module, in Fig. 8, this azimuth information is called to article identification information, for article are identified, described article identification information comprises identification information, and described chip is fixed on to article surface, and on its internal storage, canned data is associated with the information of printing labeling; The two-dimensional bar and the ordinary numbers security code that on printing labeling, comprise traceable identify objects, ordinary numbers security code is generated by computing machine, and is transformed and generated corresponding two-dimensional bar by digital anti-counterfeiting code, is printed in labeling surface; Item information data storehouse server generates described two-dimensional bar, ordinary numbers security code and corresponding article identification information, and in the process of production printing labeling and chip, two-dimensional bar, ordinary numbers security code are printed in to labeling surface, article identification information is write to chip internal, concrete ablation process as described above, is transferred to the relevant information of described article in central database server by computer network simultaneously; Central database server is stored the relevant information of described article, is connected with item information data storehouse server by network, stores the relevant information of described article, receives the identification information being sent by mobile phone and the authorization information of respective articles is sent to mobile phone; Mobile phone is connected with chip by common interface module, reads the article identification information of preserving in internal storage in chip.
Fig. 9 is the schematic diagram of generating chip and printing labeling.As shown in Figure 9, item information data storehouse server writes article identification information in the storer of described chip by special chip read write line, and print printing labeling, meanwhile, the information exchange relevant to article crossed to computer network and transfer to central database server.
Figure 10 is the schematic diagram of terminal dot generation item tracing information.As shown in figure 10, transfer website writes item tracing information by special chip read write line, each transfer website has corresponding numbering also and the binding of special chip read write line, the terminal data relevant to described tracked information of naming a person for a particular job are sent to central database server in real time, and upgrade on the server of item information data storehouse.
Terminal user can be in central database server download terminal software, by mobile phone read write tag, and relevant information is compared by the information of internet and central database, determine the true and false of article and tracking, production information; Can also select to determine by printing labeling the true and false and the tracked information of article, terminal user is by the mobile phone with camera, read the two-dimensional bar on printed label surface, and relevant information is compared by internet and central database, determine the true and false of article and tracking, production information.
Terminal user is in the time of inquiry commodity true and false and tracking, production information, and the short message prompt terminal user prompting of deducting fees, after successful query-related information, withholds relevant inquiring expense by communication operator.
Chip and printing labeling are fixed on the schematic diagram of body surface by Figure 11.As shown in figure 11, can be by chip the form with trade mark or bottle cap, be fixed on article surface; Also the printing labeling relevant to chip stored information can be fixed on to body surface in the lump.User can read out the storage information in chip tag by mobile phone, and connect central server by network, obtaining information the comparison of corresponding sequence number commodity tells truth from falsehood,, article mark information in chip tag is sent to central database, and whether central database returns according to the identification information of these article is true and false product; User can carry out authenticity verification and tracking and managing by Quick Response Code and the digital anti-counterfeiting code on printing labeling surface simultaneously.
In the specific implementation, can, according to user's request, chip package, within bottle cap, be stamped to information reserved Quick Response Code print area and the digital anti-counterfeiting code printing region of these article simultaneously on printing labeling; PC is according to the numbering of these article, production time, the term of validity, packaged form etc., calculate the digital anti-counterfeiting code of these article by software, and generate corresponding two-dimensional bar according to this digital anti-counterfeiting code, be printed to the assigned address of printing labeling, and paste on appointment article; Generating after printing labeling, according to corresponding information, generating chip writing information, utilize proprietary application software to be encrypted associated calculation process to the Quick Response Code data, digital anti-counterfeiting code data, Item Number, lot number, production time, the term of validity that gather, and cleartext information is converted into cipher-text information, by special chip read write line, corresponding information is write to appointment chip, and the bottle cap that comprises this chip is fixed on article; When article warehouse-ins and outbound, by read-and-write device, easily statistics put in storage, the information such as the kind of outbound article, quantity, time, handler, and deposit these information in database, for the use of data examination; Article enter after transfer website, and the flow direction of these article is understood and monitored to the information that the manufacturer of these article can upload by each transfer website in time; The transfer websites at different levels of these article can be by access central database server, and the relevant information of inquiring about these article also can write according to individual demand the information of transfer website, to enrich the tracked information of these article in RFID label; User inquires about the true and false, date of expiration and other relevant informations of product by access central database server, thereby meets well user's right to know, and differentiates the true and false of these article.
Traditional anti-counterfeit tracking method based on RFID radio-frequency (RF) identification, must be used specialized equipment, is not easy to end user query and use, uses the chip for identify objects of the present invention fundamentally to solve this problem.The mobile phone that terminal user only need have the general-purpose interface that possesses the various types of signal such as support GSM can carry out true-false inquiring and commodity circulation information, and the mobile phone that does not partly possess the general-purpose interface of supporting the various types of signal such as GSM can carry out two-dimension code anti-counterfeit identification XOR digital anti-counterfeiting code by printing labeling and identify.Therefore, use chip of the present invention, there is very strong extensibility and compatibility, can realize the mutual of data message and share, and the function that article genuine-fake is differentiated and article are followed the trail of is provided, thereby, this chip can be used for manufacturer to production products in circulation, sell the monitoring of links and the buyer of this product distinguishing this authenticity of products, in central database server, comprise label generation module, logistics and storage module, enquiry module; In the server of item information data storehouse, comprise logistics and storage module, enquiry module, production management module; Transfer website can be product distribution business or transfer business; At this moment, use chip of the present invention, can facilitate Inner Logistics Management; Based on chip identification article, realize materials circulation automatic management; Retail trader or terminal have the right chip to append operation, can inquire easily the circulation status of article, prevent to go here and there the risk of goods simultaneously.Terminal user can support by mobile phone the general-purpose interface of the various types of signal such as GSM, carrying out chip read-write sets, this general-purpose interface with in chip, support that the common interface module of the various types of signal such as GSM mates, the various types of signal that those skilled in the art can select the common interface module in chip to support according to mobile phone kind, here GSM signal is just as example, not as limitation of the present invention; Or carry out Quick Response Code or the identification of digital anti-counterfeiting code by SMS platform by printing paster.Therefore, concerning user, this chip is convenient and simple, and terminal user does not produce any cost.Simultaneously; the chip that the present invention proposes can pass through portable battery or solar cell or external electromagnetic energy to chip power supply; but these concrete power supply modes are not as the restriction to the application's protection domain; to those skilled in the art, can use the power supply of any existing techniques in realizing chip.
Should note; embodiment proposed by the invention and application be the object for illustrating only; not as limiting the scope of the invention, those skilled in the art can modify and be applied in the various practical applications of certain article being carried out to anti-counterfeit recognition or tracking the specific embodiment of the present invention.

Claims (26)

  1. For identify objects to realize a chip for anti-counterfeit tracking, it is characterized in that:
    Described chip comprises microprocessor, common interface module and internal storage, and described common interface module is connected with described microprocessor, and described microprocessor is connected with described internal storage;
    Described common interface module receives the checking solicited message that mobile phone sends, and this checking solicited message is transferred to microprocessor processes, receives the anti-counterfeiting information of microprocessor transmission and sends this anti-counterfeiting information to mobile phone;
    Described microprocessor receives the checking solicited message that comes from described common interface module, based on this checking solicited message, reads described anti-counterfeiting information from described internal storage, and described anti-counterfeiting information is sent to common interface module;
    Described internal storage is stored described anti-counterfeiting information; And,
    Described microprocessor comprises that serial communication controller 1, serial communication controller 2, the temporary module of input information, intrusion detection module, information are read in module, information is write out module and message output module; Wherein:
    Described serial communication controller 1 is for receiving Authority Verification information, and exports Authority Verification information to invading detection module;
    Described serial communication controller 2 is for receiving described anti-counterfeiting information, and exports described anti-counterfeiting information to the temporary module of described input information;
    Described intrusion detection module is for controlling the mode of operation of microprocessor, and described mode of operation is writing information pattern and information contrastive pattern;
    The temporary module of described input information is used for receiving described anti-counterfeiting information, also for receiving the described checking solicited message of input, and in the time that microprocessor is writing information pattern, described anti-counterfeiting information is inputed to intrusion detection module, and in the time that microprocessor is information contrastive pattern, described checking solicited message is inputed to intrusion detection module;
    Described intrusion detection module is used under writing information pattern when detecting that exporting anti-counterfeiting information to information after Authority Verification information is legal information writes out module to write internal storage, also under information contrastive pattern, checking solicited message being sent into described internal storage, and information is read in to the anti-counterfeiting information that module reads in send into message output module to send to mobile phone by common interface module.
  2. 2. chip according to claim 1, is characterized in that:
    Described common interface module supports GSM signal to communicate with mobile phone, and described internal storage is disposable programmable read only memory OTP ROM.
  3. 3. chip according to claim 2, is characterized in that:
    Described microprocessor also receives the initialization anti-counterfeiting information that comes from special chip read write line, and writes anti-counterfeiting information in described internal storage.
  4. 4. chip according to claim 2, is characterized in that: the input port of described common interface module is the 104th port, the 105th port and the 109th port; Output port is the 106th port, the 107th port and the 108th port; The 104th port is set up communication with the 101st outside port and is connected, for transmitting checking solicited message A1[7:0], the 105th port is set up communication with the 102nd outside port and is connected, for receive clock 1; The 106th port is set up communication with the 103rd outside port and is connected, for send outside anti-counterfeiting information B1[7:0 to outside]; The 107th port is connected with the 110th port of microprocessor, for transmitting the checking solicited message A[7:0 of input]; The 108th port is connected with the 11.1st port of microprocessor, for clock 1 is sent into microprocessor; The 109th port is connected with the 112nd port of microprocessor, the output anti-counterfeiting information B[7:0 sending for receiving microprocessor].
  5. 5. chip according to claim 2, is characterized in that: described disposable programmable read only memory input port has the 116th port and the 117th port; Output port is the 118th port; The 116th port is connected with the 113rd port of microprocessor, by the anti-counterfeiting information J[7:0 writing] write in disposable programmable read only memory, the region to be written of disposable programmable read only memory can only be written into primary information under the control of microprocessor, and information can not be modified thereafter; If want supplement information,, under the control of microprocessor, supplement information is write to other regions to be written of disposable programmable read only memory; Region to be written, once being written into information, cannot be revised; The area size to be written of disposable programmable read only memory is determined by the memory capacity of disposable programmable read only memory; The 117th port is connected with the 114th port of microprocessor, for by address Addr[10:0] send into the address end of disposable programmable read only memory; The 118th port is connected with the 115th port of microprocessor, for by address Addr[10:0] the anti-counterfeiting information L[7:0 that specifies] send into microprocessor.
  6. 6. chip according to claim 3, is characterized in that: the input port of microprocessor is the 110th port, the 111st port, the 115th port, the 122nd port, the 123rd port and the 124th port; The input port of microprocessor is the 112nd port, the 113rd port and the 114th port; The 119th port of the 122nd port and outside special chip read write line is connected, for receiving initialization Authority Verification information D; The 120th port of the 123rd port and special chip read write line is connected, for receive clock 2; The 121st port of the 124th port and special chip read write line is connected, for receiving initialization anti-counterfeiting information E.
  7. 7. chip according to claim 6, is characterized in that: the communication mode of described initialization anti-counterfeiting information E is serial communication, and communication protocol meets I2C bus protocol; Line between the 121st port and the 124th port is as the data line SDA of I2C bus; Line between the 120th port and the 123rd port is the clock SCL of I2C bus; The communication mode of initialization Authority Verification information D is serial communication, and communication protocol meets I2C bus protocol; Line between the 119th port and the 122nd port is as the data line SDA of I2C bus; Line between the 120th port and the 123rd port is the clock SCL of I2C bus; The content of initialization Authority Verification information D is 512 Authority Verification codes, 512 Authority Verification check codes, and 512 authorization codes, authorize check code for 512.
  8. 8. chip according to claim 7, it is characterized in that: described 512 its verification modes of Authority Verification check code are 512 Authority Verification codes to be divided into the message block of 8 groups 64, respectively D0[63:0], D1[63:0], D2[63:0], D3[63:0], D4[63:0], D5[63:0], D6[63:0], D7[63:0]; Taking D0[63:0] be example, 64 message block D0[63:0] adopt CRC-32 to generate 32 Cyclic Redundancy Code C0[31:0], generator polynomial brief note formula is 04C11DB7, message block D0[0:63] adopting CRC-32 to generate 32 Cyclic Redundancy Code C0[63:32], generator polynomial brief note formula is 1EDC6F41, finally composition check code be C0[63:0], C1[63:0], C2[63:0], C3[63:0], C4[63:0], C5[63:0], C6[63:0], C7[63:0] be 512 Authority Verification check codes.
  9. 9. chip according to claim 7, it is characterized in that: described 512 its verification modes of mandate check code are 512 authorization codes to be divided into the message block of 8 groups 64, respectively D10[63:0], D11[63:0], D12[63:0], D13[63:0], D14[63:0], D15[63:0], D16[63:0], D17[63:0]; Taking D10[63:0] be example, 64 message block D10[63:0] adopt CRC-32 to generate 32 Cyclic Redundancy Code C10[31:0], generator polynomial brief note formula is 04C11DB7, message block D10[0:63] adopting CRC-32 to generate 32 Cyclic Redundancy Code C10[63:32], generator polynomial brief note formula is 1EDC6F41, finally composition check code be C10[63:0], C11[63:0], C12[63:0], C13[63:0], C14[63:0], C15[63:0], C16[63:0], C17[63:0] be 512 mandate check codes.
  10. 10. chip according to claim 1, is characterized in that: serial communication controller 1 and serial communication controller 2 meet I2C bus communication protocol; The input port of serial communication controller 1 is the 230th port, the 231st port; Serial communication controller 1 output port is the 228th port, the 229th port; The 230th port is connected with the 122nd port of microprocessor, for receiving initialization authority information D; The 231st port is connected with microprocessor the 123rd port, for receive clock 2; The 229th port with invade the 220th port of detection module and be connected, for sending permission authorization information D1 to the 220th port of invading detection module; The 228th port is connected with the 221st port of invading detection module, the 228th port and the 231st direct port connection, and therefore the 228th port is sent to clock 2 the 221st port of invading detection module; The input port of serial communication controller 2 is the 234th port, the 235th port; Serial communication controller 2 output ports are the 232nd port, the 233rd port; The 235th port is connected with the 124th port of microprocessor, for receiving initialization anti-counterfeiting information E; The 234th port is connected with microprocessor the 123rd port, for receive clock 2; The 232nd port is connected with the 207th port of the temporary module of input information, for sending 207th port of anti-counterfeiting information E1 to the temporary module of input information; The 233rd port is connected with the 206th port of the temporary module of input information, the 233rd port and the 234th direct port connection, and therefore the 233rd port is sent to clock 2 the 206th port of the temporary module of input information.
  11. 11. chips according to claim 1, is characterized in that: the input port of the temporary module of input information is the 201st port, the 202nd port, the 204th port, the 206th port; The output port of the temporary module of input information is the 203rd port, the 205th port; The 201st port is eight bit parallel ports, with eight buses corresponding being connected one by one of the 110th port of microprocessor, for receiving the checking solicited message A[7:0 of input]; The 202nd port is connected with the 111st port of microprocessor, for receive clock 1; The 204th port is connected with the 212nd port of invading detection module, for receiving signal mode control; The 203rd port is connected with the 213rd port of invading detection module, for output system clock; The 205th port is connected with the 211st port of invading detection module, for sending input message F to invading detection module; The temporary module of input information is 1 by a width, the push-up storage that the degree of depth is 512, and 1 MUX, 1 parallel-serial converter, one and string signal maker, a system clock maker forms; The input end of system clock maker is the pattern control of clock 2, the 204 port inputs of clock 1, the 206 port input of the 202nd port input, is output as the system clock of the 203rd port output; In the time that the pattern control of the 204th port input is high level, the clock 1 of the 202nd port input is from the 203rd port output and as system clock, in the time that the pattern control of the 204th port input is low level, the clock 2 of the 206th port input is from the 203rd port output and as system clock; And string signal maker is made up of one two input and door and mould 9 counters 1; With the input end of door be the clock 1 of the 202nd port input and two signals of pattern control of the 204th port input, with the output terminal of the door clock trigger end as mould 9 counters 1; Mould 9 counters 1 count value be 9 o'clock output signals also-string switching signal is high level, when its remainder values, also-string switching signal is low level; Parallel-serial converter is in the time of the system clock rising edge of the 203rd port output, and also-string switching signal is while being high level, is written into the parallel data fake certification information A[7:0 of the 201st port input], otherwise serial output data is to an input end of MUX; MUX is in the time that the pattern control of the 204th port input is high level, the output valve of output parallel-serial converter is to the output terminal of push-up storage, in the time that the pattern control of the 204th port input is low level, output anti-counterfeiting information E1 is to the output terminal of push-up storage; Push-up storage is made up of 512 d type flip flops, and data input pin and the data output end of 512 triggers join end to end, and data output end is the input message F of the 205th port output.
  12. 12. chips according to claim 1, is characterized in that: the input port that information is read in module is the 224th port, the 223rd port; The output port that information is read in module is the 222nd port; The 224th port is connected with the 115th port of microprocessor, for receiving the anti-counterfeiting information L[7:0 of disposable programmable read only memory output]; The 223rd port is connected with the 215th port of invading detection module, for receiving system clock; The 222nd port is connected with the 216th port of invading detection module, for exporting anti-counterfeiting information H to invading detection module; It is 8 by a width that information is read in module, and the degree of depth is 1 also-and string transition trigger device group and mould 9 counters 2 form; Mould 9 counters 2 under the system clock rising edge of the 223rd port input triggers counting output signal also-string switching signal 1; Be that 9 o'clock also-string switching signals 1 are high level in count value, when its remainder values, also-string switching signal 1 is low level; Parallel-serial converter is in the time of the system clock rising edge of the 223rd port input, and when also-string switching signal 1 is high level, be written into the anti-counterfeiting information L[7:0 of parallel data the 224th port input], otherwise serial output data to the 222 ports export intrusion detection module to as anti-counterfeiting information H.
  13. 13. chips according to claim 1, is characterized in that: the input port that information is write out module is the 225th port, the 226th port; The output port that information is write out module is the 113rd port; The 225th port is connected with the 219th port of invading detection module, for receiving the anti-counterfeiting information I writing; The 226th port is connected with the 218th port of invading detection module, for receiving system clock; The 227th port is connected with the 113rd port of microprocessor, for exporting the anti-counterfeiting information J[7:0 writing]; It is 8 by a width that information is write out module, string that the degree of depth is 1-and transition trigger device group form; This string-and the input end of transition trigger device be the anti-counterfeiting information I writing of the 225th port input, under the system clock rising edge of the 226th port input triggers, the anti-counterfeiting information J[7:0 writing by the 227th port output parallel data].
  14. 14. chips according to claim 1, is characterized in that: the input port of message output module is the 209th port, the 236th port; The output port of message output module is the 208th port; The 209th port is connected with the 214th port of invading detection module, for receiving anti-counterfeiting information G to be exported; The 208th port is connected with the 112nd port of microprocessor, for sending output anti-counterfeiting information B[7:0]; The 236th port is connected with the 203rd port of the temporary module of input information, for receiving system clock; Message output module is 8 by a width, string that the degree of depth is 1-and transition trigger device group form; This string-and the input end of transition trigger device be the anti-counterfeiting information G to be exported that the 209th port receives, under the system clock rising edge of the 236th port input triggers, export parallel output anti-counterfeiting information B[7:0 by the 208th port].
  15. 15. chips according to claim 1, is characterized in that: the input port of invading detection module is the 211st port, the 213rd port, the 216th port, the 220th port, the 221st port; The output port of invading detection module is the 212nd port, the 214th port, the 215th port, the 217th port, the 218th port, the 219th port; The 213rd port and the 215th port, the 218th direct port connection, the 215th port, the 218th port is for direct output system clock; The 216th port is connected with the 214th port, for anti-counterfeiting information H being directly sent to the 209th port of message output module; The 114th port of the 217th port and microprocessor is connected, for to disposable programmable read only memory OPADD Addr[10:0]; Invade detection module by forming as lower module, mode control signal maker, address generation module, anti-counterfeiting information programming module.
  16. 16. chips according to claim 15, is characterized in that: mode control signal maker is by three d type flip flops, and the rejection gate of one three input one output forms; Joining end to end of three d type flip flops, input end is the Authority Verification information D1 of the 220th port input; The clock end of three d type flip flops is all connected with clock 2; The output terminal of a three d type flip flops respectively input end of AND OR NOT gate is connected; The output terminal of rejection gate is the pattern control of the 212nd port output.
  17. 17. chips according to claim 15, is characterized in that: address generation module forms with door and address generator by one; Address generator is counting under triggering with the rising edge of door output, and count value is as the address Addr[10:0 of 11] by the 217th port output.
  18. 18. chips according to claim 15, is characterized in that: anti-counterfeiting information programming module is 1 by two width, the push-up storage that the degree of depth is 512, XOR gate, two and door, mould 1024 frequency dividers, a d type flip flop, a CRC maker composition; Push-up storage 1 is made up of 512 d type flip flops, data input pin and the data output end of 512 triggers join end to end, push-up storage 1 data output end is the Authority Verification information D1 of the 220th port input, and input end of data output end and XOR gate is connected; The clock end of push-up storage 1 is the system clock of the 213rd port input; Push-up storage 2 is made up of 512 d type flip flops, and data input pin and the data output end of 512 triggers join end to end, and push-up storage 2 data output ends are the check code of CRC maker output, and input end of output terminal and XOR gate is connected; The clock end of push-up storage 2 is the system clock of the 213rd port input; Mould 1024 frequency dividers carry out frequency division to the system clock of the 213rd port input, and divide ratio is 1024, output terminal be connected with an input end of door 1; Mould 1024 frequency dividers carry out frequency division to the system clock of the 213rd port input; The output terminal of XOR gate be connected with another output terminal of door 1; Be connected with the output terminal of door 1 and the clock end of d type flip flop; The data terminal of d type flip flop is connected with power supply, the oppisite phase data end of d type flip flop be connected with the data input pin of door 2; The input message F that port 211 is inputted is connected with another data input pin of door 2; Be the anti-counterfeiting information I writing and export by the 219th port with the data output end of door 2.
  19. 19. chips according to claim 1, it is characterized in that: special Flash-writer is under clock 2 synchronous, by the 124th port, initialization anti-counterfeiting information E is write in serial communication controller 2, serial communication controller 2 reverts to anti-counterfeiting information E1 according to I2C bus protocol by initialization anti-counterfeiting information E, and anti-counterfeiting information E1 is sent into information temporary storage module; Special Flash-writer is under clock 2 synchronous, by the 122nd port, initialization Authority Verification information D is write in serial communication controller 1, serial communication controller 1 reverts to serial data Authority Verification information D1 according to I2C bus protocol by initialization Authority Verification information D, and Authority Verification information D1 is sent into intrusion detection module; Invade detection module after detecting that Authority Verification information D1 is legal information, the anti-counterfeiting information I writing is sent into information and write out module; Information write out module under the triggering of system clock by the anti-counterfeiting information J[7:0 writing] write disposable programmable read only memory; Disposable programmable read only memory is at address Addr[10:0] control under by the anti-counterfeiting information J[7:0 writing] write assigned address.
  20. 20. chips according to claim 1, is characterized in that: mobile phone by common interface module under clock 1 synchronous, by the fake certification information A[7:0 of input] send into the temporary module of input information; Under the rising edge of system clock and input message F phase and signal triggers, invade detection module calculated address Addr[10:0] send into disposable programmable read only memory; Information is read in module and is read in the anti-counterfeiting information L[7:0 that disposable programmable read only memory is exported]; The anti-counterfeiting information H that intrusion detection module reads in information in module directly sends into message output module as anti-counterfeiting information G to be exported; Last under the triggering of clock, message output module will be exported anti-counterfeiting information B[7:0] send to mobile phone by common interface module.
  21. 21. chips according to claim 1, it is characterized in that: described chip is fixed on article surface, the anti-counterfeiting information of storing in described internal storage is for identifying described article, described anti-counterfeiting information is associated with the information of the same printing labeling that is fixed on article surface, on described printing labeling, be printed with two-dimensional bar and the ordinary numbers security code of traceable identify objects, described two-dimensional bar, ordinary numbers security code and corresponding anti-counterfeiting information are generated by item information data storehouse server, described anti-counterfeiting information is write in described chip, and the relevant information of described article is arrived to central database server by Internet Transmission, described central database server is connected with item information data storehouse server by network, store the relevant information of described article, receive the anti-counterfeiting information that sent by mobile phone and also the authorization information of respective articles is sent to mobile phone, the relevant information of described article is one or more in following information: the identifying information of article, production information, tracked information.
  22. 22. chips according to claim 21, it is characterized in that: in the internal storage of described chip, also store item tracing information, described item tracing information is write by special chip read write line separately by transfer website, wherein each transfer website has corresponding numbering and binds with special chip read write line separately, the described terminal data relevant to described tracked information of naming a person for a particular job are sent to central database server in real time, and upgrade on the server of item information data storehouse, terminal user uses mobile phone to send described anti-counterfeiting information to central database server, and obtain from the central database the tracked information of respective articles in server.
  23. 23. chips according to claim 22, it is characterized in that: terminal user downloads reading software on center service database, read the described anti-counterfeiting information of chip-stored by mobile phone, and by internet, described anti-counterfeiting information is sent to central database server, determine the true and false of article or obtain tracking and the production information of these article.
  24. 24. chips according to claim 22, it is characterized in that: mobile phone also can obtain two-dimensional bar or the ordinary numbers security code on printed label surface, and the relevant information getting is compared by the information in internet and central database server, determine the true and false of article and obtain tracking and the production information of these article; Or by the relevant information getting with compare from the anti-counterfeiting information obtaining in chip by common interface module, intersect comparison to realize.
  25. 25. chips according to claim 22, it is characterized in that: terminal user is in the time inquiring about commodity true and false or obtain tracking and production information, the short message prompt terminal user prompting of deducting fees, after successful query-related information, withholds relevant inquiring expense by communication operator.
  26. 26. chips according to claim 21, is characterized in that: described ordinary numbers security code is generated by computing machine, and are transformed and generated corresponding two-dimensional bar by digital anti-counterfeiting code.
CN201110153664.8A 2011-05-27 2011-05-27 Item identification chip for implementing anti-counterfeiting tracking Expired - Fee Related CN102262742B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201110153664.8A CN102262742B (en) 2011-05-27 2011-05-27 Item identification chip for implementing anti-counterfeiting tracking

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201110153664.8A CN102262742B (en) 2011-05-27 2011-05-27 Item identification chip for implementing anti-counterfeiting tracking

Publications (2)

Publication Number Publication Date
CN102262742A CN102262742A (en) 2011-11-30
CN102262742B true CN102262742B (en) 2014-06-18

Family

ID=45009363

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110153664.8A Expired - Fee Related CN102262742B (en) 2011-05-27 2011-05-27 Item identification chip for implementing anti-counterfeiting tracking

Country Status (1)

Country Link
CN (1) CN102262742B (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102567889A (en) * 2012-01-17 2012-07-11 成都科诺德信息技术有限公司 Anti-counterfeiting system and anti-counterfeiting query method by using mobile phone as checking terminal
CN102999472B (en) * 2012-12-03 2016-06-08 宁波舜宇光电信息有限公司 Module personalizing parameters transmission method and system
CN109769015B (en) * 2018-12-21 2022-05-27 深圳市广和通无线股份有限公司 Anti-counterfeiting component, system, method and computer readable storage medium
CN113032852A (en) * 2021-03-12 2021-06-25 北京银联金卡科技有限公司 Chip anti-counterfeiting method based on programmable circuit
CN116011037B (en) * 2023-03-28 2023-05-30 湖南毂梁微电子有限公司 Chip anti-counterfeiting circuit and anti-counterfeiting chip aiming at reverse design

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1588386A (en) * 2004-08-02 2005-03-02 上海质尊电子科技有限公司 System and method for realizing article information detection by radio frequency identification and mobile communication combination
CN101015194A (en) * 2004-09-10 2007-08-08 摩托罗拉公司 Tag for facilitating interaction with a wireless communication device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7411821B2 (en) * 2006-03-27 2008-08-12 Intel Corporation Method and apparatus to protect nonvolatile memory from viruses

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1588386A (en) * 2004-08-02 2005-03-02 上海质尊电子科技有限公司 System and method for realizing article information detection by radio frequency identification and mobile communication combination
CN101015194A (en) * 2004-09-10 2007-08-08 摩托罗拉公司 Tag for facilitating interaction with a wireless communication device

Also Published As

Publication number Publication date
CN102262742A (en) 2011-11-30

Similar Documents

Publication Publication Date Title
CN102376031B (en) Anti-counterfeiting tracking system using chip to identify articles
CN102262742B (en) Item identification chip for implementing anti-counterfeiting tracking
CN108009780A (en) A kind of intelligent and safe delivery system
CN104022549B (en) A kind of electric automobile intelligent charge access system
CN112036901A (en) Method for protecting supply chain data in block chain and system for recording supply chain information
CN102509210B (en) Transportation storage system and method of blood
EP3227853A1 (en) Cryptographic verification of provenance in a supply chain
CN102496209A (en) Intelligent object network heat meter and management system thereof
CN202159373U (en) Electromobile in network of things and supporting electronic payment
CN107273775A (en) Electronic tag and processing system and method for ensuring electronic tag
CN102496259A (en) Internet of things based water meter and management system thereof
CN101783040B (en) Smart card swipe machine and information exchange method
CN106097467A (en) A kind of box, throwing pickup system and method and the inquiry of the box and localization method
CN101118589B (en) Read-write machine dedicated for anti-counterfeit based on radio frequency recognizing technology and management method
CN101110105A (en) Radio frequency recognizing reader-writer personal identification method based on SIM card
CN202210297U (en) Anti-fake track system utilizing chip to identify items
CN102324158A (en) Internet of things based fiscal cash register system
CN202042018U (en) Terminal of internet of things capable of supporting e-payment
CN103839322B (en) Intelligent card, verification data output method, operation request response method and system
CN103455927A (en) Dark-red enameled pottery anti-counterfeiting recognition system based on RFID
CN202171819U (en) Chip used for identifying article to realize anti-counterfeit tracking
CN203490738U (en) RFID-based dark-red enameled pottery anti-counterfeiting recognition system
CN110097347A (en) A kind of visual card transaction system of wireless charging digital cash
CN105654371B (en) A kind of financial IC card mostly application authorization card sending system
CN108319877A (en) Use the information reading terminals of the coding of external token

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
ASS Succession or assignment of patent right

Owner name: LIN JIAMIAO

Free format text: FORMER OWNER: XU LIANGYU

Effective date: 20120615

Owner name: ZHOU HUA LIN JIAZE

Free format text: FORMER OWNER: LIN JIAMIAO ZHOU HUA

Effective date: 20120615

C41 Transfer of patent application or patent right or utility model
COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; FROM: 010010 HOHHOT, INNER MONGOLIA AUTONOMOUS REGION TO: 325802 WENZHOU, ZHEJIANG PROVINCE

TA01 Transfer of patent application right

Effective date of registration: 20120615

Address after: Longgang Zhen Xi Liu Jie in Wenzhou of Zhejiang province 325802 City Garden Building 2 room 404

Applicant after: Lin Jiajiu

Co-applicant after: Zhou Hua

Co-applicant after: Lin Jiaze

Address before: 010010, Hohhot, the Inner Mongolia Autonomous Region Saihan Erdos East Street, 8037 days and Apartments

Applicant before: Xu Liangyu

Co-applicant before: Lin Jiajiu

Co-applicant before: Zhou Hua

ASS Succession or assignment of patent right

Owner name: HANGZHOU BLZX TECHNOLOGY CO., LTD.

Free format text: FORMER OWNER: LIN JIAMIAO

Effective date: 20140418

Free format text: FORMER OWNER: ZHOU HUA LIN JIAZE

Effective date: 20140418

C41 Transfer of patent application or patent right or utility model
COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; FROM: 325802 WENZHOU, ZHEJIANG PROVINCE TO: 311121 HANGZHOU, ZHEJIANG PROVINCE

TA01 Transfer of patent application right

Effective date of registration: 20140418

Address after: The city of Hangzhou in West Zhejiang province 311121 No. 998 Zhejiang overseas high-level talents Innovation Park 19 Building 501, Room 502

Applicant after: HANGZHOU BOLIAN ZHIXIN TECHNOLOGY CO., LTD.

Address before: Longgang Zhen Xi Liu Jie in Wenzhou of Zhejiang province 325802 City Garden Building 2 room 404

Applicant before: Lin Jiajiu

Applicant before: Zhou Hua

Applicant before: Lin Jiaze

C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20140618

Termination date: 20160527