CN102262742B - Item identification chip for implementing anti-counterfeiting tracking - Google Patents
Item identification chip for implementing anti-counterfeiting tracking Download PDFInfo
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- CN102262742B CN102262742B CN201110153664.8A CN201110153664A CN102262742B CN 102262742 B CN102262742 B CN 102262742B CN 201110153664 A CN201110153664 A CN 201110153664A CN 102262742 B CN102262742 B CN 102262742B
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Abstract
Description
Claims (26)
- For identify objects to realize a chip for anti-counterfeit tracking, it is characterized in that:Described chip comprises microprocessor, common interface module and internal storage, and described common interface module is connected with described microprocessor, and described microprocessor is connected with described internal storage;Described common interface module receives the checking solicited message that mobile phone sends, and this checking solicited message is transferred to microprocessor processes, receives the anti-counterfeiting information of microprocessor transmission and sends this anti-counterfeiting information to mobile phone;Described microprocessor receives the checking solicited message that comes from described common interface module, based on this checking solicited message, reads described anti-counterfeiting information from described internal storage, and described anti-counterfeiting information is sent to common interface module;Described internal storage is stored described anti-counterfeiting information; And,Described microprocessor comprises that serial communication controller 1, serial communication controller 2, the temporary module of input information, intrusion detection module, information are read in module, information is write out module and message output module; Wherein:Described serial communication controller 1 is for receiving Authority Verification information, and exports Authority Verification information to invading detection module;Described serial communication controller 2 is for receiving described anti-counterfeiting information, and exports described anti-counterfeiting information to the temporary module of described input information;Described intrusion detection module is for controlling the mode of operation of microprocessor, and described mode of operation is writing information pattern and information contrastive pattern;The temporary module of described input information is used for receiving described anti-counterfeiting information, also for receiving the described checking solicited message of input, and in the time that microprocessor is writing information pattern, described anti-counterfeiting information is inputed to intrusion detection module, and in the time that microprocessor is information contrastive pattern, described checking solicited message is inputed to intrusion detection module;Described intrusion detection module is used under writing information pattern when detecting that exporting anti-counterfeiting information to information after Authority Verification information is legal information writes out module to write internal storage, also under information contrastive pattern, checking solicited message being sent into described internal storage, and information is read in to the anti-counterfeiting information that module reads in send into message output module to send to mobile phone by common interface module.
- 2. chip according to claim 1, is characterized in that:Described common interface module supports GSM signal to communicate with mobile phone, and described internal storage is disposable programmable read only memory OTP ROM.
- 3. chip according to claim 2, is characterized in that:Described microprocessor also receives the initialization anti-counterfeiting information that comes from special chip read write line, and writes anti-counterfeiting information in described internal storage.
- 4. chip according to claim 2, is characterized in that: the input port of described common interface module is the 104th port, the 105th port and the 109th port; Output port is the 106th port, the 107th port and the 108th port; The 104th port is set up communication with the 101st outside port and is connected, for transmitting checking solicited message A1[7:0], the 105th port is set up communication with the 102nd outside port and is connected, for receive clock 1; The 106th port is set up communication with the 103rd outside port and is connected, for send outside anti-counterfeiting information B1[7:0 to outside]; The 107th port is connected with the 110th port of microprocessor, for transmitting the checking solicited message A[7:0 of input]; The 108th port is connected with the 11.1st port of microprocessor, for clock 1 is sent into microprocessor; The 109th port is connected with the 112nd port of microprocessor, the output anti-counterfeiting information B[7:0 sending for receiving microprocessor].
- 5. chip according to claim 2, is characterized in that: described disposable programmable read only memory input port has the 116th port and the 117th port; Output port is the 118th port; The 116th port is connected with the 113rd port of microprocessor, by the anti-counterfeiting information J[7:0 writing] write in disposable programmable read only memory, the region to be written of disposable programmable read only memory can only be written into primary information under the control of microprocessor, and information can not be modified thereafter; If want supplement information,, under the control of microprocessor, supplement information is write to other regions to be written of disposable programmable read only memory; Region to be written, once being written into information, cannot be revised; The area size to be written of disposable programmable read only memory is determined by the memory capacity of disposable programmable read only memory; The 117th port is connected with the 114th port of microprocessor, for by address Addr[10:0] send into the address end of disposable programmable read only memory; The 118th port is connected with the 115th port of microprocessor, for by address Addr[10:0] the anti-counterfeiting information L[7:0 that specifies] send into microprocessor.
- 6. chip according to claim 3, is characterized in that: the input port of microprocessor is the 110th port, the 111st port, the 115th port, the 122nd port, the 123rd port and the 124th port; The input port of microprocessor is the 112nd port, the 113rd port and the 114th port; The 119th port of the 122nd port and outside special chip read write line is connected, for receiving initialization Authority Verification information D; The 120th port of the 123rd port and special chip read write line is connected, for receive clock 2; The 121st port of the 124th port and special chip read write line is connected, for receiving initialization anti-counterfeiting information E.
- 7. chip according to claim 6, is characterized in that: the communication mode of described initialization anti-counterfeiting information E is serial communication, and communication protocol meets I2C bus protocol; Line between the 121st port and the 124th port is as the data line SDA of I2C bus; Line between the 120th port and the 123rd port is the clock SCL of I2C bus; The communication mode of initialization Authority Verification information D is serial communication, and communication protocol meets I2C bus protocol; Line between the 119th port and the 122nd port is as the data line SDA of I2C bus; Line between the 120th port and the 123rd port is the clock SCL of I2C bus; The content of initialization Authority Verification information D is 512 Authority Verification codes, 512 Authority Verification check codes, and 512 authorization codes, authorize check code for 512.
- 8. chip according to claim 7, it is characterized in that: described 512 its verification modes of Authority Verification check code are 512 Authority Verification codes to be divided into the message block of 8 groups 64, respectively D0[63:0], D1[63:0], D2[63:0], D3[63:0], D4[63:0], D5[63:0], D6[63:0], D7[63:0]; Taking D0[63:0] be example, 64 message block D0[63:0] adopt CRC-32 to generate 32 Cyclic Redundancy Code C0[31:0], generator polynomial brief note formula is 04C11DB7, message block D0[0:63] adopting CRC-32 to generate 32 Cyclic Redundancy Code C0[63:32], generator polynomial brief note formula is 1EDC6F41, finally composition check code be C0[63:0], C1[63:0], C2[63:0], C3[63:0], C4[63:0], C5[63:0], C6[63:0], C7[63:0] be 512 Authority Verification check codes.
- 9. chip according to claim 7, it is characterized in that: described 512 its verification modes of mandate check code are 512 authorization codes to be divided into the message block of 8 groups 64, respectively D10[63:0], D11[63:0], D12[63:0], D13[63:0], D14[63:0], D15[63:0], D16[63:0], D17[63:0]; Taking D10[63:0] be example, 64 message block D10[63:0] adopt CRC-32 to generate 32 Cyclic Redundancy Code C10[31:0], generator polynomial brief note formula is 04C11DB7, message block D10[0:63] adopting CRC-32 to generate 32 Cyclic Redundancy Code C10[63:32], generator polynomial brief note formula is 1EDC6F41, finally composition check code be C10[63:0], C11[63:0], C12[63:0], C13[63:0], C14[63:0], C15[63:0], C16[63:0], C17[63:0] be 512 mandate check codes.
- 10. chip according to claim 1, is characterized in that: serial communication controller 1 and serial communication controller 2 meet I2C bus communication protocol; The input port of serial communication controller 1 is the 230th port, the 231st port; Serial communication controller 1 output port is the 228th port, the 229th port; The 230th port is connected with the 122nd port of microprocessor, for receiving initialization authority information D; The 231st port is connected with microprocessor the 123rd port, for receive clock 2; The 229th port with invade the 220th port of detection module and be connected, for sending permission authorization information D1 to the 220th port of invading detection module; The 228th port is connected with the 221st port of invading detection module, the 228th port and the 231st direct port connection, and therefore the 228th port is sent to clock 2 the 221st port of invading detection module; The input port of serial communication controller 2 is the 234th port, the 235th port; Serial communication controller 2 output ports are the 232nd port, the 233rd port; The 235th port is connected with the 124th port of microprocessor, for receiving initialization anti-counterfeiting information E; The 234th port is connected with microprocessor the 123rd port, for receive clock 2; The 232nd port is connected with the 207th port of the temporary module of input information, for sending 207th port of anti-counterfeiting information E1 to the temporary module of input information; The 233rd port is connected with the 206th port of the temporary module of input information, the 233rd port and the 234th direct port connection, and therefore the 233rd port is sent to clock 2 the 206th port of the temporary module of input information.
- 11. chips according to claim 1, is characterized in that: the input port of the temporary module of input information is the 201st port, the 202nd port, the 204th port, the 206th port; The output port of the temporary module of input information is the 203rd port, the 205th port; The 201st port is eight bit parallel ports, with eight buses corresponding being connected one by one of the 110th port of microprocessor, for receiving the checking solicited message A[7:0 of input]; The 202nd port is connected with the 111st port of microprocessor, for receive clock 1; The 204th port is connected with the 212nd port of invading detection module, for receiving signal mode control; The 203rd port is connected with the 213rd port of invading detection module, for output system clock; The 205th port is connected with the 211st port of invading detection module, for sending input message F to invading detection module; The temporary module of input information is 1 by a width, the push-up storage that the degree of depth is 512, and 1 MUX, 1 parallel-serial converter, one and string signal maker, a system clock maker forms; The input end of system clock maker is the pattern control of clock 2, the 204 port inputs of clock 1, the 206 port input of the 202nd port input, is output as the system clock of the 203rd port output; In the time that the pattern control of the 204th port input is high level, the clock 1 of the 202nd port input is from the 203rd port output and as system clock, in the time that the pattern control of the 204th port input is low level, the clock 2 of the 206th port input is from the 203rd port output and as system clock; And string signal maker is made up of one two input and door and mould 9 counters 1; With the input end of door be the clock 1 of the 202nd port input and two signals of pattern control of the 204th port input, with the output terminal of the door clock trigger end as mould 9 counters 1; Mould 9 counters 1 count value be 9 o'clock output signals also-string switching signal is high level, when its remainder values, also-string switching signal is low level; Parallel-serial converter is in the time of the system clock rising edge of the 203rd port output, and also-string switching signal is while being high level, is written into the parallel data fake certification information A[7:0 of the 201st port input], otherwise serial output data is to an input end of MUX; MUX is in the time that the pattern control of the 204th port input is high level, the output valve of output parallel-serial converter is to the output terminal of push-up storage, in the time that the pattern control of the 204th port input is low level, output anti-counterfeiting information E1 is to the output terminal of push-up storage; Push-up storage is made up of 512 d type flip flops, and data input pin and the data output end of 512 triggers join end to end, and data output end is the input message F of the 205th port output.
- 12. chips according to claim 1, is characterized in that: the input port that information is read in module is the 224th port, the 223rd port; The output port that information is read in module is the 222nd port; The 224th port is connected with the 115th port of microprocessor, for receiving the anti-counterfeiting information L[7:0 of disposable programmable read only memory output]; The 223rd port is connected with the 215th port of invading detection module, for receiving system clock; The 222nd port is connected with the 216th port of invading detection module, for exporting anti-counterfeiting information H to invading detection module; It is 8 by a width that information is read in module, and the degree of depth is 1 also-and string transition trigger device group and mould 9 counters 2 form; Mould 9 counters 2 under the system clock rising edge of the 223rd port input triggers counting output signal also-string switching signal 1; Be that 9 o'clock also-string switching signals 1 are high level in count value, when its remainder values, also-string switching signal 1 is low level; Parallel-serial converter is in the time of the system clock rising edge of the 223rd port input, and when also-string switching signal 1 is high level, be written into the anti-counterfeiting information L[7:0 of parallel data the 224th port input], otherwise serial output data to the 222 ports export intrusion detection module to as anti-counterfeiting information H.
- 13. chips according to claim 1, is characterized in that: the input port that information is write out module is the 225th port, the 226th port; The output port that information is write out module is the 113rd port; The 225th port is connected with the 219th port of invading detection module, for receiving the anti-counterfeiting information I writing; The 226th port is connected with the 218th port of invading detection module, for receiving system clock; The 227th port is connected with the 113rd port of microprocessor, for exporting the anti-counterfeiting information J[7:0 writing]; It is 8 by a width that information is write out module, string that the degree of depth is 1-and transition trigger device group form; This string-and the input end of transition trigger device be the anti-counterfeiting information I writing of the 225th port input, under the system clock rising edge of the 226th port input triggers, the anti-counterfeiting information J[7:0 writing by the 227th port output parallel data].
- 14. chips according to claim 1, is characterized in that: the input port of message output module is the 209th port, the 236th port; The output port of message output module is the 208th port; The 209th port is connected with the 214th port of invading detection module, for receiving anti-counterfeiting information G to be exported; The 208th port is connected with the 112nd port of microprocessor, for sending output anti-counterfeiting information B[7:0]; The 236th port is connected with the 203rd port of the temporary module of input information, for receiving system clock; Message output module is 8 by a width, string that the degree of depth is 1-and transition trigger device group form; This string-and the input end of transition trigger device be the anti-counterfeiting information G to be exported that the 209th port receives, under the system clock rising edge of the 236th port input triggers, export parallel output anti-counterfeiting information B[7:0 by the 208th port].
- 15. chips according to claim 1, is characterized in that: the input port of invading detection module is the 211st port, the 213rd port, the 216th port, the 220th port, the 221st port; The output port of invading detection module is the 212nd port, the 214th port, the 215th port, the 217th port, the 218th port, the 219th port; The 213rd port and the 215th port, the 218th direct port connection, the 215th port, the 218th port is for direct output system clock; The 216th port is connected with the 214th port, for anti-counterfeiting information H being directly sent to the 209th port of message output module; The 114th port of the 217th port and microprocessor is connected, for to disposable programmable read only memory OPADD Addr[10:0]; Invade detection module by forming as lower module, mode control signal maker, address generation module, anti-counterfeiting information programming module.
- 16. chips according to claim 15, is characterized in that: mode control signal maker is by three d type flip flops, and the rejection gate of one three input one output forms; Joining end to end of three d type flip flops, input end is the Authority Verification information D1 of the 220th port input; The clock end of three d type flip flops is all connected with clock 2; The output terminal of a three d type flip flops respectively input end of AND OR NOT gate is connected; The output terminal of rejection gate is the pattern control of the 212nd port output.
- 17. chips according to claim 15, is characterized in that: address generation module forms with door and address generator by one; Address generator is counting under triggering with the rising edge of door output, and count value is as the address Addr[10:0 of 11] by the 217th port output.
- 18. chips according to claim 15, is characterized in that: anti-counterfeiting information programming module is 1 by two width, the push-up storage that the degree of depth is 512, XOR gate, two and door, mould 1024 frequency dividers, a d type flip flop, a CRC maker composition; Push-up storage 1 is made up of 512 d type flip flops, data input pin and the data output end of 512 triggers join end to end, push-up storage 1 data output end is the Authority Verification information D1 of the 220th port input, and input end of data output end and XOR gate is connected; The clock end of push-up storage 1 is the system clock of the 213rd port input; Push-up storage 2 is made up of 512 d type flip flops, and data input pin and the data output end of 512 triggers join end to end, and push-up storage 2 data output ends are the check code of CRC maker output, and input end of output terminal and XOR gate is connected; The clock end of push-up storage 2 is the system clock of the 213rd port input; Mould 1024 frequency dividers carry out frequency division to the system clock of the 213rd port input, and divide ratio is 1024, output terminal be connected with an input end of door 1; Mould 1024 frequency dividers carry out frequency division to the system clock of the 213rd port input; The output terminal of XOR gate be connected with another output terminal of door 1; Be connected with the output terminal of door 1 and the clock end of d type flip flop; The data terminal of d type flip flop is connected with power supply, the oppisite phase data end of d type flip flop be connected with the data input pin of door 2; The input message F that port 211 is inputted is connected with another data input pin of door 2; Be the anti-counterfeiting information I writing and export by the 219th port with the data output end of door 2.
- 19. chips according to claim 1, it is characterized in that: special Flash-writer is under clock 2 synchronous, by the 124th port, initialization anti-counterfeiting information E is write in serial communication controller 2, serial communication controller 2 reverts to anti-counterfeiting information E1 according to I2C bus protocol by initialization anti-counterfeiting information E, and anti-counterfeiting information E1 is sent into information temporary storage module; Special Flash-writer is under clock 2 synchronous, by the 122nd port, initialization Authority Verification information D is write in serial communication controller 1, serial communication controller 1 reverts to serial data Authority Verification information D1 according to I2C bus protocol by initialization Authority Verification information D, and Authority Verification information D1 is sent into intrusion detection module; Invade detection module after detecting that Authority Verification information D1 is legal information, the anti-counterfeiting information I writing is sent into information and write out module; Information write out module under the triggering of system clock by the anti-counterfeiting information J[7:0 writing] write disposable programmable read only memory; Disposable programmable read only memory is at address Addr[10:0] control under by the anti-counterfeiting information J[7:0 writing] write assigned address.
- 20. chips according to claim 1, is characterized in that: mobile phone by common interface module under clock 1 synchronous, by the fake certification information A[7:0 of input] send into the temporary module of input information; Under the rising edge of system clock and input message F phase and signal triggers, invade detection module calculated address Addr[10:0] send into disposable programmable read only memory; Information is read in module and is read in the anti-counterfeiting information L[7:0 that disposable programmable read only memory is exported]; The anti-counterfeiting information H that intrusion detection module reads in information in module directly sends into message output module as anti-counterfeiting information G to be exported; Last under the triggering of clock, message output module will be exported anti-counterfeiting information B[7:0] send to mobile phone by common interface module.
- 21. chips according to claim 1, it is characterized in that: described chip is fixed on article surface, the anti-counterfeiting information of storing in described internal storage is for identifying described article, described anti-counterfeiting information is associated with the information of the same printing labeling that is fixed on article surface, on described printing labeling, be printed with two-dimensional bar and the ordinary numbers security code of traceable identify objects, described two-dimensional bar, ordinary numbers security code and corresponding anti-counterfeiting information are generated by item information data storehouse server, described anti-counterfeiting information is write in described chip, and the relevant information of described article is arrived to central database server by Internet Transmission, described central database server is connected with item information data storehouse server by network, store the relevant information of described article, receive the anti-counterfeiting information that sent by mobile phone and also the authorization information of respective articles is sent to mobile phone, the relevant information of described article is one or more in following information: the identifying information of article, production information, tracked information.
- 22. chips according to claim 21, it is characterized in that: in the internal storage of described chip, also store item tracing information, described item tracing information is write by special chip read write line separately by transfer website, wherein each transfer website has corresponding numbering and binds with special chip read write line separately, the described terminal data relevant to described tracked information of naming a person for a particular job are sent to central database server in real time, and upgrade on the server of item information data storehouse, terminal user uses mobile phone to send described anti-counterfeiting information to central database server, and obtain from the central database the tracked information of respective articles in server.
- 23. chips according to claim 22, it is characterized in that: terminal user downloads reading software on center service database, read the described anti-counterfeiting information of chip-stored by mobile phone, and by internet, described anti-counterfeiting information is sent to central database server, determine the true and false of article or obtain tracking and the production information of these article.
- 24. chips according to claim 22, it is characterized in that: mobile phone also can obtain two-dimensional bar or the ordinary numbers security code on printed label surface, and the relevant information getting is compared by the information in internet and central database server, determine the true and false of article and obtain tracking and the production information of these article; Or by the relevant information getting with compare from the anti-counterfeiting information obtaining in chip by common interface module, intersect comparison to realize.
- 25. chips according to claim 22, it is characterized in that: terminal user is in the time inquiring about commodity true and false or obtain tracking and production information, the short message prompt terminal user prompting of deducting fees, after successful query-related information, withholds relevant inquiring expense by communication operator.
- 26. chips according to claim 21, is characterized in that: described ordinary numbers security code is generated by computing machine, and are transformed and generated corresponding two-dimensional bar by digital anti-counterfeiting code.
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CN102567889A (en) * | 2012-01-17 | 2012-07-11 | 成都科诺德信息技术有限公司 | Anti-counterfeiting system and anti-counterfeiting query method by using mobile phone as checking terminal |
CN102999472B (en) * | 2012-12-03 | 2016-06-08 | 宁波舜宇光电信息有限公司 | Module personalizing parameters transmission method and system |
CN109769015B (en) * | 2018-12-21 | 2022-05-27 | 深圳市广和通无线股份有限公司 | Anti-counterfeiting component, system, method and computer readable storage medium |
CN113032852A (en) * | 2021-03-12 | 2021-06-25 | 北京银联金卡科技有限公司 | Chip anti-counterfeiting method based on programmable circuit |
CN116011037B (en) * | 2023-03-28 | 2023-05-30 | 湖南毂梁微电子有限公司 | Chip anti-counterfeiting circuit and anti-counterfeiting chip aiming at reverse design |
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CN1588386A (en) * | 2004-08-02 | 2005-03-02 | 上海质尊电子科技有限公司 | System and method for realizing article information detection by radio frequency identification and mobile communication combination |
CN101015194A (en) * | 2004-09-10 | 2007-08-08 | 摩托罗拉公司 | Tag for facilitating interaction with a wireless communication device |
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