CN202168065U - Double DDS and PLL frequency synthesizer - Google Patents
Double DDS and PLL frequency synthesizer Download PDFInfo
- Publication number
- CN202168065U CN202168065U CN2011202574977U CN201120257497U CN202168065U CN 202168065 U CN202168065 U CN 202168065U CN 2011202574977 U CN2011202574977 U CN 2011202574977U CN 201120257497 U CN201120257497 U CN 201120257497U CN 202168065 U CN202168065 U CN 202168065U
- Authority
- CN
- China
- Prior art keywords
- dds
- connects
- frequency synthesizer
- output
- vco
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The utility model discloses a double DDS (Direct Digital Frequency Synthesizer) and PLL frequency synthesizer, relates to the electronic technology field and aims to solve technical problems of high cost, unsatisfactory key qualifications in stray and phase noise and the like of a prior broadband fine stepping frequency synthesizer. In the utility model, an input terminal of a frequency multiplier connects with an output terminal of a constant temperature crystal oscillator. An output terminal of the frequency multiplier connects with a DDS 1, a first input terminal of a phase discriminator, a VCO (Voltage-Controlled Oscillator), an amplifier and a filter in series successively and then outputs. An input terminal of a DDS 2 connects with a second input terminal of the phase discriminator while an output terminal of the DDS 2 connects with a second output terminal of the VCO.
Description
Technical field
The utility model relates to electronic technology field, particularly a kind of frequency synthesizer that is applied to fields such as microwave communication, electronic equipment.
Background technology
Traditional DDS+PLL phase-lock mode can be realized the frequency hopping source design of little stepping, but limited by frequency range and high-frequency, and the limited of its application arranged; And the mode of PLL+DDS under the thin stepping situation, if bandwidth is too wide, can produce the near-end spurious signal, is difficult to filtering.
At present domestic frequency source in the thin stepping in broadband realizes generally adopting YIG oscillator to realize, but this scheme cost is too high, is unfavorable for large-scale production.And there is weak point in the hybrid frequency synthesis mode on the key index of spuious and phase noise.Therefore in the market broadband, thin stepping combined product frequently and is difficult to satisfy existing partly system requirements.
Summary of the invention
The utility model is intended to solve technical problem such as thin step frequency synthesizer cost key technical index high, spuious and phase noise in traditional broadband is undesirable, so that two DDS and the PLL frequency synthesizer with advantages such as production cost are low, key technical index is good, failure rate is low, safe and reliable to be provided.
The purpose of the utility model realizes through following technical scheme.
Two DDS of the utility model and PLL frequency synthesizer; The input of frequency multiplier connects the output of constant-temperature crystal oscillator, and its output is connected in series outwards output behind first input end, voltage controlled oscillator VCO, amplifier and the filter of Direct Digital Synthesizer one DDS1, phase discriminator in order; The input of Direct Digital Synthesizer two DDS2 connects second input of phase discriminator, and its output connects second output of voltage controlled oscillator VCO.
Two DDS of the utility model and PLL frequency synthesizer, wherein said phase discriminator are HMC440.
The beneficial effect of two DDS of the utility model and PLL frequency synthesizer: production cost is low, key technical index is good, failure rate is low, safe and reliable.
Description of drawings
The circuit theory diagrams of Fig. 1 the utility model
Label declaration among the figure:
DDS1 Direct Digital Synthesizer one
DDS2 Direct Digital Synthesizer two
The VCO voltage controlled oscillator
Embodiment
The utility model detailed structure, application principle, effect and effect with reference to accompanying drawing 1, are explained through following execution mode.
Two DDS of the utility model and PLL frequency synthesizer; The input of frequency multiplier connects the output of constant-temperature crystal oscillator, and its output is connected in series outwards output behind first input end, voltage controlled oscillator VCO, amplifier and the filter of Direct Digital Synthesizer one DDS1, phase discriminator in order; The input of Direct Digital Synthesizer two DDS2 connects second input of phase discriminator, and its output connects second output of voltage controlled oscillator VCO.Phase discriminator is HMC440.
Two DDS of the utility model and PLL frequency synthesizer adopt the reference of constant-temperature crystal oscillator frequency multiplication as DDS; The output signal of DDS can not produce the deterioration of phase noise theoretically to input signal, the realization that therefore frequency of output is just successful the function of frequency hopping and optional frequency selection; Phase discriminator adopts at present the very low HMC440 in phase demodulation base on the market; Through the active power filtering loop, locking VCO, the output signal coupling part of VCO is amplified through reverse isolation; Reference signal as interior slotting DDS; The interior DDS of inserting exports fixed frequency, has successfully realized the thin stepping frequency hopping of output signal, exports signal and carries out phase demodulation with reference to DDS.
Owing to adopt the hybrid frequency synthesis mode of DDS+ (PLL+DDS), the utlity model has advantages such as volume is little, phase noise is low, spuious inhibition height, good stability.
Claims (2)
1. two DDS and PLL frequency synthesizer; It is characterized in that: the input of frequency multiplier connects the output of constant-temperature crystal oscillator, and its output is connected in series outwards output behind first input end, voltage controlled oscillator (VCO), amplifier and the filter of Direct Digital Synthesizer one (DDS1), phase discriminator in order; The input of Direct Digital Synthesizer two (DDS2) connects second input of phase discriminator, and its output connects second output of voltage controlled oscillator (VCO).
2. couple DDS as claimed in claim 1 and PLL frequency synthesizer is characterized in that: described phase discriminator is HMC440.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011202574977U CN202168065U (en) | 2011-07-20 | 2011-07-20 | Double DDS and PLL frequency synthesizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011202574977U CN202168065U (en) | 2011-07-20 | 2011-07-20 | Double DDS and PLL frequency synthesizer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202168065U true CN202168065U (en) | 2012-03-14 |
Family
ID=45803866
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011202574977U Expired - Fee Related CN202168065U (en) | 2011-07-20 | 2011-07-20 | Double DDS and PLL frequency synthesizer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202168065U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109274337A (en) * | 2017-07-18 | 2019-01-25 | 中兴通讯股份有限公司 | A kind of method and device handling clock signal |
-
2011
- 2011-07-20 CN CN2011202574977U patent/CN202168065U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109274337A (en) * | 2017-07-18 | 2019-01-25 | 中兴通讯股份有限公司 | A kind of method and device handling clock signal |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN204180052U (en) | The phase-locked frequency hopping synthesizer of a kind of X-band shift frequency | |
| CN102769462A (en) | Direct digital frequency phase-locked frequency multiplier circuit | |
| CN101510777A (en) | Phase synchronization circuit and receiver having the same | |
| CN101136631B (en) | Frequency synthesizer and frequency synthesis method | |
| CN201008145Y (en) | Rubidium atom frequency scale digital phase-locked frequency multiplier | |
| CN104135280A (en) | Frequency source circuit with harmonic generation and frequency mixing | |
| CN201298839Y (en) | Phaselocking frequency multiplier of rubidium frequency scale | |
| CN203632644U (en) | Novel X wave band frequency synthesizer based on DDS and PLL | |
| CN103414463A (en) | Resonant frequency tracking circuit | |
| CN104393871A (en) | Frequency synthesizer for driving phase-locked loop after up-converting DDS | |
| CN201541235U (en) | Microwave signal source module | |
| CN102006060A (en) | Harmonic phase locking frequency source and phase locking method thereof | |
| CN202168065U (en) | Double DDS and PLL frequency synthesizer | |
| CN103326718B (en) | A kind of rf chain of rubidium frequency standard | |
| CN102163970A (en) | Phase-locked dielectric resonator oscillator with low phase noise at microwave frequency band | |
| CN201878129U (en) | Microwave frequency band low-phase noise locking phase medium oscillator | |
| CN202663383U (en) | S-band coherence multi-frequency signal source | |
| CN204046573U (en) | Parallel DDS encourages PLL frequency synthesizer | |
| CN105577182A (en) | W-band low phase noise phase-locked source and use method thereof | |
| CN205693648U (en) | A kind of digital servo-control modulator multiplier for Rb atom frequency marking | |
| CN201985842U (en) | Local frequency generation circuit for microwave bandwidth folding receiver | |
| CN204615807U (en) | A kind of digital phase-locked frequency multiplier device | |
| CN204948028U (en) | A kind of new type inverter | |
| CN207339815U (en) | Ultralow phase noise frequency synthesizer | |
| CN208190632U (en) | When frequency module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20120314 Termination date: 20180720 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |