CN204046573U - Parallel DDS encourages PLL frequency synthesizer - Google Patents
Parallel DDS encourages PLL frequency synthesizer Download PDFInfo
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- CN204046573U CN204046573U CN201420324338.8U CN201420324338U CN204046573U CN 204046573 U CN204046573 U CN 204046573U CN 201420324338 U CN201420324338 U CN 201420324338U CN 204046573 U CN204046573 U CN 204046573U
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- frequency
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- synthesizer
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- digital synthesizer
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Abstract
The utility model encourages PLL frequency synthesizer for parallel DDS, solves the spuious difference that oneself has the thin Step Frequency in frequency synthesizer broadband, the problem that output frequency is lower and phase noise is high.Constant temperature crystal (1) is as the reference clock of frequency synthesizer, the reference clock of the 1st Direct Digital Synthesizer (3) is obtained through frequency multiplier (2) frequency multiplication, the output of the 1st Direct Digital Synthesizer (3) is as the reference input of phase discriminator (4), the output of phase discriminator (4) connects the input of voltage controlled oscillator (5), output one tunnel of voltage controlled oscillator (5) is as winding signal, winding signal exports through frequency divider (9) frequency division, as the reference clock of the 2nd Direct Digital Synthesizer (6), the output of the 2nd Direct Digital Synthesizer (6) is as the radio-frequency input signals of phase discriminator (4), another road output signal of voltage controlled oscillator (5) enters local oscillator filter (8) after the 1st amplifier (7) carries out power amplification, filtered signal amplifies output through the 2nd amplifier (10).
Description
technical field:
The utility model is relevant with frequency synthesizer.
background technology:
Traditional DDS+PLL phase-lock mode can realize the frequency hopping synthesizer design of little stepping, but limits by frequency range and high-frequency, has the limited of its application; And the mode of PLL+DDS, in thin Step Frequency situation, if bandwidth is too wide, near-end spurious signal can be produced, be difficult to filtering.
The domestic frequency source in the thin stepping in broadband realizes generally adopting YIG oscillator to realize at present, but this scheme cost is too high, is unfavorable for large-scale production.And hybrid frequency synthesis mode, Shortcomings part on the key index of spuious and phase noise.Therefore broadband in the market, thin Step Frequency are combined product and are difficult to meet existing part system requirement.
utility model content:
The purpose of this utility model is to provide that a kind of production cost is low, failure rate is low, and in thin Step Frequency situation, the high purity of output spectrum, the parallel DDS that phase noise is low encourages PLL frequency synthesizer.
The utility model is achieved in that
Parallel DDS encourages PLL frequency synthesizer, constant temperature crystal 1 is as the reference clock of frequency synthesizer, the reference clock of the 1st Direct Digital Synthesizer 3 is obtained through frequency multiplier 2 frequency multiplication, the output of the 1st Direct Digital Synthesizer 3 is as the reference input of phase discriminator 4, the output of phase discriminator 4 connects the input of voltage controlled oscillator 5, output one tunnel of voltage controlled oscillator 5 is as winding signal, winding signal exports through frequency divider 9 frequency division, as the reference clock of the 2nd Direct Digital Synthesizer 6, the output of the 2nd Direct Digital Synthesizer 6 is as the radio-frequency input signals of phase discriminator 4, another road output signal of voltage controlled oscillator 5 enters local oscillator filter 8 after the 1st amplifier 7 carries out power amplification, filtered signal amplifies output through the 2nd amplifier 10.
Constant temperature crystal 1 is GO23B-488A9Y-100, frequency multiplier 2 is AMK-2-13+, 1st Direct Digital Synthesizer 3 is AD9954, phase discriminator 4 is HMC440QS16G, and voltage controlled oscillator 5 is HMC586LC4B, and frequency divider 9 is HMC434,2nd Direct Digital Synthesizer 6 is AD9858,1st amplifier 7 is HMC788LP2E, and local oscillator filter 8 is 4-8 cavity body filters, and the 2nd amplifier 10 is HMC788LP2E.
The two DDS of the utility model and PLL frequency synthesizer adopt constant-temperature crystal oscillator frequency multiplication as the reference of Direct Digital Synthesizer DDS, the output signal of Direct Digital Synthesizer DDS can not produce the deterioration of phase noise theoretically to input signal, the frequency therefore exported just successfully achieves the function of frequency hopping and optional frequency selection; Phase discriminator adopts the HMC440 that phase demodulation base is very low on the market at present, by active power filtering loop, locking voltage controlled oscillator VCO, an output signal coupling part for voltage controlled oscillator VCO is amplified through reverse isolation, as the reference signal of interpolation DDS, interpolation DDS exports fixed frequency, successfully achieves the thin stepping frequency hopping of output signal, and output signal carries out phase demodulation with reference to DDS.
The beneficial effects of the utility model are as follows:
Of the present utility model couple of DDS and PLL frequency synthesizer, the input of frequency multiplier connects the output of constant-temperature crystal oscillator, and its output is connected in series the 1st Direct Digital Synthesizer DDS, the first input end of phase discriminator, voltage controlled oscillator VCO, amplifier and the backward outer output of filter in turn; The input of the 2nd Direct Digital Synthesizer DDS connects the second input of phase discriminator, and its output connects the second output of voltage controlled oscillator VCO.The two DDS of the utility model and PLL frequency synthesizer adopt constant-temperature crystal oscillator frequency multiplication as the reference of DDS, the output signal of DDS can not produce the deterioration of phase noise theoretically to input signal, the frequency therefore exported just successfully achieves the function of frequency hopping and optional frequency selection; Phase discriminator adopts the HMC440 that phase demodulation base is very low on the market at present, by active power filtering loop, locking VCO, an output signal coupling part of VCO is amplified through reverse isolation, as the reference signal of interpolation DDS, interpolation DDS exports fixed frequency, successfully achieves the thin stepping frequency hopping of output signal, and output signal carries out phase demodulation with reference to DDS.
The production cost of the two DDS of the utility model and PLL frequency synthesizer is low, key technical index is excellent, failure rate is low, safe and reliable.
In experimental temperature scope: in-40 ± 3 DEG C ~+85 DEG C ± 2 DEG C, with tests such as frequency spectrograph FSU-26.5GHz
,it is little that embodiment exports noise floor, achieves following technical indicator
1. constant-temperature crystal oscillator: 100MHz, input power >=7dBm; Make an uproar≤-145dBc/Hz@1KHz mutually;
2. output frequency: 4 ~ 8GHz, power output: >=15dBm;
3. phase noise
≤-95dBc/Hz@1KHz；
≤-100dBc/Hz@10KHz；
≤-105dBc/Hz@100KHz；
1. clutter recognition: >=+65dBc;
2. frequency hopping stepping: 100Hz.
accompanying drawing illustrates:
Fig. 1 is the utility model circuit theory diagrams.
embodiment:
Parallel DDS encourages PLL frequency synthesizer, constant temperature crystal 1 is as the reference clock of frequency synthesizer, the reference clock of the 1st Direct Digital Synthesizer 3 is obtained through frequency multiplier 2 frequency multiplication, the output of the 1st Direct Digital Synthesizer 3 is as the reference input of phase discriminator 4, the output of phase discriminator 4 connects the input of voltage controlled oscillator 5, output one tunnel of voltage controlled oscillator 5 is as winding signal, winding signal exports through frequency divider 9 frequency division, as the reference clock of the 2nd Direct Digital Synthesizer 6, the output of the 2nd Direct Digital Synthesizer 6 is as the radio-frequency input signals of phase discriminator 4, another road output signal of voltage controlled oscillator 5 enters local oscillator filter 8 after the 1st amplifier 7 carries out power amplification, filtered signal amplifies output through the 2nd amplifier 10.
Constant temperature crystal 1 is GO23B-488A9Y-100, frequency multiplier 2 is AMK-2-13+, 1st Direct Digital Synthesizer 3 is AD9954, phase discriminator 4 is HMC440QS16G, and voltage controlled oscillator 5 is HMC586LC4B, and frequency divider 9 is HMC434,2nd Direct Digital Synthesizer 6 is AD9858,1st amplifier 7 is HMC788LP2E, and local oscillator filter 8 is 4-8 cavity body filters, and the 2nd amplifier 10 is HMC788LP2E.
Claims (2)
1. parallel DDS encourages PLL frequency synthesizer, it is characterized in that the reference clock of constant temperature crystal (1) as frequency synthesizer, the reference clock of the 1st Direct Digital Synthesizer (3) is obtained through frequency multiplier (2) frequency multiplication, the output of the 1st Direct Digital Synthesizer (3) is as the reference input of phase discriminator (4), the output of phase discriminator (4) connects the input of voltage controlled oscillator (5), output one tunnel of voltage controlled oscillator (5) is as winding signal, winding signal exports through frequency divider (9) frequency division, as the reference clock of the 2nd Direct Digital Synthesizer (6), the output of the 2nd Direct Digital Synthesizer (6) is as the radio-frequency input signals of phase discriminator (4), another road output signal of voltage controlled oscillator (5) enters local oscillator filter (8) after the 1st amplifier (7) carries out power amplification, filtered signal amplifies output through the 2nd amplifier (10).
2. parallel DDS according to claim 1 encourages PLL frequency synthesizer, it is characterized in that constant temperature crystal (1) is GO23B-488A9Y-100, frequency multiplier (2) is AMK-2-13+, 1st Direct Digital Synthesizer (3) is AD9954, phase discriminator (4) is HMC440QS16G, voltage controlled oscillator (5) is HMC586LC4B, frequency divider (9) is HMC434, 2nd Direct Digital Synthesizer (6) is AD9858, 1st amplifier (7) is HMC788LP2E, local oscillator filter (8) is 4-8 cavity body filters, 2nd amplifier (10) is HMC788LP2E.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420324338.8U CN204046573U (en) | 2014-06-18 | 2014-06-18 | Parallel DDS encourages PLL frequency synthesizer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420324338.8U CN204046573U (en) | 2014-06-18 | 2014-06-18 | Parallel DDS encourages PLL frequency synthesizer |
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| Publication Number | Publication Date |
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| CN204046573U true CN204046573U (en) | 2014-12-24 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201420324338.8U Expired - Fee Related CN204046573U (en) | 2014-06-18 | 2014-06-18 | Parallel DDS encourages PLL frequency synthesizer |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104868911A (en) * | 2015-05-13 | 2015-08-26 | 中国电子科技集团公司第四十一研究所 | Broadband phase-locked frequency synthesis circuit |
| CN108512549A (en) * | 2018-06-07 | 2018-09-07 | 贵州航天天马机电科技有限公司 | A kind of Frequency Hopping Synthesizer |
-
2014
- 2014-06-18 CN CN201420324338.8U patent/CN204046573U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104868911A (en) * | 2015-05-13 | 2015-08-26 | 中国电子科技集团公司第四十一研究所 | Broadband phase-locked frequency synthesis circuit |
| CN104868911B (en) * | 2015-05-13 | 2017-08-25 | 中国电子科技集团公司第四十一研究所 | broadband phase locking frequency synthesis circuit |
| CN108512549A (en) * | 2018-06-07 | 2018-09-07 | 贵州航天天马机电科技有限公司 | A kind of Frequency Hopping Synthesizer |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20141224 Termination date: 20190618 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |