CN204948028U

CN204948028U - A kind of new type inverter

Info

Publication number: CN204948028U
Application number: CN201520697480.1U
Authority: CN
Inventors: 肖顺进; 杨帆; 徐鑫
Original assignee: FUJIAN LIANTUO TECHNOLOGY CO LTD
Current assignee: FUJIAN LIANTUO TECHNOLOGY CO LTD
Priority date: 2015-09-10
Filing date: 2015-09-10
Publication date: 2016-01-06
Anticipated expiration: 2025-09-10

Abstract

The utility model relates to communication system, a kind of new type inverter is provided, comprise frequency mixer, intermediate frequency amplifier, medium/Surface Acoustic Wave Filter, power amplifier, PLL phase-locked loop chip, single-chip microcomputer and 10 transcoding switches, described frequency mixer is connected with PLL phase-locked loop chip with radio-frequency (RF) signal input end respectively, described single-chip microcomputer is connected with 10 transcoding switches with PLL phase-locked loop chip respectively, described mixer output is connected with medium/Surface Acoustic Wave Filter input through intermediate frequency amplifier, described medium/Surface Acoustic Wave Filter output is connected with RF signal output through power amplifier.

Description

A kind of new type inverter

Technical field

The utility model relates to communication system, particularly a kind of new type inverter.

Background technology

Along with the development of the communications field, the communication network of different systems different frequency range gets more and more, especially in private network field, frequency is numerous and diverse, applying unit is many especially, and the signal in space is increasing, thus needs to carry out frequency conversion shift frequency to realize the communication between multi signal multiband compound.Existing frequency converter is adopt outside frequency division pattern and mimotope to select mode substantially, and the frequency shift mode of fixing local oscillator, its advantage: without the need to software support, simplicity of design; Shortcoming: working stability degree is low, working frequency points is too single, and reliability is low, improve its stability then with high costs, complex structure.

Utility model content

Therefore, for above-mentioned problem, the utility model proposes the new type inverter that a kind of structure is simple, cost is low, stability is high, reliability is high.

For solving this technical problem, the utility model takes following scheme: a kind of new type inverter, comprise frequency mixer, intermediate frequency amplifier, medium/Surface Acoustic Wave Filter, power amplifier, PLL phase-locked loop chip, single-chip microcomputer and 10 transcoding switches, described frequency mixer is connected with PLL phase-locked loop chip with radio-frequency (RF) signal input end respectively, described single-chip microcomputer is connected with 10 transcoding switches with PLL phase-locked loop chip respectively, described mixer output is connected with medium/Surface Acoustic Wave Filter input through intermediate frequency amplifier, described medium/Surface Acoustic Wave Filter output is connected with RF signal output through power amplifier.

Further improvement, the external tapping of described 10 transcoding switches is also provided with PLL phase-locked loop chip losing lock indicating circuit.

By adopting preceding solution, the beneficial effects of the utility model are: by the mode adopting 10 transcoding switches through single-chip microcomputer, PLL phase-locked loop chip to be arranged to local frequency, namely the sequential relationship curve that provided with PLL phase-locked loop chip by single-chip microcomputer of 10 transcoding switches and algorithm thereof are for PLL phase-locked loop write clock (CLK), data (Data), the clock signal of enable (LE), PLL phase-locked loop and loop filter circuit and voltage controlled oscillator (VCO) form closed-loop, when after loop-locking, this PLL phase-locked loop chip can provide an instructed voltage locked (LD), when microprocessor detect is to this voltage, being considered as this circuit is lock-out state, just no longer for PLL phase-locked loop provides corresponding clock signal, its outside in frequency converter module just can be adjusted the frequency of frequency converter module, method for designing is simple, be easy to realize, be convenient to batch production and reduce costs, reliability is high.

Accompanying drawing explanation

Fig. 1 is the theory diagram of the utility model embodiment;

Fig. 2 is the Frequency Locking sequential chart of the PLL phase-locked loop chip of the utility model embodiment.

Embodiment

Now with embodiment, the utility model is further illustrated by reference to the accompanying drawings.

With reference to figure 1, new type inverter of the present utility model, comprise frequency mixer 1, intermediate frequency amplifier 2, medium/Surface Acoustic Wave Filter 3, power amplifier 4, PLL phase-locked loop chip 5, single-chip microcomputer 6 and 10 transcoding switches 7, described PLL phase-locked loop chip 5 is for being integrated with data latches, frequency multiplier circuit, the local oscillation circuit that phase discriminator etc. are integrated, described frequency mixer 1 is connected with PLL phase-locked loop chip 5 with radio-frequency (RF) signal input end respectively, described single-chip microcomputer 6 is connected with 10 transcoding switches 7 with PLL phase-locked loop chip 5 respectively, described frequency mixer 1 output is connected with medium/Surface Acoustic Wave Filter 3 input through intermediate frequency amplifier 2, described medium/Surface Acoustic Wave Filter 3 output is connected with RF signal output through power amplifier 4, the external tapping of described 10 transcoding switches 7 is also provided with the losing lock indicating circuit of PLL phase-locked loop chip 5.

Operation principle: the local oscillation signal that radiofrequency signal produces with PLL phase-locked loop chip 5 after radio-frequency (RF) signal input end (i.e. RFin port) is input to the mixting circuit 1 of this frequency converter is combined, by forming the signal of the frequency of needs after mixing, the selected operational frequency bandwidth that needs of medium/Surface Acoustic Wave Filter 3 is sent into and after local frequency is effectively suppressed after being amplified by intermediate frequency amplifier 2, export through RF signal output (i.e. RFout port) after being amplified by power amplifier 4 again, the local oscillation signal that wherein PLL phase-locked loop chip 5 exports is exported through single-chip microcomputer 6 control PLL phase-locked loop chip 5 by 10 transcoding switches 7, namely the sequential relationship curve (with reference to figure 2) that provided with PLL phase-locked loop chip 5 by single-chip microcomputer 6 of 10 transcoding switches 7 and algorithmic formula one thereof are PLL phase-locked loop write clock (CLK), data (Data), the clock signal of enable (LE), PLL phase-locked loop and loop filter circuit and voltage controlled oscillator (VCO) form closed-loop, when after loop-locking, this PLL phase-locked loop chip 5 can provide an instructed voltage locked (LD), when single-chip microcomputer 6 detects this voltage, being considered as this circuit is lock-out state, just no longer for PLL phase-locked loop chip 5 provides corresponding clock signal.

With reference to figure 2, the clock signal of single-chip microcomputer 6 to be the sequential relationship curve that provides with PLL phase-locked loop chip 5 and following algorithmic formula one be PLL phase-locked loop write clock (CLK), data (Data), enable (LE).

Algorithmic formula one:

The utility model arranges the mode of local frequency to PLL phase-locked loop chip through single-chip microcomputer by employing 10 transcoding switches, namely the sequential relationship curve that provided with PLL phase-locked loop chip by single-chip microcomputer of 10 transcoding switches and algorithm thereof are for PLL phase-locked loop write clock (CLK), data (Data), the clock signal of enable (LE), PLL phase-locked loop and loop filter circuit and voltage controlled oscillator (VCO) form closed-loop, when after loop-locking, this PLL phase-locked loop chip can provide an instructed voltage locked (LD), when microprocessor detect is to this voltage, being considered as this circuit is lock-out state, just no longer for PLL phase-locked loop provides corresponding clock signal, its outside in frequency converter module just can be adjusted the frequency of frequency converter module, method for designing is simple, be easy to realize, be convenient to batch production and reduce costs, reliability is high.

Although specifically show in conjunction with preferred embodiment and describe the utility model; but those skilled in the art should be understood that; not departing from the spirit and scope of the present utility model that appended claims limits; can make a variety of changes the utility model in the form and details, be protection range of the present utility model.

Claims

1. a new type inverter, it is characterized in that: comprise frequency mixer, intermediate frequency amplifier, medium/Surface Acoustic Wave Filter, power amplifier, PLL phase-locked loop chip, single-chip microcomputer and 10 transcoding switches, described frequency mixer is connected with PLL phase-locked loop chip with radio-frequency (RF) signal input end respectively, described single-chip microcomputer is connected with 10 transcoding switches with PLL phase-locked loop chip respectively, described mixer output is connected with medium/Surface Acoustic Wave Filter input through intermediate frequency amplifier, and described medium/Surface Acoustic Wave Filter output is connected with RF signal output through power amplifier.

2. a kind of new type inverter according to claim 1, is characterized in that: the external tapping of described 10 transcoding switches is also provided with PLL phase-locked loop chip losing lock indicating circuit.