CN202085390U - Three-layer security label PCB - Google Patents
Three-layer security label PCB Download PDFInfo
- Publication number
- CN202085390U CN202085390U CN2011201065274U CN201120106527U CN202085390U CN 202085390 U CN202085390 U CN 202085390U CN 2011201065274 U CN2011201065274 U CN 2011201065274U CN 201120106527 U CN201120106527 U CN 201120106527U CN 202085390 U CN202085390 U CN 202085390U
- Authority
- CN
- China
- Prior art keywords
- central layer
- core plate
- parallel
- pcb board
- layers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Abstract
The utility model discloses a three-layer security label PCB (Printed Circuit Board) comprising a light panel and a core plate arranged in parallel, the two side surfaces of the core plate are printed with ink and circuits, and an insulation layer is further arranged in parallel between the light panel and the core plate. The process not only meets the requirement for the precision of the chip binding location, but also enables the surface of the PCB to be subject to complete gold plating. Moreover, due to the addition of a solder resist ink coating to the core plate, the cost of surface treatment (electroless gold plating) is greatly reduced.
Description
Technical field
The utility model relates to a kind of pcb board, relates in particular to a kind of three layers of antifalsification label pcb board.
Background technology
At present, the core technology of antifalsification label is mainly the chip binding, so chip binding status requirement is very accurate, and traditional three ply board can't reach desired accurate accuracy, also can't be very accurate fixing.In addition, traditional process is made three layers of pcb board technology, and the pit that can form the 0.3mm degree of depth owing to pad and plate face causes this operation part of surface treatment (chemical gilding) can't be gold-plated.
The utility model content
In order to overcome above-mentioned defective, the utility model provides a kind of three layers of antifalsification label pcb board and preparation technology thereof, this technology not only can satisfy the required precision of chip binding position, but and surface treatment overgild, and central layer once added the welding resistance ink coating, can reduce the cost of surface treatment (chemical gilding) greatly.
The utility model for the technical scheme that solves its technical problem and adopt is: a kind of three layers of antifalsification label pcb board, it comprises tabula rasa and the central layer that is arranged in parallel, the both side surface of described central layer all is printed with printing ink and circuit, the also parallel layer insulating that is provided with between described tabula rasa and the described central layer.
As further improvement of the utility model, described insulating barrier is made for the expoxy glass cloth material.
As further improvement of the utility model, described tabula rasa is that glass fiber material is made.
The beneficial effects of the utility model are: in the structural design of this three ply board, the 3rd layer differs the height of 0.3MM with the pad face, is the installation site of chip binding just in time, can accomplish accurate fixing.
Description of drawings
Fig. 1 is the utility model structural representation.
Embodiment
A kind of three layers of antifalsification label pcb board, it comprises tabula rasa 1 and the central layer 2 that is arranged in parallel, the both side surface of described central layer all is printed with printing ink and circuit, the also parallel layer insulating 3 that is provided with between described tabula rasa and the described central layer.
Described insulating barrier is made for the expoxy glass cloth material.
Described tabula rasa is that glass fiber material is made.
The preparation technology of above-mentioned three layers of antifalsification label pcb board may further comprise the steps:
1. central layer is opened material, promptly as required substrate is cut into the central layer of setting size;
2. central layer is holed, and the holeization;
3. in the two sides of central layer circuit is set respectively;
4. central layer is electroplated, promptly the monoblock central layer is carried out copper facing;
5. central layer is carried out etching, promptly the circuit diagram that the central layer surface is needed shows;
6. welding resistance promptly is coated with welding resistance printing ink on central layer;
7. central layer is carried out surface treatment;
8. above-mentioned central layer, insulating barrier and tabula rasa are pressed to together in order, form whole plate;
9. the secondary welding resistance is carried out in the two sides of above-mentioned whole plate;
10. holed in the two sides of above-mentioned whole plate;
Claims (3)
1. three layers of antifalsification label pcb board, it is characterized in that: it comprises tabula rasa (1) and the central layer (2) that is arranged in parallel, the both side surface of described central layer all is printed with printing ink and circuit, the also parallel layer insulating (3) that is provided with between described tabula rasa and the described central layer.
2. three layers of antifalsification label pcb board according to claim 1 is characterized in that: described insulating barrier is made for the expoxy glass cloth material.
3. three layers of antifalsification label pcb board according to claim 1 and 2 is characterized in that: described tabula rasa is that glass fiber material is made.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011201065274U CN202085390U (en) | 2011-04-13 | 2011-04-13 | Three-layer security label PCB |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011201065274U CN202085390U (en) | 2011-04-13 | 2011-04-13 | Three-layer security label PCB |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202085390U true CN202085390U (en) | 2011-12-21 |
Family
ID=45346002
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2011201065274U Expired - Fee Related CN202085390U (en) | 2011-04-13 | 2011-04-13 | Three-layer security label PCB |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202085390U (en) |
-
2011
- 2011-04-13 CN CN2011201065274U patent/CN202085390U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20111221 Termination date: 20140413 |