The utility model content
Because the above-mentioned defective of prior art, technical problem to be solved in the utility model provides a kind of D genus audio power amplifier that is used to suppress noise, to guarantee in the zero crossing distortion and crosstalk noise that suppress the D genus audio power amplifier, suppressing the switching on and shutting down noise (POP and CLICK) of D genus audio power amplifier.
For achieving the above object, the utility model provides a kind of D genus audio power amplifier, comprises integrator, comparator, driver, power switch component at least, and feedback network, also comprises voltage-controlled delay circuit; The input input of described voltage-controlled delay circuit is as the square wave with reference to ripple, and the control end input control signal of described voltage-controlled delay circuit, the output of described voltage-controlled delay circuit are exported the time-delay square wave, and described time-delay square wave is the described square wave that has produced a time-delay; Described square wave is imported the first reference wave input of described integrator, and described time-delay square wave is imported the second reference wave input of described integrator; First output of described integrator is connected with the in-phase input end of first comparator, and second output of described integrator is connected with the in-phase input end of second comparator, and reference voltage is imported the inverting input of described first comparator, described second comparator; Or the input of the input of described voltage-controlled delay circuit is as the triangular wave with reference to ripple, the control end input control signal of described voltage-controlled delay circuit, the output output time-delay triangular wave of described voltage-controlled delay circuit, described time-delay triangular wave is the described triangular wave that has produced a time-delay; Described triangular wave is imported the inverting input of described first comparator, and described time-delay square wave is imported the inverting input of described second comparator; First output of described integrator is connected with the in-phase input end of first comparator, and second output of described integrator is connected with the in-phase input end of second comparator; Or the input of described voltage-controlled delay circuit is connected with the output of described first comparator, the control end input control signal of described voltage-controlled delay circuit, and the output of described voltage-controlled delay circuit is connected with the input of first driver; The output of described second comparator is connected with the input of second driver.
Preferably, described voltage-controlled delay circuit comprises time delay resistance, delay capacitor, and when described D genus audio power amplifier was worked, the size of described time-delay was relevant with described time delay resistance and described delay capacitor:
Δ t is that described time-delay, Rd are that described time delay resistance, Cd are described delay capacitor; When described D genus audio power amplifier On/Off, described time-delay is approximately zero.
Preferably, described voltage-controlled delay circuit also comprises first switch element, and described first switch element is in parallel with described time delay resistance; When the control end of described voltage-controlled delay circuit was low level, described first switch element was closed, and made described time delay resistance short circuit; When the control end of described voltage-controlled delay circuit was high level, described first switch element was opened, and made described time delay resistance open circuit.
Preferably, described voltage-controlled delay circuit also comprises first electric capacity, and first end of described first electric capacity is connected with the control end of described first switch element, and second end of described first electric capacity is connected with ground.
Preferably, described first switch element is a metal-oxide-semiconductor.
The utility model provides, and a kind of D genus audio power amplifier that is used to suppress noise has following technique effect: owing to set up voltage-controlled delay circuit, thereby this voltage-controlled delay circuit makes and produces zero crossing distortion and the crosstalk noise that time-delay has reduced the D genus audio power amplifier between two drive signals of D genus audio power amplifier; Thereby this voltage-controlled delay circuit makes two drive signals of D genus audio power amplifier delay time when switching on and shutting down is zero switching on and shutting down noise (POP and CLICK) and the THD+N (total harmonic distortion plus noise) that has reduced the D genus audio power amplifier.The control end signal becomes high level from low level during start.Time-delay Δ t is approximately zero when beginning, and has only through discharging and recharging the Δ t that delays time after the time T s just to reach preset time T d gradually.Therefore start shooting moment, pulse-width signal PWM1, the size of the relative time delay between the PWM2 is approximately zero.Owing to avoided switching power tube at start moment output differential signal, thereby suppressed the switching on and shutting down noise (POP and CLICK) of D genus audio power amplifier.After start reached preset time T d gradually through certain hour time-delay Δ t, pulse-width signal PWM1 had the time-delay Δ t of preset time T d between the PWM2, thereby has reduced the zero crossing distortion and the crosstalk noise of amplifier.Control end control signal becomes low level from high level during shutdown, and time-delay Δ t can become approximate zero very soon, has suppressed the switching on and shutting down noise (POP and CLICK) of D genus audio power amplifier thus.Owing to use the carrier signal of square-wave modulation signal as audio input signal, saved the circuit for generating triangular wave in the D genus audio power amplifier in the prior art, saved area of chip, saved the chip manufacturing cost.
Be described further below with reference to the technique effect of accompanying drawing, to understand the purpose of this utility model, feature and effect fully design of the present utility model, concrete structure and generation.
Embodiment
Embodiment 1:
As shown in Figure 3, according to a specific embodiment of D genus audio power amplifier of the present utility model, this D genus audio power amplifier comprises integrator 20, comparator, driver, power switch component, and feedback network.This D genus audio power amplifier also comprises voltage-controlled delay circuit 5, thereby is used for the crosstalk noise and the switching on and shutting down noise of the time-delay inhibition system of control signal.
The input input of voltage-controlled delay circuit 5 is as the square wave CLK with reference to ripple, and the control end control input control signal of voltage-controlled delay circuit 5, the output of voltage-controlled delay circuit 5 are exported the time-delay square wave, and the time-delay square wave is the square wave CLK that has produced a time-delay.The first reference wave input of square wave input integral device 20, the second reference wave input of time-delay square wave input integral device 20.First output of integrator 20 is connected with the in-phase input end of first comparator 30, and second output of integrator 20 is connected with the in-phase input end of second comparator 31, and reference voltage Vref is imported the inverting input of first comparator 30, second comparator 31.
Audio input signal Vin is through the pre-amplification of preamplifier 10.Audio input signal Vin, square wave CLK, signal VOUTP behind pre-the amplification, VOUTN input integral device produces triangular signal.Triangular signal and reference signal Vref produce corresponding pulse-width signal PWM1, PWM2 respectively after by first comparator 30, second comparator 31.Pulse-width signal PWM1, the duty ratio of PWM2 is all linear with audio input signal Vin.Pulse-width signal PWM1 produces signal VOUTP by first driver 40, first power switch component; Pulse-width signal PWM2 produces signal VOUTN by second driver 41, second power switch component.In the present embodiment, control signal is control end control
Signal.Voltage-controlled delay circuit 5 is delayed time square wave CLK under the control of control end control signal, thereby makes pulse-width signal PWM1, produces time-delay Δ t between the PWM2.
After the D genus audio power amplifier is opened,, produce between the drive signal that voltage-controlled delay circuit 5 makes the power switch component of winning and the drive signal of second power switch component and delay time through a charging interval; Before the D genus audio power amplifier was closed, through a discharge time, voltage-controlled delay circuit 5 was eliminated the time-delay between the drive signal of the drive signal of the power switch component of winning and second power switch component; When D genus audio power amplifier On/Off, time-delay is approximately zero.
Owing to use the carrier signal of square wave CLK as audio input signal Vin, saved the circuit for generating triangular wave in the D genus audio power amplifier in the prior art, saved area of chip, saved the chip manufacturing cost.
As shown in Figure 4, the voltage-controlled delay circuit 5 of D genus audio power amplifier comprises time delay resistance, delay capacitor, and the size of time-delay is relevant with time delay resistance and delay capacitor:
Δ t is that time delay resistance, Cd are delay capacitor for time-delay, Rd.
In the present embodiment, voltage-controlled delay circuit 5 also comprises first switch element, second switch element.First switch element is metal-oxide-semiconductor MN1, and the second switch element is metal-oxide-semiconductor MP1.Metal-oxide-semiconductor MN1, MP1 is in parallel with time delay resistance.When the control end of voltage-controlled delay circuit 5 is low level, metal-oxide-semiconductor MN1, MP1 closes, and makes time delay resistance Rd short circuit, when the control end of voltage-controlled delay circuit 5 is high level, metal-oxide-semiconductor MN1, MP1 opens, and makes time delay resistance Rd open circuit.
Voltage-controlled delay circuit 5 also comprises first capacitor C 2, second capacitor C 3.First end of first capacitor C 2 is connected with the control end of metal-oxide-semiconductor MP1, and second end of first capacitor C 2 is connected with ground; First capacitor C 2 is used to control charging interval, discharge time of voltage of the control end of metal-oxide-semiconductor MP1.First end of second capacitor C 3 is connected with the control end of metal-oxide-semiconductor MN1, and second end of second capacitor C 3 is connected with ground; First capacitor C 2 is used to control charging interval, discharge time of voltage of the control end of metal-oxide-semiconductor MN1.
As Fig. 4, shown in Figure 5, the control end control signal of voltage-controlled delay circuit 5 and clock signal clk pass through NAND gate, inverter, capacitor C 1, inverter successively, and NAND gate, produce burst pulse CLK1.The grid voltage of voltage control metal-oxide-semiconductor MP1 on first capacitor C 2, the grid voltage of the voltage control metal-oxide-semiconductor MN1 on second capacitor C 3.Control end control signal also control second capacitor C 3 on draw metal-oxide-semiconductor MP3, simultaneously control end control signal is through the drop-down metal-oxide-semiconductor MN3 of inverter controlling.The input end signal In of voltage-controlled delay circuit 5 passes through inverter, time delay resistance Rd, metal-oxide-semiconductor MP1, metal-oxide-semiconductor MN1, delay capacitor Cd successively, and exports the output end signal Out of voltage-controlled delay circuit 5 behind the inverter.Time-delay Δ t between output end signal Out and the input end signal In is controlled.
When control end control signal was low level, the last terminal voltage V2 of first capacitor C 2 pulled down to low level by metal-oxide-semiconductor MN3, opened metal-oxide-semiconductor MP1; The following terminal voltage V3 of second capacitor C 3 opens metal-oxide-semiconductor MN1 by moving high level on the metal-oxide-semiconductor MP3, and is approximate with time delay resistance Rd short circuit, and Δ t ≈ 0 delays time this moment;
When control end control signal became high level, voltage-controlled delay circuit 5 can produce the burst pulse CLK1 that duty ratio is very little, and the duty ratio size of narrow pulsewidth CLK1 is controlled by C1.Burst pulse CLK1 charges to first capacitor C 2 through the unlatching of inverter controlling metal-oxide-semiconductor MP2, and control metal-oxide-semiconductor MN2 is to 3 discharges of second capacitor C.Charging interval Ts is by duty ratio, metal-oxide-semiconductor MP2, metal-oxide-semiconductor MN2, first capacitor C 2 of narrow pulsewidth CLK1, and 3 decisions of second capacitor C.Through behind the charging interval Ts, voltage V2 notch cuttype ground charging gradually rises to Vcc, and voltage V3 notch cuttype ground discharge gradually drops to low level.Voltage V3 on the voltage V2 on first capacitor C 2 and second capacitor C 3 influences corresponding M OS pipe MP1, the size of the conducting resistance of MN1 respectively.Said process can make metal-oxide-semiconductor MN1, and the conducting resistance of MP1 and Rd parallel resistor increase gradually, and delay time Δ t also increases thereupon gradually thus.As final metal-oxide-semiconductor MN1, when MP1 turn-offed, the size of time-delay Δ t was only by time delay resistance Rd and delay capacitor Cd decision.
Control end control signal becomes high level from low level during start.Time-delay Δ t is approximately zero when beginning, and has only through the Δ t that delays time after the charging interval Ts just to reach preset time T d gradually.Therefore start shooting moment, pulse-width signal PWM1, the relative time delay between the PWM2 are approximately zero.Owing to avoided switching power tube at start moment output differential signal, thereby suppressed the switching on and shutting down noise (POP and CLICK) of D genus audio power amplifier.After start reached preset time T d gradually through certain hour time-delay Δ t, pulse-width signal PWM1 had the time-delay Δ t of preset time T d between the PWM2, thereby has reduced the zero crossing distortion and the crosstalk noise of amplifier.Control end control signal becomes low level from high level during shutdown, and time-delay Δ t can become approximate zero very soon, has suppressed the switching on and shutting down noise (POP and CLICK) of D genus audio power amplifier thus.
Owing to set up voltage-controlled delay circuit, thereby this voltage-controlled delay circuit makes and produces zero crossing distortion and the crosstalk noise that time-delay has reduced the D genus audio power amplifier between two drive signals of D genus audio power amplifier; Thereby this voltage-controlled delay circuit makes two drive signals of D genus audio power amplifier delay time when switching on and shutting down is zero switching on and shutting down noise (POP and CLICK) and the THD+N (total harmonic distortion plus noise) that has reduced the D genus audio power amplifier.
In other embodiments, switch element also can be controlled time-delay Δ t by control delay capacitor Cd.
Embodiment 2:
As shown in Figure 6, the circuit structure of present embodiment and embodiment 1 is basic identical, institute's difference is, the input input of voltage-controlled delay circuit 5 is as the triangular wave with reference to ripple, the control end control input control signal of voltage-controlled delay circuit 5, the output output time-delay triangular wave of voltage-controlled delay circuit 5, the time-delay triangular wave is the triangular wave that has produced a time-delay; Triangular wave is imported the inverting input of first comparator 30, and the time-delay square wave is imported the inverting input of second comparator 31; First output of integrator 20 is connected with the in-phase input end of first comparator 30, and second output of integrator 20 is connected with the in-phase input end of second comparator 31;
Embodiment 3:
As shown in Figure 7, the circuit structure of present embodiment and embodiment 1 is basic identical, institute's difference is, the input of voltage-controlled delay circuit 5 is connected with the output of first comparator 30, the control end control input control signal of voltage-controlled delay circuit 5, the output of voltage-controlled delay circuit 5 is connected with the input of first driver 40; The output of second comparator 31 is connected with the input of second driver 41.
More than describe preferred embodiment of the present utility model in detail.The ordinary skill that should be appreciated that this area need not creative work and just can make many modifications and variations according to design of the present utility model.Therefore, all technical staff in the art comply with design of the present utility model on the basis of existing technology by the available technical scheme of logical analysis, reasoning, or a limited experiment, all should be in the determined protection range by claims.