CN202049478U - Checking board of a high-end server controller - Google Patents

Abstract

A checking board of a high-end server controller comprises a first bus, a second bus, an input terminal, an output terminal, a read-only memory (ROM) used for saving the initialization information of the logic of the chip to be checked, and two FPGA (field programmable gate array) chip groups each for loading a controller chip group logic bit stream; each FPGA chip group is respectively connected with the first and the second bus, the ROM and a power supply; the input terminal and the output terminal of each group of FPGA are connected with the input terminal and output terminal. The utility model realizes the huge logic quantity in checking the controller chip of a high-end server by adopting FPGA.

Description

A kind of witness plate of high-end server controller chip

Technical field

The utility model relates to computer realm, is specifically related to a kind of witness plate of high-end server controller chip.

Background technology

Along with the develop rapidly of computer technology and integrated circuit technique, in order to satisfy the needs of socio-economic development, high-performance, highly reliable computer system become one of bottleneck of restriction social development key area.Huge data computation and data analysis, message areas such as complicated pattern analysis and science budget require high to performance of computer systems.Therefore need to make up huge multichannel computer system, so that the better application demand that adapts to current each field, but also be absorbed on the other hand in the multichannel computer system Interworking Technology difficult problem, the design of system interconnect chip group becomes increasingly complex, huge amount of logic and complicated function are embodied as the FPGA(Field-Programmable Gate Array of system's node interconnecting chip, field programmable gate array) the great difficulty brought of checking.

The utility model content

The technical problems to be solved in the utility model provides the huge amount of logic when how to adopt FPGA to realize the checking of high-end server controller chip.

In order to address the above problem, the utility model provides a kind of witness plate of high-end server controller chip, comprising:

First bus, second bus, input terminal, lead-out terminal, be used to preserve the ROM (read-only memory) of the initialization information of chip logic to be verified;

Respectively be used to load two fpga chip groups of a controller chip group logic bit stream;

Each fpga chip group links to each other with described first, second bus, ROM (read-only memory), power supply respectively; Each input end/output terminal of organizing FPGA links to each other with described input/output terminal.

Further, described witness plate also comprises:

Reset button links to each other with the reset pin of the fpga chip of each fpga chip group.

Further, described reset button in comprise following any or appoint several:

Cold reset button, hard reset button, debug reset button, acquiescence reset button, warm reset button.

Further, described witness plate also comprises:

Calibrating terminal links to each other with the test pin of the fpga chip of each fpga chip group.

Further, described witness plate also comprises:

Be used for the logic register of fpga chip is carried out the serial ports of read and write access, link to each other with each fpga chip group.

Further, described witness plate also comprises:

Be used for that fpga chip is carried out the joint test behavior that logic inserts the scan chain built-in self testing and organize jtag interface, link to each other with each fpga chip group.

Further, described witness plate also comprises:

The plug-in unit that connects that is connected with described input, lead-out terminal.

Further, each described fpga chip group comprises:

First fpga chip and second fpga chip;

Described first fpga chip in each group links to each other with described first, second bus and power supply, and input end links to each other with described input terminal, the input end cascade of described second fpga chip in output terminal and this group; The output terminal of described second fpga chip in each group is connected to described lead-out terminal;

First, second fpga chip in each group all links to each other with described ROM (read-only memory), reads or preserve described initialization information.

Further, described ROM (read-only memory) is a plurality of; First, second fpga chip in each group is connected respectively to different ROM (read-only memory), or is connected to identical a plurality of ROM (read-only memory).

Further, described witness plate also comprises:

Be used to carry out the toggle switch of clock selecting, with each the group in first fpga chip link to each other.

The utility model is at the huge logical design of complexity, adopt four high-end FPGA of veneer to realize the logical design of chip, the design of system architecture considers to realize the design of dual controller chipset, veneer adopts four high-end fpga chips, realizes the logic function of two controller chips in the mode of biplate cascade; The abundant test pin of prioritization scheme of the present utility model design, integrated memory controller, and controlled toggle switch, reset button, thus guaranteed that checking work has high operability, satisfy the development effort of high-end server product.

Description of drawings

Fig. 1 is the synoptic diagram of witness plate of the high-end server controller chip of embodiment one.

Embodiment

Below in conjunction with drawings and Examples the technical solution of the utility model is described in detail.

Need to prove that if do not conflict, each feature among the utility model embodiment and the embodiment can mutually combine, all within protection domain of the present utility model.

Embodiment one, and a kind of witness plate of high-end server controller chip as shown in Figure 1, comprising:

First bus, second bus, input terminal, lead-out terminal, be used to preserve the ROM (read-only memory) of the initialization information of chip logic to be verified;

Respectively be used to load two fpga chip groups of a controller chip group logic bit stream;

Each fpga chip group links to each other with described first, second bus, ROM (read-only memory), power supply respectively; Each input end/output terminal of organizing FPGA links to each other with described input/output terminal.

In the present embodiment, described power supply is an external power supply, also can be that this witness plate carries.

In the present embodiment, each described fpga chip group comprises:

First fpga chip and second fpga chip;

Described first fpga chip in each group links to each other with described first, second bus and power supply, and input end links to each other with described input terminal, the input end cascade of described second fpga chip in output terminal and this group; The output terminal of described second fpga chip in each group is connected to described lead-out terminal;

First, second fpga chip in each group all links to each other with described ROM (read-only memory), reads or preserve described initialization information.

In the present embodiment, described ROM (read-only memory) can be for a plurality of, and first, second fpga chip in each group can be connected respectively to different ROM (read-only memory), or is connected to identical a plurality of ROM (read-only memory).

Because the design of high-end server controller chip group is complicated, logic is huge, adopts single high-end fpga chip to be difficult to realize; Present embodiment is considered design factors such as logic function, streamline, modular structure, and on the basis that guarantees test function and performance, witness plate adopts two high-end high capacity fpga chip cascades to realize.Because veneer need be realized two controller chip groups, therefore this witness plate adopts four fpga chips to realize two controller chip groups, described first bus can be used as the checking passage of a controller chip group, and described second bus can be used as the checking passage of another controller chip group.

The functional verification of the huge chip of logic must be satisfied the requirement of system design, and particularly at the high-end server product, its Performance And Reliability is the primary goal of design.At the requirement of reliability, witness plate design low speed Validation Mode, under low-speed mode, the logic function of proofing chip, protocol processes mechanism etc.At performance demands, witness plate design high speed Validation Mode, under fast mode, the streamline mechanism of proofing chip, message processing capability, and the throughput coupling etc.At different rate selection, the witness plate in the present embodiment also comprises:

Be used to carry out the toggle switch of clock selecting, with each the group in first fpga chip link to each other;

By dial-up control FPGA internal clocking logic, select different clocks for use, thereby realize choosing of speed.It is to have the chip logic of FPGA inside to realize that clock generates.Toggle switch only carries out clock selecting, thereby selects between high and low speed, to satisfy different Validation Mode requirements.

The system logic designing requirement adopts the multiple controlling mechanism that resets in the design, guarantee complicated reseting logic.Witness plate in the present embodiment can also comprise:

Reset button links to each other with the reset pin of fpga chip in each fpga chip group.

Described reset button can but be not limited to comprise following any or appoint several:

Cold reset ColdRST button, hard reset HardRST button, debug reset DebugRST button, the acquiescence a plurality of reset button such as DefaultRST button, warm reset SoftRST button that reset.

Each reset button is connected to which pin of fpga chip, and by FPGA internal logic design definition and the decision of FPGA pin assignment, reset pin is assigned to which pin of FPGA, and corresponding reset button just with which pin links to each other.

The multiple control that resets realizes having guaranteed the plate level verification of the multiple reset mechanism of chip.

Controller chip logical design complexity, plate level high-speed signal transmission circuit realize that technical difficulty is big, for guaranteeing chip functions, improve the complexity of witness plate debugging, and the witness plate in the present embodiment can also comprise:

Calibrating terminal links to each other with the test pin of fpga chip in each fpga chip group.

Each calibrating terminal is connected to which pin of fpga chip, and by FPGA internal logic design definition and the decision of FPGA pin assignment, test pin is assigned to which pin of FPGA, and calibrating terminal just with which pin links to each other.

In the present embodiment, supply the test pin of engaged test can reach nearly thousand.

Witness plate in the present embodiment can also comprise:

Be used for the logic register of fpga chip is carried out the serial ports of read and write access, link to each other with each fpga chip group.

Witness plate in the present embodiment can also comprise:

Be used for fpga chip is carried out the JTAG(Joint Test Action Group that logic is inserted the scan chain built-in self testing, joint test behavior tissue) interface, link to each other with each fpga chip group.

Witness plate in the present embodiment can also comprise:

The plug-in unit etc. that connects that is connected with described input, lead-out terminal.

Certainly; the utility model also can have other various embodiments; under the situation that does not deviate from the utility model spirit and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the utility model, but these corresponding changes and distortion all should belong to the protection domain of claim of the present utility model.

Claims (10)

1. the witness plate of a high-end server controller chip is characterized in that, comprising:

First bus, second bus, input terminal, lead-out terminal, be used to preserve the ROM (read-only memory) of the initialization information of chip logic to be verified;

Respectively be used to load two fpga chip groups of a controller chip group logic bit stream;

Each fpga chip group links to each other with described first, second bus, ROM (read-only memory), power supply respectively; Each input end/output terminal of organizing FPGA links to each other with described input/output terminal.

2. witness plate as claimed in claim 1 is characterized in that, also comprises:

Reset button links to each other with the reset pin of the fpga chip of each fpga chip group.

3. witness plate as claimed in claim 2 is characterized in that, described reset button in comprise following any or appoint several:

Cold reset button, hard reset button, debug reset button, acquiescence reset button, warm reset button.

4. witness plate as claimed in claim 1 is characterized in that, also comprises:

Calibrating terminal links to each other with the test pin of the fpga chip of each fpga chip group.

5. witness plate as claimed in claim 1 is characterized in that, also comprises:

Be used for the logic register of fpga chip is carried out the serial ports of read and write access, link to each other with each fpga chip group.

6. witness plate as claimed in claim 1 is characterized in that, also comprises:

Be used for that fpga chip is carried out the joint test behavior that logic inserts the scan chain built-in self testing and organize jtag interface, link to each other with each fpga chip group.

7. witness plate as claimed in claim 1 is characterized in that, also comprises:

The plug-in unit that connects that is connected with described input, lead-out terminal.

8. as each described witness plate in the claim 1 to 7, it is characterized in that each described fpga chip group comprises:

First fpga chip and second fpga chip;

Described first fpga chip in each group links to each other with described first, second bus and power supply, and input end links to each other with described input terminal, the input end cascade of described second fpga chip in output terminal and this group; The output terminal of described second fpga chip in each group is connected to described lead-out terminal;

First, second fpga chip in each group all links to each other with described ROM (read-only memory), reads or preserve described initialization information.

9. witness plate as claimed in claim 8 is characterized in that:

Described ROM (read-only memory) is a plurality of; First, second fpga chip in each group is connected respectively to different ROM (read-only memory), or is connected to identical a plurality of ROM (read-only memory).

10. witness plate as claimed in claim 8 is characterized in that, also comprises:

Be used to carry out the toggle switch of clock selecting, with each the group in first fpga chip link to each other.

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